JPH08340054A - Read-only memory device and its manufacture - Google Patents

Abstract

PURPOSE: To obtain a mask ROM constituted in such a planar structure that can operate at a high speed. CONSTITUTION: Word lines 28 which are composed of belt-like low-resistance metallic layers extended in the direction perpendicular to the extending direction of bit lines 26 are formed on a P-type silicon substrate 20. Polysilicon gate electrodes 32 which are separated from each at every memory transistor and separated from the substrate 20 by gate oxide films 30 are formed in the areas between each adjacent bit lines 26 and 26. A silicon oxide film 34 is formed on the gate electrodes 32 except the electrode 32 which is turned on in accordance with information to be stored when the memory transistor on the electrode 32 is selected and on which a contact hole 36 is formed and the gate electrode 32 of the memory transistor is connected to the word lines 28 through the contact hole 36.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM (read only memory) device called a planar cell structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art A planar structure mask ROM can be miniaturized because there is no element isolation region in the memory region by the selective oxidation method (LOCOS), and only one contact is required for a plurality of memory transistors. It has the advantage of becoming. An example of a memory area of a mask ROM having such a planar structure is shown in FIG. In the memory region separated by the field oxide film 4 and the element isolation layer 6 on the surface of the P-type silicon substrate 2, bit lines 8 made of N-type diffusion layers parallel to each other extending in strips in the direction perpendicular to the paper surface are formed. On the substrate 2, there are formed a plurality of word lines 12 extending in the direction orthogonal to the bit lines 8 via the gate oxide film 10 in a strip shape and arranged in parallel to each other in the direction perpendicular to the plane of the drawing. The word line 12 is composed of a polysilicon layer or a refractory metal silicide layer whose resistance is lowered by introducing impurities. An oxide film 10a thicker than the gate oxide film 10 is formed between the bit line 8 and the word line 12.

In the mask ROM having such a planar structure, the resist pattern 1 is formed according to the information to be stored.
Using 6 as a mask, an impurity 14 such as boron is implanted to increase the threshold voltage in the channel region of a predetermined memory transistor. 14a is a boron ion implanted in a predetermined channel region. 16 is a resist pattern for performing the core injection.

[0004]

The mask ROM shown in FIG. 1 has the following problems. (1) Since it has long bit lines and word lines, resistance and capacitance increase, which hinders speeding up. (2) Diffusion layer 8 of the bit line to be the source / drain
Is formed before the word line 12 also serving as the gate electrode, and the word line 12 intersects with the bit line 8. Therefore, it is difficult to adopt the LDD structure or the salicide structure. (3) Since data writing is performed by ion implantation (core implantation) into the channel region, junction leakage and junction capacitance increase. Further, due to the sneak from the core injection into the surrounding memory transistors, ions also enter the channel region of the memory transistor in which the core injection is not performed, and the drive current is reduced. (4) In addition to the core injection, there is a method of writing data by a contact method in which a word line and a bit line are connected according to information to be stored, but in that case, the memory cell size becomes large and the process becomes complicated. Such problems occur. It is an object of the present invention to provide a mask ROM having a planar structure that solves such a problem, and a method for manufacturing the mask ROM.

[0005]

In a mask ROM having a planar structure according to the present invention, band-shaped impurity diffusion layers are formed on a semiconductor substrate surface in parallel with each other at equal intervals to form bit lines, and the bit lines are formed on the substrate. A word line is formed of a plurality of strip-shaped low-resistance metal layers that are parallel to each other in the direction intersecting with the impurity diffusion layer and are equally spaced, and a substrate is formed in a region sandwiched between adjacent bit lines between the word line and the substrate. A gate electrode composed of a polysilicon layer or a polycide layer (a high-melting-point metal silicide layer is laminated on a polysilicon layer) is formed between the gate insulating film, and the MOS has a separate gate electrode. A memory transistor array consisting of transistors is configured, and the area between the memory transistor gate electrode and the word line follows the information to be stored. , Or they are electrically connected, or through an insulator layer are insulated by a contact.

In order to reduce the resistance of the bit line, it is preferable that a silicide layer is formed on the surface of the impurity diffusion layer of the bit line. In order to reduce the resistance of the word line, the word line is preferably made of an aluminum-based metal layer, a refractory metal layer or a refractory metal silicide layer. It is preferable that among the gate electrodes of the memory transistor, electrons are injected into the gate electrode that is not electrically connected to the word line to increase the threshold voltage of the memory transistor.

The manufacturing method of the present invention includes the following steps (A) to (E). (A) A polysilicon layer or a polycide layer is formed as a conductor layer in a memory region on the surface of a semiconductor substrate via a gate insulating film, and the conductor is formed so as to form openings having strip portions that are parallel to each other and are equally spaced. A step of patterning the layer by lithography and etching, (B) a step of ion-implanting an impurity for forming a bit line into the substrate by using the pattern of the conductor layer as a mask, and (C) of the conductor layer, Patterning by lithography and etching so that only the portion that will be the gate electrode of the memory transistor remains,
(D) a step of forming a first interlayer insulating film and forming a contact hole on a gate electrode of a memory transistor which should be turned on when read according to information to be stored;
(E) A step of forming a metal film on the first interlayer insulating film, patterning the metal film by lithography and etching to form a word line, and connecting it to a gate electrode through a contact hole.

In order to reduce the resistance of the bit line, sidewall spacers made of an insulator are formed on the side surfaces of the conductor layer pattern between steps (B) and (C) to form a substrate surface on which the bit line is formed and It preferably includes a salicide step of forming a silicide layer on the surface of the conductor layer.

The present invention is also applied to a method of simultaneously forming transistors in the peripheral circuit section on the same substrate. At that time, the contact holes in the step (D) are formed at the same time in the peripheral circuit portion, and the first layer metal wiring is formed in the peripheral circuit portion by patterning the metal film in the step (E). It can be kept low.
The contact hole formation in the step (D) may be performed in a step different from the contact hole formation in the peripheral circuit section. As a result, the process of forming the contact hole in the memory region can be optimized, so that the structure in which the contact hole overlaps with the gate electrode can be achieved, that is, the gate electrode can be made smaller, and thus miniaturization can be achieved. Be advantageous. In that case, the metal film in the step (E) is a refractory metal film or a refractory metal silicide film, and the metal wiring obtained by patterning the metal film is peculiar to the memory region, and a metal different from that in the peripheral circuit portion is used. A metal wiring is formed by the layers.

In order to shorten the period from product specification determination to product completion, a semiconductor substrate wafer on which the first interlayer insulating film has been formed is prepared as a master slice, and the master slice is prepared according to the user's specifications. It is preferable to employ a master slice method starting from formation of a contact hole on the gate electrode of the memory transistor according to the information to be stored.

[0011]

In the memory transistor, since the gate electrode is formed separately from the word line, the gate electrode is formed of a polysilicon layer or a polycide layer as usual, and the word line has a lower resistance aluminum-based metal layer and a higher melting point. Can be a metal layer or a refractory metal silicide layer,
In addition, a silicide layer can be formed on the surface of the bit line. In this way, the resistance of the bit line and the word line can be reduced, and since core injection is not performed, deterioration of device characteristics due to core injection is eliminated and a high-speed ROM can be realized.

[0012]

FIG. 2 shows a first embodiment. (A) is a plan view and (B) is a sectional view taken along the line XX ′. Although the memory area and the peripheral circuit are formed on the same substrate, only the memory area is shown in the embodiment because the peripheral circuit has a normal structure. On the surface of the P-type silicon substrate 20, in the memory region separated by the field dope layer 22 and the field oxide film 24, strip-shaped N-type diffusion layers 26 extending in the direction perpendicular to the plane of the drawing and parallel to each other at equal intervals are formed. Make up the line. Bit line 26 on the substrate
The word line 28 is formed of a plurality of strip-shaped low-resistance metal layers that extend in the in-plane direction in a direction orthogonal to the extending direction of, and are arranged in parallel with each other and in the direction perpendicular to the paper surface at equal intervals. The word line 28 is made of aluminum, an aluminum alloy containing a small amount of silicon in aluminum, T, or the like.
It is composed of a refractory metal such as i or Mo or a refractory metal silicide such as WSi ₂ . A gate electrode 32 formed of a polysilicon layer or a polycide layer is formed between the word line 28 and the substrate 20 and in a region sandwiched between the adjacent bit lines 26 and 26 with the gate oxide film 30 interposed therebetween. Has been formed. The gate electrode 32 is patterned in a shape separated for each memory transistor.

A silicon oxide film 34 is formed as an interlayer insulating film from above the gate electrode 32, and it should be turned on when the memory transistor is selected according to the information to be stored. A hole 36 is formed, and the gate electrode 32 of the memory transistor and the word line 28 are connected via the contact hole 36. A second interlayer insulating film 38 such as a PSG (phosphorus glass) film or a BPSG (boron / phosphorus glass) film is formed from above the word line 28, a through hole 40 is formed in the interlayer insulating film 38, and an interlayer insulating film is formed. The metal wiring of the second layer made of aluminum alloy or the like formed on the wiring 38 is connected to the word line 28 through the through hole 40. The bit lines 26 are alternately arranged so that one of the adjacent bit lines 26 serves as a drain and the other one thereof serves as a source, and a metal wiring 42 is also connected to each of them via a contact hole 44 of the interlayer insulating films 34 and 38.

FIG. 3 shows a second embodiment. The plan view is the same as FIG. 2 is different from the embodiment of FIG. 2 in that a sidewall spacer 46 made of a high temperature oxide film or a silicon nitride film is formed on the side surface of the gate electrode.
The refractory metal silicide layer 48 is formed on the gate electrode 32, and the refractory metal silicide layer 50 is also formed on the surface of the N-type diffusion layer 26 of the bit line.

Such a high melting point metal silicide layer 48,
The process of forming 50 is known as a salicide process. After forming the sidewall spacer 46, a refractory metal film is deposited on the exposed surface of the gate electrode 32 and the surface of the N-type diffusion layer 26, and a reaction is performed by heat treatment. Thus, the silicide layers 48 and 50 are formed.

FIG. 4 shows a first manufacturing method, and shows a method for manufacturing the embodiment of FIG.
(A) to (D) show the process in the order of steps by a plan view, and (a) to (d) show cross-sectional views at positions of respective chain lines from (A) to (D). It is a thing. (A) P-type silicon substrate 20 and field dope layer 22
A field oxide film 24 is formed to separate the peripheral circuit area from the memory area. After forming a gate oxide film 30 of 50 to 500 Å on the substrate 20, a conductor layer 32 made of a polysilicon film or a polycide film whose resistance has been lowered by introducing impurities is deposited to a thickness of 1000 to 5000 Å, and then the lithography is performed. By etching, openings 33 are formed which are parallel to each other and have strip portions at equal intervals. As a result, the conductor layer 32 is left in the memory region other than the bit line portion. Conductor layer 32 for forming the N-type diffusion layer of the bit line
With the pattern of as a mask, arsenic ions, for example
The substrate 20 is implanted under the conditions of 100 KeV and 1 × 10 ¹⁴ to 1 × 10 ¹⁶ / cm ² . 8a is the implanted N-type impurity.

(B) After the entire surface is oxidized, the conductor film 32 is left only at the place to be the gate electrode of the memory transistor,
The other conductor film is removed by etching. By the heat treatment at this time, the N-type impurities implanted in the substrate are activated and the bit line 26 is formed.

(C) After forming the peripheral transistor, a silicon oxide film 34 is deposited to a thickness of 1000 to 10000Å. At this time, it is desirable that the silicon oxide film 34 be buried between the adjacent gate electrodes 32 to be flattened. According to the ROM code, the contact hole 36 is formed only on the gate electrode 32 of the memory transistor which is turned on when selected. At this time, the contact hole of the peripheral circuit portion and the contact hole 44 for the bit line are also formed at the same time. In this embodiment, the contact hole 32 is preferably formed in the same size as or smaller than the gate electrode 32 so as not to be electrically connected to the diffusion layer 26 of the bit line by overetching. Then, a first layer of aluminum alloy film is deposited and patterned by lithography and etching to form word lines 2 in the memory region.
8. In the peripheral circuit section, the first metal wiring layer is formed.

(D) The second interlayer insulating film 38 is formed of a PSG film or a BPSG film, the surface is flattened by densification, and then the through hole 4 for the word line 28 is formed.
Form 0. After that, a second-layer aluminum alloy film is deposited and patterned by lithography and etching to form a second-layer aluminum wiring 42. Then, a passivation film is formed according to a normal process.

When this process is carried out by the master slice method, the silicon oxide film 34 in the step (C) is used.
And the densification for the surface flattening are performed as a master process, and the wafer is prepared as a master slice. Then, if there is an order from the user, the custom process can be started from the process of forming the contact hole 36 according to the information to be stored according to the specifications.

The method shown in FIG. 4 is applied to a mask ROM having a normal single layer polysilicon not having a planar cell structure and two layers of metal wiring.
Compared with the process, only a single patterning of the conductor layer 32 and an ion implantation process for forming the bit line 26 are required, and the mask R that is fine and can operate at high speed is used.
OM can be realized.

As in the embodiment of FIG. 3, bit line 26
To obtain a structure in which the silicide layers 50 and 46 are provided on the surface of the gate electrode 32 and the surface of the gate electrode 32, respectively, the step (B) of FIG.
After that, a high temperature oxide film is formed and etched back to form a sidewall spacer 46, and then a refractory metal film of tungsten, titanium, molybdenum or the like is deposited on the entire surface, and heat treatment is performed to form the silicide layers 50 and 48. After forming, the step of removing unreacted refractory metal with an etching solution may be added.

Although the manufacturing method of FIG. 4 is an example in which the contact hole 36 for the ROM code and the contact hole of the peripheral circuit are formed in the same step, an embodiment in which those contact holes are formed in different steps Will be described as a second manufacturing method. The drawing utilizes FIG. The steps (A) and (B) are the same as in the first manufacturing method.

(C) After forming the peripheral transistor, a silicon oxide film is deposited by the CVD method to a thickness of 500 to 3000 Å, and the contact hole 36 is formed only on the gate electrode of the memory transistor selected by the ROM code and turned on. To form. At this time, no contact hole is formed in the peripheral circuit. Next, a refractory metal film such as tungsten or a refractory metal silicide film such as tungsten silicide is deposited, and then patterned to form the word lines 28. The wiring to be the word line 28 is formed only in the memory area, not in the peripheral circuit.

(D) A PSG film or a BPSG film is deposited as the interlayer insulating film 38 to a thickness of 5000 to 8000 Å, and then densification is performed to flatten it. After that, the contact holes 40 and 44 are formed. At this time, the contact holes of the peripheral circuit are simultaneously formed. After that, the second-layer metal wiring 42 is formed and a passivation film is formed.

In the first manufacturing method, the contact hole 36
Since it is formed at the same time as the contact hole in the peripheral circuit portion, there is a risk of short-circuiting with the underlying substrate or the diffusion layer 26 of the bit line if it is formed so as to protrude from the gate electrode 32. Needed to be larger than size. However, in the second manufacturing method, since the contact hole 36 is formed in a step independent of the contact hole of the peripheral circuit, the etching of the contact hole 32 is brought into contact with the gate electrode 32 and the diffusion layer 2 is formed.
Since it is possible to optimize the depth so as not to contact the gate electrode 6, it is possible to form a structure in which the contact hole overlaps the gate electrode 32, that is, the gate electrode 3
Since 2 can be reduced, further miniaturization can be achieved. Even when the second manufacturing method is applied to the master slice method, the master process can be performed up to the stage where the silicon oxide film 34 is deposited.

In the memory transistor shown in FIGS. 2 and 3, since the gate electrode 32 of the bit not connected to the word line 28 is in a floating state, it is electrically unstable. Therefore, after completing all the process steps, one of the bit lines adjacent to the plurality of bit lines 26 or the metal wiring connected to the bit lines has a GND potential, and the other has a positive potential (for example, 5 to 15 V). By alternately applying the GND potential and the positive potential to the bit line 26 and applying the high potential of 10 V or more to the word line 28, the gate electrode 32 in the floating state is provided.
It is preferable to inject channel hot electrons into.

Alternatively, the bit line 28 may be GN
The word line 28 is set to the D potential or the floating state.
F-N
Electrons may be injected into the floating gate electrode 32 by (Fowler-Nordheim) tunneling. In this way, by injecting and retaining the electrons only in the gate electrode in the floating state, the threshold voltage of the memory transistor of these bits is changed to that of the memory transistor of the bit electrically connected to the word line 28. It becomes higher than the threshold voltage on the positive side and can be stabilized. It is desirable that the threshold voltage of the memory transistor in the floating state is Vcc or higher.

[0029]

According to the present invention, since the word line can be made of a low resistance metal layer such as aluminum or refractory metal silicide, the word line has a low resistance. Moreover, since the lower part of the gate electrode is the conventional N-type polysilicon, the transistor characteristics do not change due to the work function. Since core injection is not used for writing the ROM code, there is no increase in junction leakage or junction capacitance due to core injection. In addition, the driving current does not decrease due to the rounding of the core injection of the adjacent memory transistors. Therefore, deterioration of the characteristics of the memory transistor can be suppressed. Unlike the core injection method, a memory transistor in a completely off state can be formed, so that the voltage of the word line can be increased and the drive current can be increased. Since the salicide technique can be used as in the normal process, the resistance of the bit line can be reduced. As a result of the above, a high-speed mask ROM can be realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a conventional mask ROM having a planar structure.

FIG. 2 is a cross-sectional view showing a mask ROM having a planar structure according to an embodiment.

FIG. 3 is a sectional view showing a mask ROM having a planar structure according to another embodiment.

FIG. 4 is a diagram showing an example showing a manufacturing method,
(A) to (D) show the process in the order of steps by a plan view, and (a) to (d) show cross-sectional views at positions of respective chain lines from (A) to (D). It is a thing.

[Explanation of symbols]

 20 P-type silicon substrate 26 N-type diffusion layer of bit line 28 Word line 30 Gate oxide film 32 Gate electrodes 34, 38 Interlayer insulating film 36 Contact hole for writing ROM code

Claims (9)

[Claims] 1. A bit line is formed by forming strip-shaped impurity diffusion layers parallel to each other on a surface of a semiconductor substrate at equal intervals, and parallel to each other in the direction intersecting the impurity diffusion layers on the substrate at equal intervals. A word line composed of a plurality of strip-shaped low-resistance metal layers is formed, and in a region sandwiched between adjacent word lines between the word line and the substrate, a polysilicon layer or a polycide layer is formed between the substrate and the gate insulating film. A memory transistor array composed of MOS transistors each having a gate electrode formed of a layer and having separate gate electrodes is formed. Between the gate electrode of the memory transistor and the word line, according to the information to be stored, A lead-only that is electrically connected by a contact or insulated through an insulator layer. Memory device. 2. The lead layer according to claim 1, wherein a silicide layer is formed on the surface of the impurity diffusion layer of the bit line.
Only memory device. 3. The read-only memory device according to claim 1, wherein the word line comprises an aluminum-based metal layer, a refractory metal layer or a refractory metal silicide layer. 4. The gate electrode of the memory transistor, which is not electrically connected to the word line, is injected with electrons to increase the threshold voltage of the memory transistor. Read-only memory device. 5. A method for manufacturing a read-only memory device, which includes the following steps (A) to (E). (A) A polysilicon layer or a polycide layer is formed as a conductor layer in a memory region on the surface of a semiconductor substrate via a gate insulating film, and the conductor is formed so as to form openings having strip portions that are parallel to each other and are equally spaced. Patterning the layer by lithography and etching, (B) ion-implanting impurities for forming a bit line into the substrate using the pattern of the conductor layer as a mask, (C) of the conductor layer, A step of patterning by lithography and etching so that only the portion to be the gate electrode of the memory transistor remains, (D) forming a first interlayer insulating film, and turning on when read according to the information to be stored Step of forming a contact hole on the gate electrode of the memory transistor, (E) forming a metal film on the first interlayer insulating film Then, the metal film is patterned by lithography and etching to form a word line, which is connected to the gate electrode through the contact hole. 6. Between the steps (B) and (C), a side wall spacer of an insulator is formed on a side surface of the conductor layer pattern, and a substrate surface on which a bit line is formed and a surface of the conductor layer. The method for manufacturing a read-only memory device according to claim 5, further comprising a salicide step of forming a silicide layer on the substrate. 7. A method of simultaneously forming transistors in a peripheral circuit portion on the same substrate, wherein the contact hole formation in the step (D) is also performed in the peripheral circuit portion at the same time, and the patterning of the metal film in the step (E) is performed. 7. The method for manufacturing a read-only memory device according to claim 5, wherein the first-layer metal wiring is formed in the peripheral circuit portion by the method. 8. A method of simultaneously forming transistors in a peripheral circuit portion on the same substrate, wherein the contact hole formation in the step (D) is performed in a step different from the contact hole formation in the peripheral circuit portion, and the step (E) is performed. ) Is a refractory metal film or refractory metal silicide film, and the metal wiring obtained by patterning it is peculiar to the memory area, and the metal wiring is formed by a different metal layer from that in the peripheral circuit section. 7. The method for manufacturing the read-only memory device according to claim 5, wherein. 9. A semiconductor substrate wafer on which a first interlayer insulating film has been formed is prepared as a master slice, and a contact hole is formed on a gate electrode of a memory transistor according to information to be stored according to specifications from a user. The master slice method starting from 5.
7. The method for manufacturing the read-only memory device according to 7 or 8.