JP3434630B2 - Mask ROM device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask ROM device and a method for manufacturing the same, and more particularly to a depletion type memory transistor in which a source and a drain are electrically connected to each other even when a driving voltage is not applied to a gate electrode, and a driving voltage is applied to a gate electrode. The present invention relates to a NAND-type mask ROM device that stores information by a combination with an enhancement-type memory transistor that does not conduct between a source and a drain when there is no state, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a method in which a program according to information to be stored in a NAND type mask ROM is performed before forming a gate electrode, a period TAT (Turn Around) from an order to a product is completed.
There is a problem that Time) becomes long. Therefore, as a manufacturing method for shortening the TAT, some methods have been proposed in which after the gate electrode is formed, the source / drain of the memory cell transistor is short-circuited by a conductor layer that straddles the gate electrode to program it as a depletion type. .

In the method of short-circuiting the source and drain with a metal wiring such as aluminum instead of the depletion type transistor, a metal wiring layer for programming is formed under a normal metal wiring (see Japanese Patent Laid-Open No. 9157/1985). ). For the metal wiring for programming, short the source / drain and leave the metal wiring only at the gate electrode that is to be the depletion type, or if all memory transistors are short-circuited and only the memory transistor that is to be the enhancement type. Two types of wire breaks have been introduced. A method of short-circuiting all memory transistors and disconnecting only the enhancement type is also disclosed in JP-A-2-194648. It is also shown that a low resistance polysilicon layer or a silicide layer is used in place of the metal wiring (see Japanese Patent Laid-Open No. 4-257259).

[0004]

SUMMARY OF THE INVENTION In these proposed methods, a memory transistor of a depletion type is provided between a gate electrode of a word line and a normal metal wiring in accordance with information to be stored. Another additional wiring layer is required. Therefore, the unevenness of the device surface becomes remarkable, and problems such as disconnection and short circuit of metal wiring and cracking of the passivation film occur with miniaturization.

Further, since the surface of the source / drain region of the enhancement type transistor, the bit contact part, and the contact part between the depletion type conductor layer and the source / drain remain as the impurity diffusion layer, they are accompanied by miniaturization. There is a problem that the sheet resistance and the contact resistance increase remarkably and the operation speed of the device decreases.

Therefore, the present invention is a NAND type mask ROM.
Is the same as the one proposed in that the source / drain of the memory transistor to be depletion type is programmed by short-circuiting with the conductor layer that straddles the gate electrode, An object of the present invention is to provide a NAND type mask ROM capable of reducing the resistance of the source / drain and reducing the contact resistance without significantly increasing the unevenness of the base of the metal wiring to be formed, and a manufacturing method thereof. Is.

[0007]

According to the present invention, a plurality of gate electrodes extending parallel to each other on a semiconductor substrate and a source / source provided on the semiconductor substrate between the gate electrodes in a direction orthogonal to the extending direction of the gate electrodes are provided. A NAND-type mask ROM device having a series of MOS memory transistors connected in series with a drain impurity region, wherein a source electrode and a drain electrode sandwiching a gate electrode are short-circuited by a conductor layer that straddles the gate electrode. And the conductor layer is a silicide layer formed on the silicon of the substrate, and the silicide formed on the polysilicon sidewall formed on the side surface of the gate electrode via the insulating film. Layer and a silicon cap layer formed on a polysilicon cap layer formed on the upper surface of the gate electrode through an oxidation resistant insulating layer. In which successive consisting De layer.

According to the method of the present invention for manufacturing the mask ROM device, a plurality of gate electrodes extending in parallel with each other via a gate oxide film are formed on a semiconductor substrate, and then a gate electrode to be a depletion type memory transistor is formed. Is covered with polysilicon, and a silicon oxide film is covered around the gate electrode used as the enhancement type memory transistor to expose the substrate silicon in the source / drain regions, and then a refractory metal film is deposited and heat treated. Is performed to form a silicide layer on the polysilicon and the substrate silicon in a self-aligned manner.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION The gate electrode of a memory transistor is composed of a polysilicon layer formed on a gate oxide film or a polycide layer on which a silicide layer is further formed. A cap layer is formed via a conductive insulating layer, and a sidewall is formed on the side surface of the gate electrode via an insulating film, so that the source and drain do not conduct when the drive voltage is not applied to the gate electrode. Type memory transistor, the cap layer and sidewalls are insulators, and even if the drive voltage is not applied to the gate electrode, the
In a depletion type memory transistor in which drains are electrically connected, a cap layer and a sidewall are made of polysilicon, and a silicide layer is formed as a conductor layer for programming on the polysilicon. In order to reduce the resistance of the source / drain and the contact resistance, it is preferable that the source / drain regions of all the memory transistors and peripheral transistors are silicided.

In the manufacturing method, a polysilicon layer is formed on a semiconductor substrate via a gate oxide film, an oxidation resistant insulating layer is formed on the polysilicon layer, and a polysilicon layer is formed on the polysilicon layer, and then the layer on the gate oxide film is formed. A gate electrode to be a depletion type memory transistor by patterning into a gate electrode shape, forming a polysilicon film with the surface of the gate electrode covered with an oxide film and performing etch back to form a polysilicon sidewall on the side surface of the gate electrode. Oxidation treatment is performed with only the surface of the substrate covered with the oxidation-resistant insulating film, and the oxide film is etched back until the substrate silicon in the source / drain regions is exposed. Covered with polysilicon,
A silicon oxide film is formed around the gate electrode of the enhancement type memory transistor to expose the substrate silicon in the source / drain regions.

[0011]

1 shows an embodiment of a NAND type mask ROM of the present invention. (A) is a schematic plane, (B) is X of (A)
It is sectional drawing in the -X 'line position. On the silicon substrate 2, a gate electrode 6 which extends in parallel with each other via a gate oxide film 4 and also serves as a plurality of word lines is formed of a polysilicon layer whose resistance is lowered by introducing an N-type impurity. A source / drain 8 of an N-type impurity diffusion layer is formed on the substrate 2 between the gate electrodes in a direction orthogonal to the extending direction of the gate electrode 6. The gate electrode 6 is continuous for a plurality of memory transistors, and a silicon nitride film 10 is formed on the gate electrode 6 as an oxidation resistant insulating film.

Enhancement-type memory transistor 1
2e, the gate electrode 6 and the silicon nitride film 10 on it
Is surrounded by a silicon oxide film 14. on the other hand,
In the depletion type memory transistor 12d, a polysilicon cap layer 16 is further formed on the silicon nitride film 10, a polysilicon side wall 20 is formed on the side surface of the gate electrode via a silicon oxide film 18, and a polysilicon cap on the gate electrode is formed. A continuous silicide layer 22 is formed on the layer 16, the polysilicon sidewall 20 and the source / drain 8 to short-circuit the source and drain of the memory transistor 12d.

This memory transistor has an LDD structure, and a low-concentration impurity layer 8a is formed below the sidewalls 20 and 14, and a high-concentration impurity layer 8b is formed outside the low-concentration impurity layer 8a. Since the silicide layer 22 of the depletion type memory transistor has a salicide structure formed in a self-aligned manner, the process is simple as compared with the case where a conductor layer is separately deposited as in the method proposed for short circuit, and the film is formed. The thickness is also small, and the level difference on the surface of the interlayer insulating film on which the normal metal wiring is formed is also small.

Next, a method for manufacturing this embodiment will be described with reference to FIGS. (A) P-type silicon substrate 2 as is normally done
A gate oxide film 4 is formed on the surface of the substrate by thermal oxidation, and an N-type polysilicon layer 6 for a gate electrode is formed thereon. The polysilicon layer 6 may be formed by depositing a polysilicon layer containing no impurities by a CVD method and then introducing an N-type impurity such as arsenic or phosphorus by an ion implantation method or a diffusion method. It may be deposited as a polysilicon layer containing. The steps up to this point are usually performed.

A silicon nitride film 10 having a thickness of about 1000 Å is deposited on the polysilicon layer 6 by a CVD method, and an N-type polysilicon layer 16 to be a cap layer is formed on the silicon nitride film 10 by several tens.
Deposit to a thickness of 0-2000Å. Polysilicon layer 16
Similarly to the polysilicon layer 6, a polysilicon layer containing no impurities may be deposited by the CVD method, and then N-type impurities such as arsenic and phosphorus may be introduced by the ion implantation method or the diffusion method. It may be deposited as a polysilicon layer containing such impurities. Here, a silicon oxide film may be further formed between the silicon nitride film 10 and the polysilicon layer 16 in order to reduce stress.

(B) In order to form a gate electrode which also serves as a word line, strip-shaped resist patterns parallel to each other are formed, and the polysilicon layer 16, the silicon nitride film 10 and the polysilicon layer 6 are sequentially etched using the resist patterns as a mask. By doing so, band-shaped gate electrodes parallel to each other are formed. At this time, the gate oxide film 4 is removed in the region between the gate electrodes to expose the silicon substrate 2.

Next, the silicon oxide film 18 is formed by thermal oxidation so as to have a film thickness of several tens to several hundreds Å on the silicon substrate 2. The silicon oxide film 18 is formed so as to cover the silicon substrate 2 and the gate electrode.
After that, ion implantation with arsenic or phosphorus is performed to form a low-concentration impurity layer of the LDD structure of the source / drain. 8a represents the implanted impurity ion layer.

(C) A polysilicon film is formed on the entire surface by 1000 to 1000.
Deposited by the CVD method to a thickness of 3000Å,
By performing etch back, the polysilicon sidewall 2 is formed on the side surface of the gate electrode through the silicon oxide film 18.
Form 0.

(D) A silicon nitride film is deposited on the entire surface by the CVD method to a thickness of several hundred liters to 2,000 liters. The silicon nitride film 30 is patterned by photolithography and etching so that the silicon nitride film 30 remains only in the memory transistor portion where the depletion type is desired. Figure 3
The hatched portion in (D) is the silicon nitride film 30.
Is the remaining part. The silicon nitride film on the memory transistor to be enhancement type is removed by etching. At this point, the conditions are set so that all memory transistors are of the enhancement type.

(E) Oxidation is performed to form the silicon nitride film 30.
The polysilicon side wall 22 and the polysilicon cap layer 16 above the gate electrode of the memory transistor which is not covered with the above, that is, the memory transistor which is desired to be the enhancement type are all changed to the silicon oxide film 14. In this oxidation step, since the polysilicon is composed of columnar grains, the oxidation selectively advances in the direction perpendicular to the substrate surface, and the oxidation in the in-plane direction of the substrate, that is, in the lateral direction is suppressed, and the silicon nitride film is almost formed. Oxidation and non-oxidation are distinguished according to 30 patterns.

Also in the enhancement type memory transistor in which the polysilicon cap layer 16 and the polysilicon sidewall 22 are oxidized, the silicon nitride film 10 which is an oxidation resistant insulating film is provided on the polysilicon layer 6 of the gate electrode. Therefore, the silicon nitride film 1
0 prevents the diffusion of oxygen molecules, the polysilicon layer 6 of the gate electrode is not oxidized, and the polysilicon cap layer 1 of the upper layer is not oxidized.
Only 6 and the polysilicon sidewall 22 are oxidized.

After that, the silicon nitride film 30 is removed and the silicon oxide film is partially etched to expose the surface of the silicon substrate in the active region and the polysilicon cap layer 16 which is the upper layer of the depletion type memory transistor. The hatched portion in FIG. 3 (E) represents the portion where the upper polysilicon cap layer 16 and the polysilicon sidewall 20 remain.

(F) N-type impurity implantation of phosphorus or arsenic for the source / drain high-concentration impurity layer 8b is performed, and then heat treatment for activating the impurity layers 8a and 8b is performed. After that, a titanium film is deposited on the entire surface and annealed to form the substrate silicon or polysilicon layers 16 and 20.
After performing a silicidation reaction by titanium and silicon in the portion in contact with, only unreacted titanium is removed with an alkaline solution. As a result, the drain 8-polysilicon sidewall 20-upper polysilicon cap layer 16-polysilicon sidewall 20-source 8 of the depletion type memory transistor is connected by a continuous silicide layer, and the memory transistor is short-circuited. become.

The surface of the impurity diffusion layer (source / drain) 8 in the active region is also silicided, and the resistance of the bit line and the resistance of the bit contact are reduced. After that, an interlayer insulating film is formed according to a known process, contact holes are opened, metal wiring is formed on the interlayer insulating film, and a passivation film is formed to complete the semiconductor device.

[0025]

According to the present invention, the short circuit between the source and the drain of the depletion type memory transistor is formed not by the separately deposited conductor layer such as aluminum or polysilicon layer but by the conductor layer by the salicide process. Therefore, the flatness of the device is realized,
It is possible to suppress disconnection of the metal wiring formed above it and generation of cracks in the passivation film. Further, in the present invention, since the diffusion layer is entirely silicided, the sheet resistance of the bit diffusion layer and the contact resistance of the bit contact are reduced, and the device speed can be increased. Since the polysilicon layer, which is the source of the conductor layer for short-circuiting between the source and the drain, is formed around the gate electrode by self-alignment, miniaturization and high integration are possible. Further, the polysilicon layer in the portion which is not desired to be silicidized is oxidized to form a silicon oxide film. However, since the oxidation resistant layer is provided on the polysilicon layer of the gate electrode, even if sufficient oxidation is performed. The gate electrode is not oxidized.

[Brief description of drawings]

FIG. 1 is a diagram showing a mask ROM of one embodiment,
(A) is a schematic plan view and (B) is a cross-sectional view taken along the line XX ′.

FIG. 2 is a process sectional view showing a first half of a process of an embodiment of the manufacturing method of the present invention.

FIG. 3 is a diagram showing the latter half of the embodiment of the manufacturing method,
(D) to (F) show respective steps as plan views, and (d) to (f) show sectional views taken along line XX 'of each plan view.

[Explanation of symbols]

2 P-type silicon substrate 4 Gate oxide film 6 Polysilicon layer of gate electrode 8 Source / Drain 10 Silicon nitride film 16 Polysilicon cap layer 18 Silicon oxide film 20 Polysilicon sidewall 22 Silicide layer 30 Silicon nitride film

Claims (5)

(57) [Claims] 1. A plurality of gate electrodes extending parallel to each other on a semiconductor substrate and a source / drain impurity region provided on the semiconductor substrate between the gate electrodes in a direction orthogonal to the extending direction of the gate electrodes are connected in series. In a NAND-type mask ROM device configured with a MOS memory transistor array formed as described above, programming is performed depending on whether or not a source electrode and a drain electrode that sandwich a gate electrode are short-circuited by a conductor layer that straddles the gate electrode. In addition, the conductor layer is a silicide layer formed on the silicon of the substrate, a silicide layer formed on the polysilicon sidewall formed on the side surface of the gate electrode via an insulating film, and an oxidation resistance on the upper surface of the gate electrode. Of a silicide layer formed on a polysilicon cap layer formed through a conductive insulating layer Mask ROM device, characterized in that the at it. 2. The gate electrode of the memory transistor is composed of a polysilicon layer formed on a gate oxide film or a polycide layer having a silicide layer formed on the polysilicon layer, and the gate electrode has oxidation resistance. A cap layer is formed via an insulating layer, and a sidewall is formed on the side surface of the gate electrode via an insulating film, so that the source and drain do not conduct when the drive voltage is not applied to the gate electrode. In the memory transistor of, the cap layer and the sidewall are insulators, and in the depletion type memory transistor in which the source and drain are electrically connected even when the driving voltage is not applied to the gate electrode, the cap layer and the sidewall are made of polysilicon. On the polysilicon as a conductor layer for the programming. Mask ROM device of claim 1, the side layer is formed. 3. The mask ROM device according to claim 1, wherein the source / drain regions of all memory transistors and peripheral transistors are silicided. 4. An enhancement type memory transistor in which a plurality of gate electrodes extending in parallel to each other via a gate oxide film are formed on a semiconductor substrate, and then the gate electrode to be a depletion type memory transistor is covered with polysilicon. After covering the gate electrode with a silicon oxide film to expose the substrate silicon in the source and drain regions, deposit a refractory metal film and heat treat it on the polysilicon and substrate silicon. A method of manufacturing a mask ROM device, which comprises forming a silicide layer in a self-aligned manner. 5. After forming a polysilicon layer on a semiconductor substrate via a gate oxide film, an oxidation resistant insulating layer thereon, and a polysilicon layer thereon, the layer on the gate oxide film is formed into a gate electrode shape. Then, a polysilicon film is formed with the gate electrode surface covered with an oxide film and etched back to form a polysilicon sidewall on the side surface of the gate electrode. Only the surface of the gate electrode to be the depletion type memory transistor is formed. Is covered with an oxidation-resistant insulating film, and is oxidized, and the oxide film is etched back until the substrate silicon in the source / drain regions is exposed. Cover, around the gate electrode to be the enhancement type memory transistor with a silicon oxide film, Method for manufacturing a mask ROM according to claim 4, while exposing the substrate silicon over scan and drain regions.