JPH06310733A - Fabrication of semiconductor memory - Google Patents

Abstract

PURPOSE:To remove an ONO film, which is not used in the peripheral circuit region, by etching without causing any damage on a substrate in the fabrication process of a flash memory. CONSTITUTION:When a first polysilicon film 103 is formed on a tunnel insulation film 102 formed on a substrate 100 and then it is patterned in a cell array region to form a floating gate 103', the peripheral circuit region is also covered by a resist 104 and the first polysilicon film 103 is left therein. Under that state, an ONO film 105 is formed on the entire surface. When the ONO film 105 is removed by dry etching from the peripheral circuit region, the underlying first polysilicon film 103 prevents the thin oxide tunnel insulation film 102 from being etched to cause a damage on the substrate 100.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, which is particularly suitable for application to a method for manufacturing a floating gate type nonvolatile semiconductor memory device having a composite gate structure of a floating gate and a control gate. Is.

[0002]

2. Description of the Related Art Conventionally, a polycrystalline silicon two-layer process has been used in a manufacturing process of a floating gate type nonvolatile semiconductor memory device. This conventional polycrystalline silicon 2
The layer process will be described with reference to FIGS. 3 and 4 by taking as an example a method of manufacturing a flash memory such as a batch erase EEPROM.

In each of FIGS. 3 and 4, a cell array region for forming a memory cell is shown on the left side, and a peripheral circuit region for forming a normal MOS transistor is shown on the right side.

First, as shown in FIG. 3A, a field oxide film 201 is formed on the surface of a silicon substrate 200 by the LOCOS method, and then tunnel insulation made of a silicon oxide film having a thickness of about 100 Å is formed in an element formation region. The film 202 is formed. Next, the first polycrystalline silicon film 203 is formed on the entire surface.
In the cell array region for depositing and processing it into a floating gate pattern.
To form a pattern.

Next, as shown in FIG. 3B, the first polycrystalline silicon film 20 is formed using the resist 204 as a mask.
3 is selectively etched to remove the first polycrystalline silicon film 203 in the peripheral circuit region and a floating gate 203 'is formed in the cell array region. After that, an ONO film 205 having a film thickness of about 200 Å is formed on the entire surface.

Next, as shown in FIG. 3C, the entire cell array region is covered with a resist 206, and the resist 2
The ONO film 205 in the peripheral circuit region is removed by dry etching using 06 as a mask.

Next, as shown in FIG. 3D, after removing the resist 206, the tunnel insulating film 2 in the peripheral circuit region is formed.
02 is removed.

Next, as shown in FIG. 4A, a gate insulating film 207 made of a silicon oxide film is formed in the peripheral circuit region.

Next, as shown in FIG. 4B, a second polycrystalline silicon film 208 is deposited on the entire surface.

After that, the second polycrystalline silicon film 208 is processed into a control gate pattern in the cell array region, and the second polycrystalline silicon film 208 is processed in the peripheral circuit region.
Is processed into the pattern of the gate electrode of the MOS transistor. Then, after impurity diffusion is performed on the silicon substrate 200 to form source / drain diffusion layers in the respective regions, an interlayer insulating film is formed and necessary wirings are formed to manufacture a flash memory.

[0011]

In the conventional polycrystalline silicon two-layer process described above, when the ONO film 205 in the peripheral circuit region is removed by dry etching in the step shown in FIG. 3C, the ONO film 205 is removed. Since the base is the tunnel insulating film 202 made of a thin silicon oxide film,
The selectivity of the tunnel insulating film 202 with respect to the dry etching of the ONO film 205 is low, and as a result, the tunnel insulating film 202 may be etched by this dry etching, which may further damage the silicon substrate 200. It was

Therefore, the MOS formed in the peripheral circuit region
There is a problem that the characteristics of the transistor deteriorate.

Therefore, an object of the present invention is a semiconductor capable of reliably removing an ONO film in a peripheral circuit region without damaging a silicon substrate in a polycrystalline silicon two-layer process for manufacturing a flash memory or the like. A method of manufacturing a memory device is provided.

[0014]

In order to solve the above problems, according to the present invention, a first region for forming an element having a structure in which two layers of polycrystalline silicon gates are stacked with an insulating film interposed therebetween is provided. A method of manufacturing a semiconductor memory device, comprising: a second region forming an element having a single-layer polycrystalline silicon gate; a first insulating film on a semiconductor substrate in the first region and the second region; And a step of forming a first polycrystalline silicon film on the first insulating film, covering the entire second region, and forming a first gate film in the first region. A step of forming a first resist on the pattern; a step of selectively removing the first polycrystalline silicon film using the first resist as a mask; Before the step of forming the second insulating film First forming a second resist to cover the entire area, the second insulating film in the second region of the second resist as a mask and the first
Removing the polycrystalline silicon film, removing the second resist, removing the first insulating film in the second region, and removing the first insulating film in the second region on the semiconductor substrate. A step of forming a third insulating film, a step of forming a second polycrystalline silicon film on the entire surface, and a step of forming the second polycrystalline silicon film in the pattern of the second gate in the first region, Each of the second regions has a step of processing into a third gate pattern.

According to another aspect of the present invention, there is provided a device having a first region and a single-layer polycrystalline silicon gate forming a device having a structure in which two-layer polycrystalline silicon gates are stacked with an insulating film interposed therebetween. In a method of manufacturing a semiconductor memory device having a second region to be formed, a step of forming a first insulating film on a semiconductor substrate in the first region and the second region, and the first insulating film. Forming a first polycrystalline silicon film on the film, covering the entire second region, and forming a first gate pattern in the first region in the first region.
The step of forming the resist, the step of selectively removing the first polycrystalline silicon film by using the first resist as a mask, and the step of removing the first resist, and then the second insulating film over the entire surface. And a step of forming a second resist covering the entire first region, and using the second resist as a mask, the second insulating film in the second region and the first region Removing the polycrystalline silicon film and the first insulating film, and forming a third insulating film on the semiconductor substrate in the second region after removing the second resist, Forming a second polycrystalline silicon film on the entire surface, and forming the second polycrystalline silicon film in a pattern of the second gate in the first region and in a pattern of the third gate in the second region. And a step of processing each into a pattern.

According to a preferred aspect of the present invention, there is provided a method of manufacturing a floating gate type non-volatile semiconductor memory device, wherein the first gate is a floating gate.
The second gate is a control gate, and the third gate is a MOS transistor gate.

In a further preferred aspect of the present invention, the first
The insulating film is a tunnel insulating film.

[0018]

In the present invention, when the second insulating film in the second region is removed by, for example, dry etching, the first polycrystalline silicon film is left under the first insulating film.
The polycrystalline silicon film of (1) acts as an etching stopper, and reliably prevents the substrate from being damaged by etching. When removing the first polycrystalline silicon film by, for example, dry etching, a relatively large etching selection ratio should be set between them even if the underlying first insulating film is thin. Because you can
It is possible to prevent the underlying first insulating film from being unexpectedly etched, and also to prevent etching damage to the substrate.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIG. 1 and FIG.

1 and 2 show an embodiment in which the present invention is applied to a method for manufacturing a flash memory. In these figures, as in the conventional example shown in FIGS. 3 and 4, the cell array region for forming memory cells is shown on the left side, and the peripheral circuit region for forming normal MOS transistors is shown on the right side.

In the present embodiment, first, as shown in FIG. 1A, an LO is formed in the element isolation region of the silicon substrate 100.
After forming the field oxide film 101 having a film thickness of about 300 to 500 nm by the COS method, 10 to 1 is formed in the element formation region.
A tunnel insulating film 102 made of a silicon oxide film having a film thickness of about 2 nm is formed. Next, a first polycrystalline silicon film 103 having a film thickness of about 150 nm is deposited on the entire surface. Then, in the cell array region, a resist 104 for processing the first polycrystalline silicon film 103 into a pattern of the floating gate is patterned, and in the peripheral circuit region, the whole is covered with the resist 104.

Next, as shown in FIG. 1B, the first polycrystalline silicon film 103 is etched using the resist 104 as a mask to form a floating gate 103 'in the cell array region. After that, the ONO film (bot
A tom oxide film of about 10 nm, a nitride film of about 5 nm, and a top oxide film of about 5 nm) 105 are formed.

Next, as shown in FIG. 1C, the entire cell array region is covered with a resist 106, and this resist 1
The ONO film 105 in the peripheral circuit region is removed by dry etching using 06 as a mask.

Next, as shown in FIG. 1D, the first polycrystalline silicon film 103 in the peripheral circuit region is formed of a gas having a high selectivity with respect to the oxide film (selectivity ratio of 10 to 30: 1), for example. CF
Etch away using ₄ .

Next, as shown in FIG. 1E, after removing the resist 106, the tunnel insulating film 102 in the peripheral circuit region is removed by wet processing. This process is ONO
The fact that the oxide film (top oxide film) on the nitride film of the film 105 is hardly wet-etched is used.

Next, as shown in FIG. 2A, a gate insulating film 107 made of a silicon oxide film with a film thickness of about 10 to 30 nm is formed in the peripheral circuit region by thermal oxidation.

Next, as shown in FIG.
A second polycrystalline silicon film 108 having a film thickness of about 50 nm is deposited.

After that, the second polycrystalline silicon film 108 is processed into the pattern of the control gate in the cell array region, and the second polycrystalline silicon film 108 is processed in the peripheral circuit region.
Is processed into the pattern of the gate electrode of the MOS transistor. Then, after impurity diffusion is performed on the silicon substrate 100 to form source / drain diffusion layers in respective regions, an interlayer insulating film is formed and necessary wirings are formed to manufacture a flash memory.

In the embodiment described above, when the ONO film 105 in the peripheral circuit region is removed by dry etching in the step shown in FIG. 1C, the first polycrystalline silicon film 103 is left as the underlying layer. , The first polycrystalline silicon film 103 acts as an etching stopper,
It is reliably prevented that the thin tunnel insulating film 102 is etched and damages the silicon substrate 100 as in the conventional case. When the first polycrystalline silicon film 103 is etched, dry etching is performed using a gas having a high selection ratio with respect to the oxide film, so that the thin tunnel insulating film 102 is also etched and the silicon substrate is also etched. It is possible to prevent 100 from being damaged.

Although the tunnel insulating film 102 is removed by the wet process in the above-described embodiments, if the dry process is also performed using the resist 106 as a mask, the ONO film 105 in the peripheral circuit region and the first film are removed. It is possible to remove the first polycrystalline silicon film 103 and the tunnel insulating film 102 as a series of steps only by changing the etching gas.

Further, in the above-described embodiment, the entire peripheral circuit region is resist 10 in the step shown in FIG.
However, if it is necessary to use the ONO film 105 also in the peripheral circuit region, only the portion in the peripheral circuit region where the ONO film 105 needs to be used is not covered with the resist 104 and is formed in that portion. The removed first polycrystalline silicon film 103 may be removed by etching in the step shown in FIG.

Furthermore, the present invention is not limited to the method of manufacturing the floating gate type nonvolatile semiconductor memory device as in the above-described embodiments, but for example, a semiconductor memory such as a two-layer polysilicon DRAM having a control gate and a storage gate. It can also be applied to a method of manufacturing a device.

[0033]

According to the present invention, for example, in a polycrystalline silicon two-layer process at the time of manufacturing a flash memory, an ONO film is not damaged in a peripheral circuit region where an ONO film as an interlayer insulating film is unnecessary. Can be reliably removed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing, in the order of steps, a polycrystalline silicon two-layer process in manufacturing a flash memory according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing, in the order of steps, a polycrystalline silicon two-layer process in manufacturing a flash memory according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing, in the order of steps, a polycrystalline silicon two-layer process in manufacturing a conventional flash memory.

FIG. 4 is a cross-sectional view showing, in the order of steps, a polycrystalline silicon two-layer process in manufacturing a conventional flash memory.

[Explanation of symbols]

 100 Silicon Substrate 102 Tunnel Insulating Film 103 First Polycrystalline Silicon Film 103 ′ Floating Gate 104 Resist 105 ONO Film 106 Resist 108 Second Polycrystalline Silicon Film

Claims (4)

[Claims] 1. A first region forming an element having a structure in which two layers of polycrystalline silicon gates are stacked with an insulating film interposed therebetween, and a second region forming an element having one layer of polycrystalline silicon gates. And a step of forming a first insulating film on the semiconductor substrate in the first region and the second region, and a method of manufacturing the first insulating film on the first insulating film. Forming a polycrystalline silicon film, and forming a first resist on the pattern of the first gate in the first region while covering the entire second region; and Selectively removing the first polycrystalline silicon film by using the mask as a mask, forming the second insulating film over the entire surface after removing the first resist, and completely removing the first region. Forming a second resist covering the A step of removing the second insulating film and the first polycrystalline silicon film in the second region by using the second resist as a mask; and a step of removing the second resist after the second resist film is removed. Removing the first insulating film in the region, forming a third insulating film on the semiconductor substrate in the second region, and forming a second polycrystalline silicon film over the entire surface A step of processing the second polycrystalline silicon film into a second gate pattern in the first region and a third gate pattern in the second region, respectively. Manufacturing method of semiconductor memory device. 2. A first region forming an element having a structure in which two layers of polycrystalline silicon gates are laminated with an insulating film interposed therebetween and a second region forming an element having one layer of polycrystalline silicon gates. And a step of forming a first insulating film on the semiconductor substrate in the first region and the second region, and a method of manufacturing the first insulating film on the first insulating film. Forming a polycrystalline silicon film, and forming a first resist on the pattern of the first gate in the first region while covering the entire second region; and Selectively removing the first polycrystalline silicon film by using the mask as a mask, forming the second insulating film over the entire surface after removing the first resist, and completely removing the first region. Forming a second resist covering the A step of removing the second insulating film, the first polycrystalline silicon film, and the first insulating film in the second region using the second resist as a mask; After the removal, a step of forming a third insulating film on the semiconductor substrate in the second region, a step of forming a second polycrystalline silicon film on the entire surface, and a step of forming the second polycrystalline silicon film And a second gate pattern in the first region, and a third gate pattern in the second region, respectively. 3. A method of manufacturing a floating gate type nonvolatile semiconductor memory device, wherein the first gate is a floating gate, the second gate is a control gate, and the third gate is a MOS transistor. 3. The method for manufacturing a semiconductor memory device according to claim 1, wherein the gate is a gate of the semiconductor memory device. 4. The method of manufacturing a semiconductor memory device according to claim 3, wherein the first insulating film is a tunnel insulating film.