JPH10154808A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect a gate oxide film from damage or destruction by a plasma process in fabrication of an LSI having an insulated gate type transistor structure. SOLUTION: A diffusion layer contact 17 leading to an impurity diffusion layer 15, electrode contacts 18, 1AL19, Via20 and 2AL21 leading to a gate electrode 14 are formed to a CVD-SiO2 film 16, for example, after having a gate electrode 14 formed thereto. Dummy wiring lines 31,... are formed simultaneously with formation of the contact 1AL19, and dummies Via33,... are formed simultaneously with formation of the contact Via20. By dispersing a plasma damage by the dummy wiring lines 31,... and dummies Via33,... in this way, the damage of a gate oxide film 13 by plasma etching at the time of forming the contacts 1AL19 and Via20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an insulated gate transistor and a method for manufacturing the same, and more particularly to a method for forming a multilayer wiring by a plasma etching process.

[0002]

2. Description of the Related Art In recent years, in the field of manufacturing semiconductor devices, for example, with the miniaturization of LSIs, the thickness of gate oxide films has been reduced. However, LS which uses a plasma etching process frequently for forming a contact hole with a gate electrode, an AL wiring, and a via hole, etc.
In the case of I, the thinning of the gate oxide film has become a factor which further increases the problem of damage or destruction of the gate oxide film by plasma.

FIG. 3 shows a schematic configuration of an LSI manufactured by using a plasma etching process. For example, this LSI has a field oxide film 102 and a gate oxide film (here, SiO 2
₂ ) 103 is formed. Then, W and C are formed on the field oxide film 102 and the gate oxide film 103.
The gate electrode 104 is formed using a conductive material such as.

[0006] Except for the position where the gate electrode 104 is formed, an impurity diffusion layer 105 serving as a source / drain is formed immediately below the gate oxide film 103. Furthermore, CVD-containing phosphorus or boron to be an interlayer film
For the SiO ₂ film 106, a diffusion layer contact 107 connected to the diffusion layer 105, an electrode contact 108 connected to the gate electrode 104, and a first layer AL
The wiring (1AL) 109, Via 110, and the second-layer AL wiring (2AL) 111 are respectively formed by a plasma etching process or the like, thereby forming an insulated gate transistor having a multilayer wiring structure.

FIG. 4 shows the result of evaluating the above-described gate oxide film of the LSI. As is apparent from this figure, when the total of the antenna ratio (circumferential length of the wire to the area of the opening area or the SiO ₂ film to the area of the SiO ₂ film) is up to about 1000 times, the yield of the SiO ₂ film is significantly deteriorated You can see that it starts to do.

As described above, in the LSI manufactured by using the conventional plasma etching process, there is a problem that as the antenna ratio increases, the yield of the gate oxide film decreases accordingly.

For this reason, as the gate oxide film becomes thinner, the plasma etching damage to the gate oxide film becomes larger, and the problem of damage or destruction of the gate oxide film by plasma becomes more serious.

[0008]

As described above, conventionally, as the thickness of a gate oxide film is reduced, the problem of damage or destruction of the gate oxide film due to plasma is further increased.

Accordingly, the present invention provides a semiconductor device capable of preventing a decrease in the yield of an insulating film even if the insulating film is thinned, and maintaining high reliability, and a method of manufacturing the same. It is an object.

[0010]

In order to achieve the above object, a semiconductor device according to the present invention has an insulated gate transistor structure in which a gate electrode is formed on a semiconductor substrate via an insulating film. In one embodiment, at least a dummy gate electrode pattern is provided for one transistor separately from the gate electrode.

Further, in the semiconductor device of the present invention,
In a transistor having an insulated gate transistor structure in which a gate electrode is formed on a semiconductor substrate via an insulating film, a dummy electrode contact is provided for at least one transistor separately from an electrode contact connected to the gate electrode. It is configured to have a pattern.

In the semiconductor device of the present invention,
In a transistor having an insulated gate transistor structure in which a gate electrode is formed over a semiconductor substrate with an insulating film interposed therebetween, a dummy wiring pattern is formed for one transistor at least separately from a wiring connected to the gate electrode. It is configured to be provided.

Further, according to the method of manufacturing a semiconductor device of the present invention, when manufacturing a semiconductor device having an insulated gate transistor structure in which a gate electrode is formed on a semiconductor substrate via an insulating film, a plasma A dummy pattern for preventing the insulating film from being damaged by plasma is formed by etching.

According to the semiconductor device and the method of manufacturing the same of the present invention, plasma etching damage to the insulating film can be reduced even if the antenna ratio is high. As a result, it is possible to protect the thinned insulating film from damage or destruction by plasma.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 schematically shows a configuration of an LSI according to an embodiment of the present invention.

For example, this LSI has a semiconductor substrate 11
A field oxide film 12 and a gate oxide film (insulating film) 13 made of a SiO ₂ film are formed thereon. And
A gate electrode 1 made of a conductive material such as W or C is formed on the field oxide film 12 and the gate oxide film 13.
4 are formed.

On the surface of the substrate 11 except for the position where the gate electrode 14 is formed, an impurity is introduced through the gate oxide film 13 to form an impurity diffusion layer 15 serving as a source / drain. I have.

Further, the diffusion layer 1 is applied to the CVD-SiO ₂ film 16 containing phosphorus or boron as an interlayer film.
5, an electrode contact 18 connected to the gate electrode 14, a first-layer AL wiring (1AL) 19, and a Via (wiring contact) 2
The 0th and second-layer AL wirings (2AL) 21 are formed by a plasma etching process or the like, respectively, to configure an insulated gate transistor having a multilayer wiring structure.

A plurality of dummy wirings (dummy wiring patterns) 31... Are formed on the CVD-SiO ₂ film 16 so that at least the area density of the 1AL 19 is constant for one transistor. I have. These dummy wirings 31 are formed, for example, simultaneously with the formation of the 1AL19.

Are connected to the substrate 11 via contacts 32, respectively. Furthermore, on each of the dummy wirings 31..., At least one Via for connecting one transistor to another wiring (here, 2AL21) is connected to one transistor.
20 so that the area density of the plurality of dummy Vis is constant.
a (dummy wiring contact patterns) 33 are formed. Each of the dummy vias 33 is formed at the same time as the formation of the vias 20, for example.

According to the LSI having such a configuration, at least when the 1AL19 and the Via 20 are formed, the damage to the gate oxide film 13 by the plasma in the plasma etching process is reduced by the dummy Vias 33 and. The plasma can be dispersed to the substrate 11 through the contact 32 while being dispersed by the dummy wirings 31.

Therefore, even if the antenna ratio of the LSI is increased, the damage due to the plasma etching of the gate oxide film 13 can be sufficiently reduced.
FIG. 2 shows the result of evaluating the above-described gate oxide film 13 of the LSI.

As is apparent from this figure, by forming the dummy vias 33 and the dummy wirings 31 until the antenna ratio becomes 10,000 times or more.
It can be seen that the yield of the gate oxide film 13 does not deteriorate.

As described above, the damage of the gate oxide film 13 due to the plasma etching can be reduced, and the thinned gate oxide film 13 can be protected from damage or destruction by the plasma.

As described above, even if the antenna ratio is high,
The plasma etching damage of the gate oxide film can be reduced. That is, a dummy pattern is formed to prevent plasma damage from occurring in the gate oxide film. As a result, plasma damage can be dispersed, so that the thinning gate oxide film can be protected from damage or destruction by plasma. Therefore, even if the gate oxide film is made thinner, the yield of the gate oxide film can be improved, and the high reliability L
It is possible to provide SI.

In the above-described embodiment of the present invention, a case has been described in which a dummy pattern is formed for 1AL and Via. However, the present invention is not limited to this. For example, a dummy pattern (a dummy gate Similarly, it is also possible to form a dummy pattern (dummy electrode contact pattern) of an electrode contact connected to a gate electrode, a dummy pattern of a 2AL (dummy wiring pattern), or a dummy pattern of a diffusion layer contact. It is possible.

The present invention is not limited to a two-layer wiring composed of 1AL and 2AL, but can be applied to, for example, a wiring having a three-layer or more wiring structure. As a material for the gate electrode, W
It is also possible to use a conductive material other than C and C.

As an interlayer film, CVD-SiO ₂
PSG or BPSG other than a film can also be used. further,
The size and shape of the dummy pattern and the number thereof are not limited at all. Of course, various modifications can be made without departing from the scope of the present invention.

[0029]

As described above in detail, according to the present invention, even if the thickness of the insulating film is reduced, it is possible to prevent the yield of the insulating film from lowering and to maintain high reliability. An apparatus and a method for manufacturing the same can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a configuration of an LSI according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a result of evaluating a gate oxide film of an LSI.

FIG. 3 is shown to explain the prior art and its problems;
FIG. 1 is a schematic configuration diagram of an LSI.

FIG. 4 is a schematic diagram showing a result of evaluating a gate oxide film of a conventional LSI.

[Explanation of symbols]

11 ... semiconductor substrate 12 ... field oxide film 13 ... gate oxide film 14 ... gate electrode 15 ... impurity diffusion layer 16 ... CVD-SiO ₂ film 17 ... diffusion layer contact 18 ... electrode contact 19 ... 1AL 20 ... Via 21 ... 2AL 31 ... Dummy wiring 32 ... Contact 33 ... Dummy Via

Claims (11)

[Claims] 1. A semiconductor device having an insulated gate transistor structure in which a gate electrode is formed on a semiconductor substrate via an insulating film, wherein at least one dummy transistor is provided separately from the gate electrode for one transistor. A semiconductor device comprising a gate electrode pattern. 2. A semiconductor device having an insulated gate transistor structure in which a gate electrode is formed on a semiconductor substrate with an insulating film interposed therebetween, wherein at least one electrode contact for one transistor is connected to the gate electrode. Separately, a semiconductor device provided with a dummy electrode contact pattern. 3. A semiconductor device having an insulated gate transistor structure in which a gate electrode is formed on a semiconductor substrate with an insulating film interposed therebetween, wherein at least one of the transistors is provided separately from a wiring connected to the gate electrode. And a dummy wiring pattern. 4. The dummy wiring pattern further includes a dummy wiring contact pattern different from a wiring contact for connecting the wiring to another wiring. 3. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein each of the dummy patterns is connected to the semiconductor substrate.
The semiconductor device according to any one of items 3 and 4. 6. A method for manufacturing a semiconductor device having an insulated gate transistor structure in which a gate electrode is formed on a semiconductor substrate via an insulating film, wherein plasma etching is prevented from being caused in the insulating film by plasma etching. A method of manufacturing a semiconductor device, wherein a dummy pattern for forming a dummy pattern is formed. 7. The device according to claim 6, wherein the dummy pattern is a gate electrode pattern formed so that at least the area density of the gate electrode is constant for one transistor. A method for manufacturing a semiconductor device. 8. The method according to claim 1, wherein the dummy pattern is an electrode contact pattern formed so that at least one electrode contact connected to the gate electrode has a constant area density with respect to one transistor. 7. The method for manufacturing a semiconductor device according to item 6. 9. The semiconductor device according to claim 6, wherein the dummy pattern is a wiring pattern formed so that at least one wiring has a constant area density with respect to one transistor. The manufacturing method of the semiconductor device described in the above. 10. The wiring formed so that the area density of wiring contacts for connecting at least one wiring connected to the gate electrode to another wiring is constant for one transistor. 7. The method according to claim 6, wherein the method is a contact pattern. 11. The semiconductor device according to claim 6, wherein the dummy pattern is connected to the semiconductor substrate.
11. The method for manufacturing a semiconductor device according to any one of 8, 9, and 10.