JPH01270248A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve reliability of wiring by decreasing the thickness of an insulating film between layers in the region where plural contact holes concentrate than that of the insulation film between layers at other region. CONSTITUTION:The first layer Al wirings 2a-2e are coated with an interlayer insulating film 4, and the second layer Al wirings 5a-5e patterned at the surface of the insulating film 4 between layers and the first layer Al wirings 2a-2e are connected through contact holes 6a-6e. The upper region of the first layer Al wirings 2a-2d which are arranged at short intervals forms a contact hole concentrated region C, where the thickness t1 of the insulation film 4 between layers is formed thinner than the thickness t2 of the insulation film 4 between layers in other regions. Accordingly, the aspect ratio of the contact holes 6a-6d formed in the contact hole concentrated region C is smaller than that of the contact hole 6e formed at other regions, and step coverage of the second layer Al wirings 5a-5d becomes excellent. Hereby, reliability of connection in wiring can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for manufacturing semiconductor devices, and in particular to a technology that is effective when applied to a technology for processing contact holes for connecting multilayer wiring.

[Conventional technology]

As semiconductor devices become more highly integrated and interconnects become finer, the aspect ratio (contact hole depth/contact hole depth/contact hole depth/contact hole depth/contact hole depth/contact hole depth/ The diameter of the contact hole increases, and the step coverage of the conductive film such as AI deposited inside the contact hole decreases.
Wiring connection reliability begins to deteriorate.

As a countermeasure to this problem, a technique has been put into practical use that improves the step coverage of the conductive film by making the cross-sectional shape of the contact hole stepped or tapered.

As a technique for forming a contact hole in a step-like cross-sectional shape, for example, there is an invention described in Japanese Patent Application Laid-Open No. 140720/1983, in which a step-like stepped portion is formed on the wall surface of the contact hole along the longitudinal direction of the lower wiring. This aims to improve the step coverage of the conductive film.

[Problem to be solved by the invention]

However, according to the inventor's study, the above-mentioned prior art has the drawback that as semiconductor devices become highly integrated and the pitch between contact holes becomes narrower, sufficient connection reliability cannot be obtained. ing.

In other words, as the pitch between contact holes becomes narrower, the thickness of the insulating film separating the contact holes becomes thinner, and especially in contact holes with a stepped or tapered cross-sectional shape, the thickness of the insulating film at the upper edge of the contact hole becomes thinner. Since the thickness is extremely thin, even the slightest stress can cause the insulating film to chip or deform.

If such a chip or deformation occurs in a part of the insulating film that separates the contact holes, a short circuit may occur between the contact holes, or the chipped fragments may become foreign particles that get mixed into the conductive film and cause electrical continuity. This will cause defects, and the connection reliability of the wiring will be significantly reduced.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that can improve the reliability of wiring connected through contact holes.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, one of the areas where multiple contact holes are concentrated
This is a semiconductor device structure in which the interlayer insulating film is thinner than the interlayer insulating film in other regions.

[Effect]

According to the above-described means, it is possible to prevent chipping or deformation of the insulating film that separates contact holes having a narrow pitch.

Furthermore, since the aspect ratio of the contact hole is reduced, the step coverage of the conductive film deposited within the contact hole is improved.

〔Example〕

FIG. 1 is a sectional view of a main part of a semiconductor substrate showing a semiconductor device which is an embodiment of the present invention, and FIGS. 2(a) to (C) are main parts of a semiconductor substrate showing a method for manufacturing this semiconductor device. FIG.

This embodiment is a semiconductor device in which predetermined integrated circuit elements (not shown) are formed on the main surface of a semiconductor substrate (hereinafter referred to as substrate) 1 made of silicon single crystal, and the integrated circuit elements are electrically interconnected. Connecting -th layer Al wirings 2a to 2e are patterned on the surface of the oxide film 3.

The -th layer Al wirings 2a to 2e are covered with an interlayer insulating film 4, and the second layer Al wirings 5a to 5e patterned on the surface of the interlayer insulating film 4 and the -th layer Aj2 wiring 2a.
2e are connected to each other via contact holes 6a to 6e.

-th layer A arranged at very close intervals to each other
The region above the l interconnects 2a to 2d forms a contact hole dense region C, and the thickness (tl) of the interlayer insulating film 4 is processed to be thinner than the thickness (t2) of the interlayer insulating film 4 in other regions. There is.

Therefore, the aspect ratio of the contact holes 6a to 6d formed in the contact hole dense region C is smaller than the aspect ratio of the contact hole 6e formed in other regions, and the step coverage of the second layer A1 wirings 5a to 5d is Becomes good.

On the other hand, the isolated contact hole 6e in the other region is formed so that its cross section is step-like, and thereby A
This is intended to improve the step coverage of the l wiring 5e.

Next, an example of the method for manufacturing the above semiconductor device is shown in FIG. 2(a).
This will be explained according to (C).

First, a thin oxide film 3 is formed on the surface of the substrate 1 by heat treatment, and a predetermined integrated circuit element is formed in the active element region according to a conventional method. After that, an Af film is deposited on the surface of the substrate 1. Etching is performed to form the -th layer Aβ wirings 2a to 2e (FIG. 2(a)).

Next, the surface of the substrate 1 is made of phosphosilicate glass (PSG) or S.
After depositing the interlayer insulating film 4 made of i3N4 or the like, a photoresist 7a is deposited on the surface of the interlayer insulating film 4, and using this as a mask, the interlayer insulating film 4 is anisotropically etched.
Vertical contact holes 6a to 6e are formed above a to 2e (FIG. 2Q)).

Next, after removing the photoresist (7a), a new photoresist (7b) is deposited on the surface of the substrate (1), and a mask with openings above the contact hole dense area (C) and the isolated contact hole (6e) is created. The interlayer insulating film 4 is anisotropically etched using a mask to thin the interlayer insulating film 4 in the contact hole dense region C, and to obtain a contact hole 6e having a stepped cross-sectional shape (second etching).
Figure (C)).

Finally, after removing the photoresist 7b, the Al film deposited on the surface of the substrate 1 is etched to form a second layer, l wirings 5a to 5e, to obtain the semiconductor device structure shown in FIG.

As described above, according to this embodiment, the following effects can be obtained.

(1) Since the thickness of the interlayer insulating film 4 in the contact hole dense region C is made thinner than the film thickness of the interlayer insulating film 4 in other regions, the contact holes 6a to 6d formed in the contact hole dense region C are The aspect ratio is reduced, and the step coverage of the second layer Al wirings 5a to 5d is improved.

(2), according to (1) above, the second layer A1 wiring 5a to 5d
Improves electromigration resistance.

(3) Due to (1) above, wiring can be made into a machine box, and as a result,
High density and high integration of semiconductor devices will be promoted.

(4) Since chipping and deformation of the interlayer insulating film 4 that separates the contact holes 6a to 6d from each other can be prevented,
-th layer Aj2 wiring 2a to 2d and second layer AJ wiring 5a to
The reliability of the connection with 5d is improved.

(5) Since the film thickness (t2) of the 9-layer insulating film 4 can be increased, the wiring capacitance l of the first layer and second layer A1 wiring is reduced, thereby reducing the propagation delay of electrical inertia. do.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and various changes can be made without departing from the gist thereof. It goes without saying that it is possible.

For example, in the embodiment, a case has been described in which the application is applied to a contact hole for connecting a first layer wiring and a second layer wiring, but it is also applicable to a contact hole for connecting a second layer wiring and a substrate. You can also do it.

Further, the cross-sectional shape of the contact holes formed in the region other than the contact hole dense region may be, for example, tapered.

Furthermore, in the example, a two-layer mask process was required to thin the interlayer insulating film in the contact hole dense area, but by using a resist regression method, the interlayer insulating film can be thinned in - times of masking. It is also possible to process it.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, by making the thickness of the interlayer insulating film in a region where a plurality of contact holes are densely packed thinner than the thickness of the interlayer insulating film in other regions, the step coverage of wiring is improved and the contact holes can be cornered with each other. Since chipping and deformation of the insulating film can be prevented, connection reliability of wiring can be improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a semiconductor substrate showing a semiconductor device which is an embodiment of the present invention, and FIGS. 2(a) to (C) are main cross sections of a semiconductor substrate showing a method of manufacturing this semiconductor device. It is a diagram. 1...Semiconductor substrate, 2a-2e...-th fan Aj! r
: l line, 3... oxide film, 4... interlayer insulating film, 5a~
5e...Second line, 6a-6e...Contact hole, 7a, 7b...Photoresist, C...
Contact hole dense area.

Claims (1)

[Scope of Claims] 1. A semiconductor device that connects upper and lower layer wiring or the semiconductor substrate and wiring through a plurality of contact holes formed in an interlayer insulating film on a semiconductor substrate, the semiconductor device comprising a plurality of contacts. A semiconductor device characterized in that the thickness of the interlayer insulating film in a region where holes are concentrated is made thinner than the thickness of the interlayer insulating film in other regions. 2. The semiconductor device according to claim 1, wherein the contact hole formed in the interlayer insulating film in the other region has a stepped cross-sectional shape.