JPH03136351A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To avoid the cracking in interlayer film as well as the short-circuit between adjacent wirings of the film due to thermal stress by a method wherein at least one out of a lower and upper layer wirings at an intersection part provided at least on the peripheral part of a semiconductor chip is made rugged. CONSTITUTION:An upper layer Al wiring 5 is formed by anisotropically dry- etching away an Al layer using the first and second masks. At this time, the first mask in the opening of the second mask is simultaneously etched away so as to each away the parts of exposed Al layer thereby making grooves 6. Next, the first and second masks are removed to form a protective film 7 on the whole surface including the Al wiring 5 having the grooves 6. Then, the formed semiconductor chip is mounted on a leadframe; the leadframe and the semiconductor chip are connected by a metallic fine wire and resin-sealed to form a semiconductor integrated circuit while the sectional space of the Al wiring 5 at an intersection part is limited and made rugged so that the stress imposed on an interlayer insulating film 4 may be abated to avoid the cracking in the film 4 as well as the short-circuit between adjacent wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a resin-sealed semiconductor integrated circuit.

[Conventional technology]

Conventional resin-sealed semiconductor integrated circuits are shown in Fig. 3(a).
As shown in (b), a silicon substrate 1 provided with an element region
a silicon oxide film 2 provided above, an interlayer insulating film 4 provided on the surface including the lower layer AJ2 wiring 3 and A1 wiring 3 selectively provided on the silicon oxide film 2; The upper layer A1 wiring 5 provided in the upper layer and intersecting the Aρ wiring 3, and the AJ
A semiconductor chip was formed by having a protective film 7 provided on the surface including the wiring 5, and the semiconductor chip was sealed with a resin.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, when attempting to increase the size of the semiconductor chip through higher integration, the AJ wiring may be moved due to thermal stress caused by the difference in thermal expansion coefficient between the semiconductor chip and the resin body that encapsulates it. This has the drawback of causing cracks in the interlayer insulating film where upper and lower wires intersect, and short-circuiting between adjacent wires in the same layer.

On the other hand, if the material of the sealing resin is changed to select one that generates less stress, the filling property into the mold will be poor and the moisture resistance will be weakened, so this cannot be used.

[Means to solve the problem]

The resin-sealed semiconductor integrated circuit of the present invention includes a lower layer wiring provided on an insulating film provided on a semiconductor substrate, an interlayer insulating film provided on a surface including the lower layer wiring, and an interlayer insulating film provided on the interlayer insulating film. A semiconductor integrated circuit having an upper layer wiring that is provided and intersects with the lower layer wiring includes an uneven portion provided on a surface of at least one of the lower layer wiring and the upper layer wiring at the intersecting portion.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along the line AA' of a first embodiment of the present invention.

As shown in FIGS. 1(a) and 1(b), a silicon oxide film 2 is formed on a silicon substrate 1 on which an element region is formed.
Next, a lower layer Al wiring 3 is selectively formed on the silicon oxide film 2, and an interlayer insulating film 4 is deposited on the surface including the Al wiring 3. Next, an A1 layer is deposited on the interlayer insulating film 4 by sputtering, and a low viscosity photoresist film is applied on the A1 layer to a thickness of 0°2 to 0.5 μm and patterned.
A first mask for forming upper layer wiring is formed.

Next, a high viscosity photoresist film is applied to the surface including the first mask to a thickness of 2 to 3 μm to form a pattern that matches the first mask and a peripheral edge within at least 2 mm from the outer periphery of the semiconductor chip area. The second layer has a pattern in which strip-shaped openings are arranged in parallel at the intersection with the lower layer wiring formed in the section.
A mask is stacked and provided on the first mask. Next, the A1 layer is removed by anisotropic dry etching using the first and second masks to form the upper layer A1 wiring 5. At this time, the first mask within the opening of the second mask is also etched at the same time, and a portion of the exposed surface of the Aff1 layer is etched to form a groove 6. Next, the first and second masks are removed, and a protective film 7 is formed on the surface including the Affl wiring 5 having the groove 6.

The semiconductor chip formed in this way is mounted on a lead frame, the lead frame and the semiconductor chip are connected with thin metal wires, and the semiconductor integrated circuit is sealed with resin. The small cross-sectional area and unevenness have the effect of reducing the stress applied to the interlayer insulation film 4 and preventing cracks in the interlayer insulation M4 and short circuits between adjacent wirings.

FIG. 2 is a plan view of a second embodiment of the invention.

As shown in FIG. 2, the structure is the same as that of the first embodiment except that grooves 8 are provided in the A and R wires 3 below the intersection.

Note that a checkered recess may be provided instead of the groove 6.8.

〔Effect of the invention〕

As explained above, the present invention provides unevenness on at least one of the lower layer wiring and the upper layer wiring at the intersection provided at least at the peripheral edge of a semiconductor chip, thereby preventing cracks in the interlayer film due to thermal stress. This has the effect of preventing short circuits between adjacent wiring lines and improving reliability in making resin-sealed semiconductor integrated circuits into larger chips.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a plan view and a sectional view taken along line A-A' of a first embodiment of the present invention, FIG. 2 is a plan view of a second embodiment of the present invention, and FIG. (a) and (b) are a plan view and a sectional view taken along the line BB' showing an example of a conventional semiconductor integrated circuit. l...Silicon substrate, 2...Silicon oxide film, 3.
... A1 wiring, 4... Interlayer insulating film, 5... Al wiring, 6... Groove, 7... Protective film, 8... Groove.

Claims (1)

[Claims] A lower layer wiring provided on an insulating film provided on a semiconductor substrate, an interlayer insulating film provided on a surface including the lower layer wiring, and an upper layer wiring provided on the interlayer insulating film and crossing the lower layer wiring. 1. A semiconductor integrated circuit comprising: an uneven portion provided on the surface of at least one of the lower-layer wiring and the upper-layer wiring at the intersecting portion.