JPH02297953A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02297953A
JPH02297953A JP11931389A JP11931389A JPH02297953A JP H02297953 A JPH02297953 A JP H02297953A JP 11931389 A JP11931389 A JP 11931389A JP 11931389 A JP11931389 A JP 11931389A JP H02297953 A JPH02297953 A JP H02297953A
Authority
JP
Japan
Prior art keywords
wiring
film
conductor film
conductive film
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11931389A
Other languages
Japanese (ja)
Inventor
Akihiro Hosoya
明宏 細谷
Mitsuhiro Furuichi
古市 充寛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP11931389A priority Critical patent/JPH02297953A/en
Publication of JPH02297953A publication Critical patent/JPH02297953A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the stress due to sealing with mold resin and prevent the stress from acting directly on a wiring layer so as to prevent cracks on the layer by forming a dummy conductive film at the outside or the inside of wiring conductive films which are formed on a semiconductor substrate through insulating films. CONSTITUTION:The wiring conductive film 12 of a semiconductor peripheral part, the wiring conductive film 14 of the inside of a semiconductor, a bonding pad part 13 that is formed by the wiring conductive film, and a conductive film 15 for dummy are formed on a semiconductor element region 11 at each corner part of a semiconductor substrate 20. Simultaneously with the formation of patterns of these conductive films 12 and 14, the pattern of the conductive film 15 for dummy is formed and the increase in the number of a process is prevented. A wiring film 22 at the peripheral part of a semiconductor device, a dummy conductive film 25, an interlayer insulation film 26, and a protection insulating film 27 are formed at respective parts of the semiconductor substrate 20 in a cross-section taken along a line A-A' of a substrate 10. In this way, stress generated by mold resin is relieved by making the width of the conductive film 25 that is provided at the outside of the wiring film 22 narrow and thus the stress is not applied very much to the conductive film 22.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型の半導体装置における配線用導体膜
の応力緩和構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a stress relaxation structure for a wiring conductor film in a resin-sealed semiconductor device.

〔従来の技術〕[Conventional technology]

従来この種の半導体装置は第5図および第6図に示すと
おり半導体基板50の一主面に半導体素子領域51が形
成され層間絶縁膜66を介してアルミなどの配線用導体
膜52および62をポンディングパッドとなる部分を含
めて形成しリンシリケートガラスシリコンナイトライド
膜等の保護用絶縁膜67で覆った後ボンディングバット
部53のみをエツチングして露光させる構造となってい
る。
Conventionally, in this type of semiconductor device, as shown in FIGS. 5 and 6, a semiconductor element region 51 is formed on one main surface of a semiconductor substrate 50, and conductor films 52 and 62 for wiring, such as aluminum, are formed through an interlayer insulating film 66. The structure is such that only the bonding pad portion 53 is etched and exposed after it is formed including the portion that will become the bonding pad and covered with a protective insulating film 67 such as a phosphosilicate glass silicon nitride film.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

このような従来の半導体装置はモールド樹脂にて封止を
行った場合モールド樹脂、リンシリケートガラスシリコ
ンナイトライド等の保護膜、アルミ等の導体膜などそれ
ぞれの膨張率の差から応力が発生し、特に半導体装置の
コーナ一部においては幅広の導体膜を囲む保護膜や導体
膜の下層となる絶縁膜にクラックが発生し配線の信頼性
を低下させるような欠点があった。
When such conventional semiconductor devices are sealed with mold resin, stress is generated due to the difference in expansion coefficient of the mold resin, a protective film such as phosphosilicate glass silicon nitride, and a conductive film such as aluminum. In particular, cracks occur in the protective film surrounding the wide conductor film and the insulating film underlying the conductor film at some corners of the semiconductor device, resulting in a reduction in the reliability of the wiring.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、半導体基板上に絶縁膜を介して
形成される配線用導体膜と配線用導体膜に付加されるダ
ミー用の導体膜を有している。
The semiconductor device of the present invention includes a wiring conductor film formed on a semiconductor substrate with an insulating film interposed therebetween, and a dummy conductor film added to the wiring conductor film.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示す平面図である。FIG. 1 is a plan view showing one embodiment of the present invention.

図において10は半導体基板、11は半導体素子領域、
12は半導体周辺部の配線用導体膜、13は配線用導体
膜で形成されるポンディングパッド部、14は半導体内
部の配線用導体膜、15はダミー用の導体膜である。本
発明の実施にあたっては特に新しい技術は必要とせず周
知の従来技術をもって実現しうるものであり配線用導体
膜パターン12,14の形成時に同時にダミー用のノ(
ターン15が形成できる為工程数も増加しない。
In the figure, 10 is a semiconductor substrate, 11 is a semiconductor element region,
Reference numeral 12 designates a wiring conductor film in the peripheral area of the semiconductor, 13 a bonding pad portion formed of the wiring conductor film, 14 a wiring conductor film inside the semiconductor, and 15 a dummy conductor film. The present invention does not require any new technology and can be realized using well-known conventional techniques, and it is possible to simultaneously form dummy holes (
Since turn 15 can be formed, the number of steps does not increase.

第2図は第1図のA−A’線断面図を拡大したものであ
る。図において20は半導体基板、22は半導体装置周
辺部の配線用導体膜、25はダミー用の導体膜、26は
層間絶縁膜、27は保護用絶縁膜である。モールド樹脂
で封止された半導体装置は半導体装置のコーナーから半
導体装置の中心へ向って応力が発生する。このとき第5
図のごとく半導体装置のコーナ一部に配線用導体膜がお
かれた場合第6図より明らかなように配線用導体膜に直
接応力が加わり保護用絶縁膜や層間絶縁膜にクラックが
発生する。一方策2図のごとく半導体装置のコーナ一部
に配置される半導体周辺部の配線用導体膜22の外側に
ダミー用の導体膜25を設置することによりモールド樹
脂による応力はダミー用導体膜25に加わるようになり
ダミー用導体膜25の幅が狭い為ダミー用導体膜25が
クッションの役目をして応力を緩和するだけでなく応力
の多くはダミー用導体膜25に加わり配線用導体膜22
にはほとんど加わらない。実際に形成されるダミー用導
体膜25自身の幅と保護される配線用導体膜22との間
隔については、導体膜がアルミの場合は幅2間隔とも5
〜20μm程度が適当であり効果も大きい。
FIG. 2 is an enlarged view of the sectional view taken along the line AA' in FIG. In the figure, 20 is a semiconductor substrate, 22 is a conductive film for wiring around the semiconductor device, 25 is a dummy conductive film, 26 is an interlayer insulating film, and 27 is a protective insulating film. In a semiconductor device sealed with mold resin, stress is generated from the corners of the semiconductor device toward the center of the semiconductor device. At this time, the fifth
As shown in the figure, when a wiring conductor film is placed in a part of a corner of a semiconductor device, stress is applied directly to the wiring conductor film, causing cracks to occur in the protective insulating film and the interlayer insulating film, as is clear from FIG. On the other hand, as shown in Figure 2, by installing a dummy conductor film 25 on the outside of the wiring conductor film 22 in the semiconductor periphery, which is placed in a part of the corner of the semiconductor device, the stress caused by the molding resin is removed from the dummy conductor film 25. Since the width of the dummy conductor film 25 is narrow, the dummy conductor film 25 not only acts as a cushion and relieves the stress, but also most of the stress is applied to the dummy conductor film 25 and the wiring conductor film 22
hardly adds to it. Regarding the width of the dummy conductor film 25 itself to be actually formed and the interval between the wiring conductor film 22 to be protected, if the conductor film is made of aluminum, the width 2 interval is 5.
A thickness of about 20 μm is appropriate and has a great effect.

第3図は本発明の第2の実施例でありダミー用の導体膜
を複数設けた例である。保護される配線用導体膜の内側
にも外側と同様なダミー用の導体膜を設けることにより
応力を一層緩和することができる。
FIG. 3 shows a second embodiment of the present invention, and is an example in which a plurality of dummy conductor films are provided. Stress can be further alleviated by providing a dummy conductor film similar to the outside of the wiring conductor film to be protected.

第4図は本発明の第3の実施例を示すものでありダミー
用の導体膜が細かく長方形に分かれており応力の緩和に
はより効果的である。
FIG. 4 shows a third embodiment of the present invention, in which the dummy conductor film is divided into fine rectangular sections, which is more effective in alleviating stress.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は半導体基板上に絶縁膜を介
して形成される配線用導体膜に対しダミーとなる導体膜
を配線用導体膜の外側あるいは内側に形成することによ
りモールド樹脂の封入によって発生する応力を緩和でき
るだけでなく発生した応力が直接配線用導体膜に加わら
なくすることができる為配線用導体膜をとりまく保護用
絶縁膜や層面絶縁膜にクラックがはいることを防止し配
線の信頼性を著しく向上させる効果がある。
As explained above, the present invention forms a dummy conductor film on the outside or inside of the wiring conductor film formed on the semiconductor substrate with an insulating film interposed therebetween. Not only can the generated stress be alleviated, but it can also be prevented from being applied directly to the wiring conductor film, which prevents cracks from forming in the protective insulating film and layered insulating film surrounding the wiring conductor film. This has the effect of significantly improving reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す平面図、第2図は第1
図のA−A’線の断面図、第3図は本発明の第2の実施
例を表す平面図、第4図は本発明の第3の実施例を表す
平面図、第5図は従来の実施例を表す平面図、第6図は
第5図のB−B’線の断面図である。 10.20,30,40,50.60・・・・・・半導
体基板、11,31,41.51・・・・・・半導体素
子領域、12,22,32,42,52.62・・・・
・・半導体装置周辺部の配線用導体膜、13,33゜4
3.53・・・・・・ポンディングパッド部、14゜3
4.44.54・・・・・・半導体装置内部の配線用導
体膜、15,25,35.45・・・・・・ダミー用導
体膜、26.66・・・・・・層間絶縁膜、27.67
・・・・・・保護用絶縁膜。 代理人 弁理士  内 原   音 \13flぐンテシ・クツ勺゛さμ 第1図 第2図 第4図
Fig. 1 is a plan view showing one embodiment of the present invention, and Fig. 2 is a plan view showing an embodiment of the present invention.
3 is a plan view showing the second embodiment of the present invention, FIG. 4 is a plan view showing the third embodiment of the present invention, and FIG. 5 is a plan view showing the conventional example. FIG. 6 is a sectional view taken along line BB' in FIG. 5. 10.20, 30, 40, 50.60... Semiconductor substrate, 11, 31, 41.51... Semiconductor element region, 12, 22, 32, 42, 52.62...・・・
・・Conductor film for wiring around semiconductor device, 13,33゜4
3.53...Ponding pad part, 14゜3
4.44.54... Conductor film for wiring inside semiconductor device, 15, 25, 35.45... Conductor film for dummy, 26.66... Interlayer insulating film , 27.67
・・・・・・Protective insulating film. Agent Patent Attorney Oto Uchihara \13flGuntesi Kutsusasaμ Fig. 1 Fig. 2 Fig. 4

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板上の一主面に形成された半導体装置の
素子領域上に絶縁膜を介して配線層となる導体膜を形成
する樹脂封止型の半導体装置において該半導体基板上の
4隅を含むコーナー周辺部に配置される上記配線用導体
膜の外側、あるいは内側に該導体膜に臨接してダミー用
の導体膜を配置することを特徴とする半導体装置。
(1) In a resin-sealed semiconductor device in which a conductor film serving as a wiring layer is formed on an element region of the semiconductor device formed on one principal surface of the semiconductor substrate via an insulating film, the four corners on the semiconductor substrate A semiconductor device characterized in that a dummy conductor film is disposed adjacent to the conductor film outside or inside the conductor film for wiring disposed around the corner including the conductor film.
(2)上記ダミー用の導体膜はダミー用導体膜が付され
る配線用導体膜に比べて幅が十分に狭く形成されており
かつダミー用導体膜が付される配線用導体膜は半導体基
板上の絶縁膜上に形成された他の配線用導体膜に比べて
幅広であることを特徴とする特許請求の範囲第1項記載
の半導体装置。
(2) The width of the dummy conductor film is formed to be sufficiently narrower than the wiring conductor film to which the dummy conductor film is attached, and the wiring conductor film to which the dummy conductor film is attached is a semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the semiconductor device is wider than other wiring conductor films formed on the upper insulating film.
(3)上記ダミー用の導体膜が複数本あるいは複数個設
けられたことを特徴とする特許請求の範囲第1項記載の
半導体装置。
(3) The semiconductor device according to claim 1, wherein a plurality or plurality of the dummy conductor films are provided.
JP11931389A 1989-05-11 1989-05-11 Semiconductor device Pending JPH02297953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11931389A JPH02297953A (en) 1989-05-11 1989-05-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11931389A JPH02297953A (en) 1989-05-11 1989-05-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02297953A true JPH02297953A (en) 1990-12-10

Family

ID=14758352

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11931389A Pending JPH02297953A (en) 1989-05-11 1989-05-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02297953A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448112A (en) * 1991-02-07 1995-09-05 Nec Corporation Plastic sealed multiple level metalization semiconductor device
JPH1012615A (en) * 1996-06-27 1998-01-16 Nec Ic Microcomput Syst Ltd Semiconductor device
US5763936A (en) * 1995-04-27 1998-06-09 Yamaha Corporation Semiconductor chip capable of supressing cracks in insulating layer
JP2006332344A (en) * 2005-05-26 2006-12-07 Matsushita Electric Ind Co Ltd Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448112A (en) * 1991-02-07 1995-09-05 Nec Corporation Plastic sealed multiple level metalization semiconductor device
US5763936A (en) * 1995-04-27 1998-06-09 Yamaha Corporation Semiconductor chip capable of supressing cracks in insulating layer
JPH1012615A (en) * 1996-06-27 1998-01-16 Nec Ic Microcomput Syst Ltd Semiconductor device
JP2006332344A (en) * 2005-05-26 2006-12-07 Matsushita Electric Ind Co Ltd Semiconductor device
JP4675159B2 (en) * 2005-05-26 2011-04-20 パナソニック株式会社 Semiconductor device

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