JP3098333B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP3098333B2
JP3098333B2 JP04245904A JP24590492A JP3098333B2 JP 3098333 B2 JP3098333 B2 JP 3098333B2 JP 04245904 A JP04245904 A JP 04245904A JP 24590492 A JP24590492 A JP 24590492A JP 3098333 B2 JP3098333 B2 JP 3098333B2
Authority
JP
Japan
Prior art keywords
conductor film
wiring conductor
semiconductor device
film
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP04245904A
Other languages
Japanese (ja)
Other versions
JPH0669212A (en
Inventor
智弘 上村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP04245904A priority Critical patent/JP3098333B2/en
Publication of JPH0669212A publication Critical patent/JPH0669212A/en
Application granted granted Critical
Publication of JP3098333B2 publication Critical patent/JP3098333B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体チップを樹脂で封
止した半導体装置に関し、特に半導体チップのコーナ領
域の隣接部に配置される配線用導体膜の耐応力性を向上
した半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor chip is sealed with a resin, and more particularly to a semiconductor device in which a wiring conductor film disposed adjacent to a corner region of a semiconductor chip has improved stress resistance.

【0002】[0002]

【従来の技術】従来、半導体装置は、図3(a)及び
(b)に示すように、半導体基板10の一主面に半導体
素子領域11が形成され、第1の層間絶縁膜20を介し
てアルミニウム等の内部配線用導体膜12及び半導体装
置周辺部の第1の配線用導体膜13を形成し、次に第2
の層間絶縁膜21を介してアルミニウム等の半導体装置
周辺部の第2の配線用導体膜14をボンディングパッド
部18を含めて形成し、リンシリケートガラス、シリコ
ン窒化膜等の保護用絶縁膜23で覆った後、ボンディン
グパッド部18のみエッチングして露出させる構造とな
っていた。
2. Description of the Related Art Conventionally, in a semiconductor device, as shown in FIGS. 3A and 3B, a semiconductor element region 11 is formed on one main surface of a semiconductor substrate 10 and a first interlayer insulating film 20 is interposed therebetween. To form an internal wiring conductor film 12 of aluminum or the like and a first wiring conductor film 13 around the semiconductor device.
The second wiring conductor film 14 around the semiconductor device such as aluminum is formed including the bonding pad portion 18 with the interlayer insulating film 21 interposed therebetween, and is formed with a protective insulating film 23 such as a phosphor silicate glass or a silicon nitride film. After covering, only the bonding pad portion 18 is etched and exposed.

【0003】[0003]

【発明が解決しようとする課題】このような従来の半導
体装置は、+ 150℃〜−65℃の温度サイクル試験を行っ
た場合に、半導体チップを封止する樹脂の伸び縮みによ
り応力が発生し、図3(a)の矢印のように半導体装置
周辺部の第2の配線用導体膜14に大きな応力が加わ
る。このとき、近年における大チップの樹脂封止化に伴
い、チップサイズが15mm□を越えるような大チップを
樹脂封止して温度サイクル試験を行った場合、図3
(b)のように、応力が半導体装置周辺部の第2の配線
用導体膜14に直接加わるため、この第2の配線用導体
膜14を覆う保護用絶縁膜23にクラックが発生する。
In such a conventional semiconductor device, when a temperature cycle test at + 150.degree. C. to -65.degree. C. is performed, stress is generated due to expansion and contraction of a resin for sealing the semiconductor chip. As shown by arrows in FIG. 3A, a large stress is applied to the second wiring conductor film 14 around the semiconductor device. At this time, when a large chip having a chip size exceeding 15 mm □ was sealed with a resin and a temperature cycle test was performed with the recent resin sealing of a large chip, FIG.
As shown in (b), since the stress is directly applied to the second wiring conductor film 14 in the peripheral portion of the semiconductor device, a crack is generated in the protection insulating film 23 covering the second wiring conductor film 14.

【0004】更には、図4のモデル図に示すように、応
力により配線用導体膜にスライドが発生する。このスラ
イドは、半導体装置のコーナ領域24よりコーナ隣接領
域25においてスライドの移動幅が大きいという傾向を
有し、コーナ隣接領域25において半導体装置周辺部の
第2の配線用導体膜14のずれが発生し、配線の信頼性
を低下させるという問題がある。例えば、14.8mm□のチ
ップを樹脂封止して実験を行った結果、3〜4mm長のコ
ーナ隣接領域25でクラックやずれ26の発生が認めら
れた。本発明の目的は、応力によるクラックの発生と配
線用導体膜のスライドを防止して配線の信頼性を改善し
た半導体装置を提供することにある。
Further, as shown in the model diagram of FIG. 4, a slide occurs in the wiring conductor film due to stress. This slide has a tendency that the sliding width is larger in the corner adjacent region 25 than in the corner region 24 of the semiconductor device, and the second wiring conductor film 14 in the peripheral portion of the semiconductor device is shifted in the corner adjacent region 25. However, there is a problem that the reliability of the wiring is reduced. For example, as a result of conducting an experiment with a 14.8 mm square chip sealed with a resin, cracks and shifts 26 were found in the corner adjacent region 25 having a length of 3 to 4 mm. It is an object of the present invention to provide a semiconductor device in which cracks due to stress and sliding of a wiring conductor film are prevented to improve wiring reliability.

【0005】[0005]

【課題を解決するための手段】本発明は半導体基板に絶
縁膜を介して周辺部に沿うように配線用導体膜を形成し
た半導体装置において、前記配線用導体膜を覆う絶縁膜
が形成され、半導体装置の周辺部のコーナー隣接領域の
前記配線用導体膜に沿ってかつ前記絶縁膜の上側から前
記配線用導体膜を覆うダミー用導体膜が形成されている
ことを特徴とする半導体装置である。
According to the present invention, there is provided a semiconductor device having a wiring conductor film formed along a peripheral portion on a semiconductor substrate with an insulation film interposed therebetween, wherein an insulation film covering the wiring conductor film is formed. A semiconductor device, wherein a dummy conductor film is formed along the wiring conductor film in an area adjacent to a corner in a peripheral portion of the semiconductor device and covering the wiring conductor film from above the insulating film. .

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図1(a)及び(b)は本発明の第1実施例を示す
半導体装置の平面図とそのA−A線断面図である。半導
体基板10の一主面に例えば1.0μmのフィールド酸化
膜19を形成して半導体素子領域11を区画し、この上
に膜厚1.0μmのリンシリケートガラス膜等の第1の層
間絶縁膜20を介して膜厚0.5μmのアルミニウム等の
内部配線用導体膜12、及び半導体装置周辺部の第1の
配線用導体膜13を含めて形成する。
Next, the present invention will be described with reference to the drawings. FIGS. 1A and 1B are a plan view of a semiconductor device according to a first embodiment of the present invention and a sectional view taken along line AA of the semiconductor device. A field oxide film 19 of, for example, 1.0 μm is formed on one main surface of the semiconductor substrate 10 to divide the semiconductor element region 11, and a first interlayer insulating film such as a 1.0 μm-thick phosphor silicate glass film is formed thereon. The conductor film 12 is formed to include the internal wiring conductor film 12 of 0.5 μm or the like and the first wiring conductor film 13 in the periphery of the semiconductor device through the interlayer insulating film 20.

【0007】また、膜厚1.0μmのプラズマ酸化膜等の
第2の層間絶縁膜21を介して膜厚1.0μmのアルミニ
ウム等の半導体装置周辺部の第2の配線用導体膜14を
ボンディングパッド部18を含めて形成する。更に、こ
の上に膜厚1.0μmのプラズマ酸化膜等の第3の層間絶
縁膜22を介して膜厚1.3μmのアルミニウム等のダミ
ー導体膜15を形成する。このダミー用導体膜15は、
半導体装置のコーナ部に隣接する領域25における2本
の配線用導体膜14を覆うように形成する。その上に、
膜厚1.0μmのリンシリケートガラス,シリコン窒化膜
等の保護用絶縁膜23で覆った後、この絶縁膜23をボ
ンディングパッド部のみをエッチングしてボンディング
パッド部を露出させることにより所望の構造を得る。
A second wiring conductor film 14 around a semiconductor device, such as aluminum, having a thickness of 1.0 μm is bonded via a second interlayer insulating film 21 such as a plasma oxide film having a thickness of 1.0 μm. It is formed including the pad portion 18. Further, a 1.3 μm-thick dummy conductor film 15 made of aluminum or the like is formed thereon via a third interlayer insulating film 22 such as a 1.0 μm-thick plasma oxide film. This dummy conductor film 15
It is formed so as to cover the two wiring conductor films 14 in a region 25 adjacent to the corner of the semiconductor device. in addition,
After the insulating film 23 is covered with a protective insulating film 23 such as a phosphor silicate glass or a silicon nitride film having a thickness of 1.0 μm, only the bonding pad portion is etched to expose the bonding pad portion to form a desired structure. obtain.

【0008】この構成によれば、樹脂で封止された半導
体装置には、その中心方向に向かって応力が発生する。
このとき、半導体装置の周辺部のコーナに隣接する領域
25に配置される第2の配線用導体膜14の上に第3の
層間絶縁膜22を介して2本の第2の配線用導体膜14
を覆うようにダミー用導体膜15が設けられているた
め、応力は直接このダミー用導体膜15に加わり、ここ
で吸収され、或いは緩和される。これにより、第2の配
線用導体膜14を覆う層間絶縁膜22のクラックの発生
やコーナ隣接領域25での第2の配線用導体膜14のず
れの発生も防止できる。なお、ダミー用導体膜15はア
ルミニウムの場合、幅は第2の配線用導体膜14より2
0μm大きいのが適当であり、耐応力性の効果も大き
い。
According to this structure, a stress is generated in the semiconductor device sealed with the resin toward the center direction.
At this time, the two second wiring conductor films are disposed on the second wiring conductor film 14 arranged in the region 25 adjacent to the corner in the peripheral portion of the semiconductor device via the third interlayer insulating film 22. 14
Is provided so as to cover the dummy conductor film 15, the stress is directly applied to the dummy conductor film 15 and is absorbed or reduced here. This can prevent the occurrence of cracks in the interlayer insulating film 22 covering the second wiring conductor film 14 and the occurrence of displacement of the second wiring conductor film 14 in the corner adjacent region 25. In the case where the dummy conductor film 15 is made of aluminum, the width of the dummy conductor film 15 is two times larger than that of the second wiring conductor film 14.
It is suitably larger by 0 μm, and the effect of stress resistance is also large.

【0009】図2(a)及び(b)は本発明の第2実施
例の平面図とそのB−B線断面図である。図1の実施例
と同一部分には同一符号を付してある。この実施例で
は、ダミー用導体膜15を半導体装置周辺部のコーナ領
域隣接部の第2の配線用導体膜14のみを覆うように形
成している。この実施例においても、ダミー用導体膜1
5によって応力を吸収し、或いは緩和することができ、
層間絶縁膜22のクラック防止や第2の配線用導体膜1
4のずれを有効に防止することができる。なお、ダミー
用導体膜15はアルミニウムの場合、幅は前記第2の配
線用導体膜14より20μm大きいのが適当であり、耐
応力性の効果も大きい。
FIGS. 2A and 2B are a plan view and a sectional view taken along line BB of a second embodiment of the present invention. The same parts as those in the embodiment of FIG. 1 are denoted by the same reference numerals. In this embodiment, the dummy conductor film 15 is formed so as to cover only the second wiring conductor film 14 adjacent to the corner area around the semiconductor device. Also in this embodiment, the dummy conductor film 1 is used.
5 can absorb or relieve stress,
Crack prevention of the interlayer insulating film 22 and the second wiring conductor film 1
4 can be effectively prevented. When the dummy conductor film 15 is made of aluminum, its width is suitably larger than that of the second wiring conductor film 14 by 20 μm, and the effect of stress resistance is great.

【0010】[0010]

【発明の効果】 以上説明したように本発明は、配線用
導体膜を覆う絶縁膜が形成され、半導体装置の周辺部の
コーナー隣接領域の前記配線用導体膜に沿ってかつ前記
絶縁膜の上側から前記配線用導体膜を覆うダミー用導体
膜が形成されているので、封止用の樹脂等から生じる応
力をダミー用導体膜によって吸収し、或いは緩和し、配
線用導体膜に加わらなくすることができる。これによ
り、配線用導体膜を囲む絶縁膜等のクラックの発生や配
線用導体膜のずれを防止し、配線の信頼性を著しく高め
ることができる効果がある。
As described above, according to the present invention, an insulating film is formed to cover a wiring conductor film, and the insulating film is formed along the wiring conductor film in a region adjacent to a corner in a peripheral portion of a semiconductor device and above the insulating film. Since the dummy conductor film covering the wiring conductor film is formed from above, the stress generated from the sealing resin or the like is absorbed or reduced by the dummy conductor film so as not to be applied to the wiring conductor film. Can be. This has the effect of preventing the occurrence of cracks in the insulating film or the like surrounding the wiring conductor film and the displacement of the wiring conductor film, thereby significantly improving the reliability of the wiring.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例の周辺部の平面図とそのA
−A線断面図である。
FIG. 1 is a plan view of a peripheral portion of a first embodiment of the present invention and FIG.
FIG. 4 is a cross-sectional view taken along a line A.

【図2】本発明の第2実施例の周辺部の平面図とそのB
−B線断面図である。
FIG. 2 is a plan view of a peripheral portion of a second embodiment of the present invention and FIG.
FIG. 4 is a cross-sectional view taken along line B.

【図3】従来の半導体装置の一例の平面図とそのC−C
線断面図である。
FIG. 3 is a plan view of an example of a conventional semiconductor device and its CC.
It is a line sectional view.

【図4】配線用導体膜のスライドを説明するためのモデ
ル図である。
FIG. 4 is a model diagram for explaining sliding of a wiring conductive film.

【符号の説明】[Explanation of symbols]

10 半導体基板 12,13 第1の配線用導体膜 14 第2の配線用導体膜 15 ダミー用導体膜 20 第1の層間絶縁膜 21 第2の層間絶縁膜 22 第3の層間絶縁膜 23 保護用絶縁膜 DESCRIPTION OF SYMBOLS 10 Semiconductor substrate 12, 13 First wiring conductor film 14 Second wiring conductor film 15 Dummy conductor film 20 First interlayer insulating film 21 Second interlayer insulating film 22 Third interlayer insulating film 23 For protection Insulating film

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板に絶縁膜を介して周辺部に沿う
ように配線用導体膜を形成した半導体装置において、前
記配線用導体膜を覆う絶縁膜が形成され、半導体装置の
周辺部のコーナー隣接領域の前記配線用導体膜に沿って
かつ前記絶縁膜の上側から前記配線用導体膜を覆うダミ
ー用導体膜が形成されていることを特徴とする半導体装
置。
1. A semiconductor substrate is formed along an edge of a semiconductor substrate via an insulating film.
In the semiconductor device in which the wiring conductor film is formed as described above, an insulating film covering the wiring conductor film is formed, and is located along the wiring conductor film in a region adjacent to a corner in a peripheral portion of the semiconductor device and above the insulating film. Forming a dummy conductor film covering the wiring conductor film.
JP04245904A 1992-08-22 1992-08-22 Semiconductor device Expired - Fee Related JP3098333B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04245904A JP3098333B2 (en) 1992-08-22 1992-08-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04245904A JP3098333B2 (en) 1992-08-22 1992-08-22 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0669212A JPH0669212A (en) 1994-03-11
JP3098333B2 true JP3098333B2 (en) 2000-10-16

Family

ID=17140557

Family Applications (1)

Application Number Title Priority Date Filing Date
JP04245904A Expired - Fee Related JP3098333B2 (en) 1992-08-22 1992-08-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JP3098333B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001210744A (en) 2000-01-25 2001-08-03 Nec Corp Circuit board

Also Published As

Publication number Publication date
JPH0669212A (en) 1994-03-11

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