JPS6156608B2 - - Google Patents
Info
- Publication number
- JPS6156608B2 JPS6156608B2 JP4995277A JP4995277A JPS6156608B2 JP S6156608 B2 JPS6156608 B2 JP S6156608B2 JP 4995277 A JP4995277 A JP 4995277A JP 4995277 A JP4995277 A JP 4995277A JP S6156608 B2 JPS6156608 B2 JP S6156608B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- wiring
- electrode wiring
- semiconductor substrate
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 31
- 239000000758 substrate Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 238000002161 passivation Methods 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Landscapes
- Structure Of Printed Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は、トランジスタ、ICなど電子部品の
配線に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to wiring for electronic components such as transistors and ICs.
従来、電子部品たとえば半導体ICの電極配線
は、ダイオードやトランジスタなどの半導体素子
が設けられている半導体基板上でアルミニウム真
空蒸着とフオトエツチング技術を用いて形成さ
れ、その表面を絶縁膜によつて表面保護している
のが一般的である。 Conventionally, electrode wiring for electronic components such as semiconductor ICs has been formed using aluminum vacuum evaporation and photoetching technology on a semiconductor substrate on which semiconductor elements such as diodes and transistors are provided, and the surface is covered with an insulating film. Generally protected.
しかしながら、従来のこの種の電極配線は、そ
れを表面保護している酸化シリコン膜やリンシリ
ケートガラス膜などの表面保護膜にクラツクを発
生させ、信頼度を低下させている。これは特に、
ボンデイングパツド部などの配線面積が大きく、
しかもコーナ部の多い個所に多発していることに
より、電極配線の各コーナにアルミニウム配線と
表面保護膜との熱膨張係数差によるストレス（応
力集中）が生に、そのストレスの突破口として表
面保護膜のクラツクという現象が生ずるものと考
えられる。 However, in this type of conventional electrode wiring, cracks occur in the surface protection film such as a silicon oxide film or a phosphosilicate glass film that protects the surface of the electrode wiring, reducing reliability. This is especially
The wiring area such as the bonding pad part is large,
Moreover, because they occur frequently in areas with many corners, stress (stress concentration) is generated at each corner of the electrode wiring due to the difference in thermal expansion coefficient between the aluminum wiring and the surface protective film. It is thought that a phenomenon called crack occurs.
そこで、本発明は、この種の現象にともなう表
面保護膜のクラツクを防止し、もつて高信頼度の
デバイスを得る新規な電極配線を提供することを
目的とするものである。 SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a novel electrode wiring that prevents the surface protective film from cracking due to this type of phenomenon and provides a highly reliable device.
このような目的を達成するための本発明の要旨
は、
(a) 半導体基体と
(b) その主表面に形成された複数の半導体素子と
(c) 上記複数の半導体素子間又は外部端子と上記
複数の半導体素子間を電気的に接続するため
に、上記半導体基体上に絶縁膜を介して設けら
れた配線層と
(d) 上記配線層および上記絶縁膜上に形成された
クラツクを生じ易い保護膜とよりなる半導体集
積回路装置の製造方法において、上記配線層を
パターニングする為の転写用マスク・パターン
として上記配線のコーナ部に対応する平面パタ
ーンが多角形状又は円形状の平面パターンを用
いることを特徴とする半導体集積回路装置の製
造法にある。 The gist of the present invention to achieve such an object is as follows: (a) a semiconductor substrate; (b) a plurality of semiconductor elements formed on the main surface thereof; and (c) between the plurality of semiconductor elements or between the external terminals and the above. (d) a wiring layer provided on the semiconductor substrate via an insulating film in order to electrically connect a plurality of semiconductor elements; and (d) a crack-prone protection formed on the wiring layer and the insulating film. In the method of manufacturing a semiconductor integrated circuit device comprising a film, a plane pattern having a polygonal or circular plane pattern corresponding to the corner part of the wiring is used as a transfer mask pattern for patterning the wiring layer. The feature lies in a method of manufacturing a semiconductor integrated circuit device.
以下、本発明の一実施例である半導体ICの電
極配線を図面を参照しながら詳述する。 EMBODIMENT OF THE INVENTION Hereinafter, electrode wiring of a semiconductor IC which is an embodiment of the present invention will be described in detail with reference to the drawings.
第１図は、本発明の一実施例である半導体IC
の電極配線を示す平面図であり、第２図は第１図
におけるAA′矢視断面図である。同図において、
１はシリコン等の半導体基板でダイオードやトラ
ンジスタ等の半導体素子が数多く設けられている
ものである。２は、酸化シリコン膜等のフイール
ド絶縁膜で半導体基板１表面を被覆して、素子表
面を安定化しているものである。３は、本発明の
特徴である平面パターンを有するアルミニウム電
極配線で、半導体基板に設けられている半導体素
子からフイールド絶縁膜における電極用窓を通し
てオーミツクコンタクトされている配線部３ａ
と、外部リードに金属細線を介して相互接続する
際、金属細線をボンデイングするボンデイングパ
ツド電極部３ｂとから構成されているものであ
る。なお、図中、２点鎖線は表面保護膜であるパ
ツシベーシヨン膜あるいはそれに穿設されている
ボンデイング用窓を示すものである。 Figure 1 shows a semiconductor IC that is an embodiment of the present invention.
FIG. 2 is a plan view showing the electrode wiring of FIG. In the same figure,
1 is a semiconductor substrate made of silicon or the like, on which many semiconductor elements such as diodes and transistors are provided. In No. 2, the surface of the semiconductor substrate 1 is coated with a field insulating film such as a silicon oxide film to stabilize the element surface. Reference numeral 3 denotes an aluminum electrode wiring having a planar pattern, which is a feature of the present invention, and a wiring portion 3a that is in ohmic contact from a semiconductor element provided on a semiconductor substrate through an electrode window in a field insulating film.
and a bonding pad electrode portion 3b for bonding the thin metal wire when interconnecting the external lead via the thin metal wire. In the figure, the two-dot chain line indicates a passivation film which is a surface protection film or a bonding window formed therein.
そして、本発明にかかる半導体ICの電極配線
３は、その平面形状において、各コーナ部をでき
るだけゆるやかな稜角を描く（稜角が鈍角とな
る）ように、多角形状としておる。これは、ボン
デイングパツド電極部３ｂ等の広面積領域のみ
が、上述したような多角形状のものとし、配線幅
の小さい配線部３ａは従来通りのコーナ部のよう
に稜角が直角であるようにした態様とすることも
できる。また、電極配線３のコーナ各部を円形状
のものとした態様とすることもできる。 The electrode wiring 3 of the semiconductor IC according to the present invention has a polygonal shape in its planar shape so that each corner has a ridge angle as gentle as possible (the ridge angle is an obtuse angle). This is because only the large area area such as the bonding pad electrode part 3b has a polygonal shape as described above, and the wiring part 3a with a small wiring width has a right-angled edge angle like the conventional corner part. It is also possible to adopt a mode in which: Further, each corner portion of the electrode wiring 3 may have a circular shape.
この種の電極配線３は、公知のアルミニウム真
空蒸着とフオトエツチング技術を用いて製作する
ことができる。その場合、従来と異なる点は、電
極配線パターンを形成するフオトエツチング工程
に使用するフオトマスクパターンのみである。フ
オトマスクを形成する際、その電極配線パターン
におけるコーナ部を多角形状にすることは容易で
あるが、円形状のものとすることは現状のフオト
リソ技術からみて、問題が生ずる場合は、可及的
に円形状に近い多角形状のものにして行なえばよ
い。 This type of electrode wiring 3 can be manufactured using known aluminum vacuum deposition and photoetching techniques. In this case, the only difference from the conventional method is the photomask pattern used in the photoetching process to form the electrode wiring pattern. When forming a photomask, it is easy to make the corners of the electrode wiring pattern polygonal, but considering the current photolithography technology, it is difficult to make the corners of the electrode wiring pattern polygonal. It may be made into a polygonal shape close to a circular shape.
上述したように、本発明にかかる半導体ICの
電極配線３は、そのコーナー部が多角形状または
円形状のものであるため、この電極配線３とこれ
を表面保護しているパツシベーシヨン膜との熱膨
張係数差によるストレスが、電極配線３のコーナ
部に集中することがなくストレス集中の分散が生
に、上記パツシベーシヨン膜のこの種のストレス
によるクラツク等の破損が防止できるものであ
る。そのため、本発明にかかるデバイスは、表面
保護効果の十全なパツシベーシヨン膜によつて電
極配線および半導体基体に設けられている半導体
素子を被覆できるため、特性劣化や不良事故の発
生等がない高信頼度のものである。 As described above, since the corner portions of the electrode wiring 3 of the semiconductor IC according to the present invention are polygonal or circular, thermal expansion between the electrode wiring 3 and the passivation film that protects the surface of the electrode wiring 3 may occur. The stress due to the difference in coefficients is not concentrated on the corner portions of the electrode wiring 3, and the stress concentration is effectively dispersed, thereby preventing damage such as cracks in the passivation film due to this type of stress. Therefore, since the device according to the present invention can cover the electrode wiring and the semiconductor element provided on the semiconductor substrate with a passivation film that has a sufficient surface protection effect, it is highly reliable without deterioration of characteristics or occurrence of defects. It is a matter of degree.
本発明は、上述した実施例に限定されず、ダイ
オード、トランジスタ、サイリスタ等のデイスク
リート素子、バイポーラIC、MISIC、ハイブリ
ツドIC等のICなど種々の態様の電子部品におけ
る電極配線に適用でき、その電極配線材料もアル
ミニウム、シリコン入りアルミニウム、金等を使
用している耐食性配線材料としたものに適用でき
る。 The present invention is not limited to the embodiments described above, and can be applied to electrode wiring in various types of electronic components such as discrete elements such as diodes, transistors, and thyristors, and ICs such as bipolar ICs, MISICs, and hybrid ICs. Corrosion-resistant wiring materials using aluminum, silicon-containing aluminum, gold, etc. can also be used as wiring materials.
第１図は、本発明の一実施例である半導体IC
の電極配線を示す平面図、第２図は第１図におけ
るAA′矢視断面図である。
１……素子が設けられている半導体基体、２…
…フイールド絶縁膜、３……電極配線、３ａ……
電極配線３における配線部、３ｂ……電極配線３
におけるパツド電極部。
Figure 1 shows a semiconductor IC that is an embodiment of the present invention.
FIG. 2 is a cross-sectional view taken along the line AA' in FIG. 1. 1... Semiconductor substrate on which an element is provided, 2...
...Field insulating film, 3... Electrode wiring, 3a...
Wiring part in electrode wiring 3, 3b...electrode wiring 3
Pad electrode part.
Claims (1)
複数の半導体素子間を電気的に接続するため
に、上記半導体基体上に絶縁膜を介して設けら
れた配線層と (d) 上記配線層および上記絶縁膜上に形成された
クラツクを生じ易い保護膜とよりなる半導体集
積回路装置の製造方法において、上記配線層を
パターニングする為の転写用マスク・パターン
として上記配線のコーナ部に対応する平面パタ
ーンが多角形状又は円形状の平面パターンを用
いることを特徴とする半導体集積回路装置の製
造方法。[Scope of Claims] 1. (a) A semiconductor substrate, (b) a plurality of semiconductor elements formed on the main surface thereof, and (c) an electrical connection between the plurality of semiconductor elements or between an external terminal and the plurality of semiconductor elements. a semiconductor integrated circuit device comprising: a wiring layer provided on the semiconductor substrate via an insulating film in order to connect to the semiconductor substrate; and (d) a protective film that is prone to cracks and formed on the wiring layer and the insulating film. In the manufacturing method of the semiconductor integrated circuit device, a plane pattern having a polygonal or circular plane pattern corresponding to a corner portion of the wiring is used as a transfer mask pattern for patterning the wiring layer. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4995277A JPS53135585A (en) | 1977-05-02 | 1977-05-02 | Wiring for electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4995277A JPS53135585A (en) | 1977-05-02 | 1977-05-02 | Wiring for electronic components |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5589385A Division JPS60242643A (en) | 1985-03-22 | 1985-03-22 | Wiring for electronic part |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53135585A JPS53135585A (en) | 1978-11-27 |
| JPS6156608B2 true JPS6156608B2 (en) | 1986-12-03 |
Family
ID=12845362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4995277A Granted JPS53135585A (en) | 1977-05-02 | 1977-05-02 | Wiring for electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS53135585A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63305309A (en) * | 1987-06-05 | 1988-12-13 | Akai Electric Co Ltd | Connecting device for optical fiber |
| JPH0511528Y2 (en) * | 1986-11-17 | 1993-03-23 |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56162854A (en) * | 1980-05-20 | 1981-12-15 | Nec Corp | Semiconductor integrated circuit device |
| JPS5745259A (en) * | 1980-09-01 | 1982-03-15 | Hitachi Ltd | Resin sealing type semiconductor device |
| JPS5756935A (en) * | 1980-09-22 | 1982-04-05 | Nec Corp | Semiconductor device |
| JPS5936945A (en) * | 1982-08-24 | 1984-02-29 | Mitsubishi Electric Corp | Input connection terminal of semiconductor device |
| JPS61255039A (en) * | 1985-05-07 | 1986-11-12 | Rohm Co Ltd | Semiconductor device |
| JPH0373438U (en) * | 1989-11-21 | 1991-07-24 | ||
| KR20070073984A (en) | 1998-05-19 | 2007-07-10 | 이비덴 가부시키가이샤 | Printed circuit board and method of production thereof |
| JP6040456B2 (en) * | 2010-01-15 | 2016-12-07 | ローム株式会社 | Semiconductor device and manufacturing method thereof |
| JP2018139290A (en) * | 2018-03-28 | 2018-09-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
-
1977
- 1977-05-02 JP JP4995277A patent/JPS53135585A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0511528Y2 (en) * | 1986-11-17 | 1993-03-23 | ||
| JPS63305309A (en) * | 1987-06-05 | 1988-12-13 | Akai Electric Co Ltd | Connecting device for optical fiber |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53135585A (en) | 1978-11-27 |
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