JPS6248026A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain reliable semiconductor device having a passivation film for preventing a crack by forming a slit in the passivation film portion disposed around metal wirings. CONSTITUTION:A slit 12 is formed in a passivation film 10 portion disposed around aluminum wiring 8, 9. According to this configuration, a thermal stress due to the difference of thermal expansion coefficients among an aluminum gate electrode 7, the wirings 8, 9 and the film 10 is generated in the film 10 at sintering time, but since the slit 12 is formed in the film 10 portion disposed around the wiring 8, 9, the stress can be released by the slit 12. As a result, it can prevent the film 10 from cracking to prevent moisture from entering the interior, thereby providing a semiconductor device having no aluminum corrosion nor loss of aluminum and high reliability.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which the shape of a /'P tsipation film is improved.

[Technical background of the invention]

2. Description of the Related Art In a semiconductor device, a passivation film is usually formed to cover the wiring and the like after the wiring is formed, in order to prevent moisture and the like from the outside world from penetrating into the elements and wiring.

Incidentally, a semiconductor device having the above-described structure, for example, an n-channel MO8 integrated circuit having an At gate, has conventionally had the structure shown in FIG. 2. That is, 1 in the figure is a p-type silicon substrate. On the surface of the substrate 1, n-type source and drain regions 2.3 are provided.

A dirt oxide film 4 is formed on the surface of the substrate 1 including between these source and drain regions 2 and 3. A thick oxide film 5 is provided on the substrate 1 except for the dirt oxide film 4.

A contact hole 6 is formed in a portion of the oxide film 5 corresponding to a portion of the source and drain regions 2 and 3. On the dirt oxide film 4, kl)y”-)
An electrode 7 is provided, and a portion of the dirt electrode 7 extends over the thick oxide film 5. Further, on the thick oxide film 5, source and drain At wirings 8 and 9 are provided which are connected to the source and drain regions 2 and 3 through the contact hole 6, respectively. Then, on the thick oxide film 5 including the dirt electrode 7 and the At wirings 8 and 9,
A passivation film 10 made of silicon nitride or the like is coated. In addition, t of this arm nosipation film 10
A hole is formed in a portion corresponding to a pole-# Rad portion (not shown), and the same pad portion is exposed.

[Problems with background technology]

However, in the MO8 integrated circuit with the above structure, /? When heat treatment (sintering) is performed after coating the passivation film 10, stress is generated due to the difference in thermal expansion between the passivation film 10 and the At wires 8 and 9 below, and this causes the Crack 1 in membrane 10
There was a problem that 1 occurred. These cracks 1
If this occurs in the pad page film IQ, the completed semiconductor device will suffer from corrosion of the M wirings 8, 9 and dirt electrodes 7 due to moisture entering from the outside world, resulting in a decrease in reliability.

[Purpose of the invention]

SUMMARY OF THE INVENTION The present invention aims to provide a semiconductor device having a non-crack-free film.

[Summary of the invention]

The present invention provides a semiconductor substrate, an insulating film provided on the substrate, a metal wiring provided on the insulating film, a passivation film provided on the insulating film including the metal wiring, and a passivation film provided on the insulating film including the metal wiring. and a slit provided in the noccupation film portion located around the periphery of the semiconductor device. According to the present invention 8AK, it is possible to obtain a highly reliable semiconductor device having a passivation film in which cracks and scratches are prevented from occurring.

[Embodiments of the invention]

Hereinafter, an example in which the present invention is applied to an n-channel U-dart MO8 integrated circuit will be described with reference to FIG. Components similar to those shown in FIG. 2 described above are designated by the same reference numerals, and description thereof will be omitted.

The MO8 integrated circuit of the present invention has a position t around the M wirings 8 and 9.
It has a structure in which a slit 12 is provided in the part of the sipation film 10.
/4' It is possible to form the hole at the same time as the photolithography for forming the electrode node in the oxidation film 10.

According to such a configuration, during sinkling, A
te-) Thermal stress due to the difference in thermal expansion coefficient between the electrode 2, the At wirings 8 and 9, and the mother passivation film 10 causes the The heat stress generated in the tsusipation film 10 can be released because the slit 12 is provided in the part of the tsusipation film 10 located around the kl wirings 8 and 9. As a result, it is possible to prevent the occurrence of cracks in the A/dissipation film 10, prevent the infiltration of moisture, etc., and obtain a highly reliable semiconductor device free from corrosion and loss of At.

Further, since the slits 12 can be formed in parallel when forming the openings of the electrode/9-rad portions, the effects described above can be achieved without increasing the number of steps.

In the above embodiments, an n-channel MO8 integrated circuit has been described, but the invention is not limited thereto, and can be similarly applied to, for example, a p-channel MO8 semiconductor device, a bipolar type semiconductor device, and the like.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a highly reliable semiconductor device that has a passivation film that does not generate cracks and prevents corrosion of metal wiring.

[Brief explanation of the drawing]

FIG. 1 shows an n-channel MO8 illustrating an embodiment of the present invention.
A cross-sectional view of the integrated circuit, FIG. 2, shows a conventional n-channel MO
8 is a cross-sectional view showing an integrated circuit. 1...p-type silicon substrate, 2...n-type source region,
3...n-type drain region, 4...f-) oxide film, 5
... Thick oxide film, 6... Contact hole, 7...
・kt gate electrode, 8...At source wiring, 9...
At drain wiring, 10...ri, etc., tsipation m, 1
2...Slit.

Claims (1)

[Claims] A semiconductor substrate, an insulating film provided on this substrate, a metal wiring provided on this insulating film, a passivation film provided on an insulating film including this metal wiring, and a position around the metal wiring. A slit provided in the passivation film portion.