JPS6367754A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6367754A JPS6367754A JP21312386A JP21312386A JPS6367754A JP S6367754 A JPS6367754 A JP S6367754A JP 21312386 A JP21312386 A JP 21312386A JP 21312386 A JP21312386 A JP 21312386A JP S6367754 A JPS6367754 A JP S6367754A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- gate
- molybdenum silicide
- phosphorus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 12
- 239000011574 phosphorus Substances 0.000 abstract description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 11
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 abstract description 8
- 230000001681 protective effect Effects 0.000 abstract description 5
- 230000007423 decrease Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910000714 At alloy Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000007774 longterm Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 150000003017 phosphorus Chemical class 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係シ、特に２層ゲート構造を有す
るＭＯ８形牛形体導体素子上ンディングパッドの構造に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and more particularly to the structure of a landing pad on an MO8 type cow-shaped conductor element having a two-layer gate structure.
従来、この種の半導体装置は、そのポンディングパッド
部分の断面および平面図をそれぞれ第３図、第４図に示
すように、回路素子が組み込まれたシリコン基板１の上
にフィール、ド酸化膜２およびリンを含有する二酸化硅
素膜（以下、ＰＳＧｇと称す）７を順次形成したうえ、
とのＰＳＧ膜Ｔ上に蒸着などによシアルミニウム（以下
、Ａｔと記す）膜１０を形成する。そして、これをパタ
ーニングした後、絶縁保護膜９を被着してそのＡ４膜１
０上のボンディング部のみを開孔させることによシ、こ
の回礼されたＡｚ、［１０をポンディングパッドとして
金（Ａｕ）などのリード線（図示せず）Ｋてボンディン
グするものとなっている。なお、同図中、９ａは絶縁保
護膜９に設けられた開孔部である。Conventionally, this type of semiconductor device has been manufactured by depositing a field oxide film on a silicon substrate 1 in which circuit elements are incorporated, as shown in FIG. 3 and FIG. After sequentially forming a silicon dioxide film (hereinafter referred to as PSGg) 7 containing 2 and phosphorus,
A sialumium (hereinafter referred to as At) film 10 is formed on the PSG film T by vapor deposition or the like. After patterning this, an insulating protective film 9 is applied to the A4 film 1.
By opening only the bonding part on the bonding part 0, bonding is performed using a lead wire (not shown) made of gold (Au) or the like using the rounded Az and [10 as a bonding pad. . In addition, in the same figure, 9a is an opening provided in the insulating protective film 9.
しかし、従来の半導体装置は以上のような構造を有して
いるので、ＰＳＧ膜Ｔ中の不純物特にリンのｈｔＦＡ１
０中への拡散が起こ）易く、このリンの影響による初期
ボンディング性の低下、あるいは金−Ａｔ合金層の高温
時の早期劣化、水分の侵入によシリン酸が発生しＡｔを
腐食させる耐温性不良現象などを引き起こすという問題
点があった。However, since the conventional semiconductor device has the above structure, impurities in the PSG film T, especially phosphorus htFA1
The influence of this phosphorus can cause a decrease in initial bonding properties, or the early deterioration of the gold-At alloy layer at high temperatures, and the intrusion of moisture can generate silicic acid, which corrodes At. There was a problem in that it caused problems such as sexual delinquency.
本発明は上記のような問題点を解消するためになされた
もので、その目的は、２層ゲート構造を有する半導体装
置においてポンデイングパットニシリコンを含有するア
ルミ・シリコン（Ａｔ−８１）膜またはＡ４膜を用いる
際にそのアルミ・シリコン膜またはＡｔ膜へのリンの拡
散を抑制することにより、信頼性を向上させた半導体装
置を提供することにある。The present invention has been made in order to solve the above-mentioned problems, and its purpose is to provide a semiconductor device having a two-layer gate structure with an aluminum silicon (At-81) film containing bonded silicon or An object of the present invention is to provide a semiconductor device with improved reliability by suppressing the diffusion of phosphorus into an aluminum silicon film or an At film when an A4 film is used.
本発明に係る半導体装置は、シリコン基板上にフィール
ド酸化膜、第４ゲートとしてドープトポリシリコン膜を
形成し、該ドープトポリシリコン膜を覆うように形成さ
れた二酸化硅素膜上に第２ゲートを設置する２層ゲート
構造を備えた半導体装置において、前記第２ゲートは、
前記二酸化硅素膜上に順次設置されたリンをドープした
ポリシリコン膜およびモリブデンシリサイド膜からなり
、前記モリブデンシリサイド膜の上にＰＳＧｉまたはＢ
ＰＳＧ膜を設置して、とのＰＳＧ膜またはＢＰＳＧ膜の
ポンディングパッド部に相当する部分のみをエッチング
により開孔させたうえ、その部分にＡｔ膜もしくはアル
ミ・シリコン膜を設けてなるものである。In the semiconductor device according to the present invention, a field oxide film and a doped polysilicon film are formed as a fourth gate on a silicon substrate, and a second gate is formed on a silicon dioxide film formed to cover the doped polysilicon film. In the semiconductor device equipped with a two-layer gate structure in which the second gate is provided with
It consists of a phosphorus-doped polysilicon film and a molybdenum silicide film which are sequentially disposed on the silicon dioxide film, and PSGi or B is formed on the molybdenum silicide film.
A PSG film is installed, a hole is made by etching only the part corresponding to the bonding pad part of the PSG film or BPSG film, and an At film or an aluminum/silicon film is provided in that part. .
本発明においては、第２ゲートを、リンをドープしたポ
リシリコン膜とモリブデンシリサイド膜から構成して、
このモリブデンシリサイド膜の上にＡｔ膜もしくはアル
ミ・シリコン膜を設置スルことによシ、前記リンをドー
プしたポリシリコン膜とモリブデンシリサイド膜は、Ｐ
ＳＧ膜またはＢＰＳＧｉ中のリンが拡散するのを防止す
るバリアメタルとしての機能を持つこととなる。In the present invention, the second gate is composed of a phosphorus-doped polysilicon film and a molybdenum silicide film,
By installing an At film or an aluminum/silicon film on this molybdenum silicide film, the phosphorus-doped polysilicon film and molybdenum silicide film are
It functions as a barrier metal that prevents phosphorus in the SG film or BPSGi from diffusing.
以下、本発明を図面に示す実施例に基づいて詳細に説明
する。Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.
第１図は本発明の一実施例による半導体装置のポンディ
ングパッド部分の概略断面図で、第２図はその平面図で
ある。これらの図において、１はシリコン基板、２はフ
ィールド酸化膜、３は第１ゲートとしてのドープトポリ
シリコン膜、４は二酸化硅素膜、５はリンをドープした
ポリシリコン膜、６はモリブデンシリサイド膜で１、こ
れらポリシリコン膜５とモリブデンシリサイド膜６によ
り第２ゲートを構成している。また、７はＰＳＧ膜、８
はシリコンを含有させたＡｔＨつまシアルミ・シリコン
（Ａｔ−８ｉ）膜、９は絶縁保饅膜である。FIG. 1 is a schematic sectional view of a bonding pad portion of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view thereof. In these figures, 1 is a silicon substrate, 2 is a field oxide film, 3 is a doped polysilicon film as a first gate, 4 is a silicon dioxide film, 5 is a phosphorus-doped polysilicon film, and 6 is a molybdenum silicide film. 1, these polysilicon film 5 and molybdenum silicide film 6 constitute a second gate. In addition, 7 is a PSG film, 8
9 is an AtH aluminum silicon (At-8i) film containing silicon, and 9 is an insulating film.
すなわち、この実施例では、シリコン基板１上に形成さ
れたフィールド酸化膜２の上に第１ゲートとしてドープ
トポリシリコン膜３を形成させたうえ、このドープトポ
リシリコン膜３を覆うように二酸化硅素膜４を形成する
。そして、この二酸化硅素膜４上に、第２ゲートとして
リンをドープしたポリシリコン膜５およびモリブデンシ
リサイド膜６を順に設置する。さらに、その上にＰＳＧ
膜７を設置し、とのＰＳＧｉ７のポンディングパッドに
相当する部分のみをエッチングにより除去して開孔部γ
＆を施したうえ、この開孔部７ａを含むＰＳＧ膜７の上
にスパッタリング法によシアルミ・シリコン膜８を被着
する。次いで、このアルミ・シリコン膜８を所定形状に
バターニングした後、その上に絶縁保穫膜９を被着して
、この膜９のポンディングパッドに相当する部分を開孔
させることにより、第１図に示すように、その部分にア
ルミ・シリコン膜８をポンディングパッドとして露出さ
せて形成したものである。々お、図中、同一符号は同一
または相当部分を示している。That is, in this embodiment, a doped polysilicon film 3 is formed as a first gate on a field oxide film 2 formed on a silicon substrate 1, and then a doped polysilicon film 3 is formed to cover this doped polysilicon film 3. A silicon film 4 is formed. Then, on this silicon dioxide film 4, a phosphorus-doped polysilicon film 5 and a molybdenum silicide film 6 are sequentially provided as a second gate. Furthermore, on top of that, PSG
The membrane 7 is installed, and only the portion corresponding to the bonding pad of the PSGi 7 is removed by etching to form the opening γ.
&, and then a sialuminium-silicon film 8 is deposited on the PSG film 7 including the opening 7a by sputtering. Next, after patterning this aluminum/silicon film 8 into a predetermined shape, an insulating protective film 9 is applied thereon, and a hole is formed in a portion of this film 9 corresponding to a bonding pad. As shown in FIG. 1, an aluminum/silicon film 8 is exposed and formed in that portion as a bonding pad. In the figures, the same reference numerals indicate the same or corresponding parts.
このように上記実施例によると、第２ゲートのリンをド
ープしたポリシリコン膜５とモリブデンシリサイド膜６
を設け、このモリブデンシリサイド膜６０上にアルミ・
シリコン膜８を設置することによシ、このアルミ・シリ
コン膜８とＰＳＧ膜７とが接融する部分を少なくして、
そのＰＳＧ膜７中のリンの拡散をモリブデンシリサイド
膜６をバリアメタルとして防止できるので、ＰＳＧＪＪ
Ｔ中のリンがアルミ・シリコン膜８中へ拡散するのを抑
制できる。これによって、ＰＳＧ膜Ｔ中のリンの影響に
よる初期ボンディング性の低下を防ぐことができるとと
もに、膜の界面を通じて侵入した水とＰｇＧｇ％Ｔ中の
リンとの反応を防止することができる。In this way, according to the above embodiment, the phosphorus-doped polysilicon film 5 and the molybdenum silicide film 6 of the second gate
on this molybdenum silicide film 60.
By providing the silicon film 8, the area where the aluminum/silicon film 8 and the PSG film 7 are fused can be reduced.
Since the diffusion of phosphorus in the PSG film 7 can be prevented by using the molybdenum silicide film 6 as a barrier metal, PSGJJ
Diffusion of phosphorus in T into the aluminum/silicon film 8 can be suppressed. Thereby, it is possible to prevent a decrease in initial bonding properties due to the influence of phosphorus in the PSG film T, and it is also possible to prevent a reaction between water that has entered through the interface of the film and phosphorus in PgGg%T.
さらに、ＰＳＧ膜γにボロンを添加することによシリン
濃度を減少せしめて、ボンディング時の金−Ａｔ合金層
に悪影響を及ぼすリンの拡散を抑えることができるなど
、長期的信頼性の向上がはかれる利点を奏する。Furthermore, by adding boron to the PSG film γ, it is possible to reduce the syringe concentration and suppress the diffusion of phosphorus, which has an adverse effect on the gold-At alloy layer during bonding, improving long-term reliability. play an advantage.
なお、上記実施例ではＰＳＧ腹を用いる場合について示
したが、本発明はこれに限らず、リンおよびボロンを含
有する二酸化硅素膜つまｆｉ ＢＰＳＧ膜を用いる場合
やアルミ・シリコン膜の他にＡｔ膜を用いる場合にも適
用して、上記実施例と同様の効果を得ることができる。In addition, although the above embodiment shows a case where a PSG antinode is used, the present invention is not limited to this, and the present invention is not limited to this. The same effect as in the above embodiment can be obtained by applying the present invention to the case where the above embodiment is used.
以上のように本発明によれば、ポンディングパッド部の
構造を、Ａｔ膜もしくはアルミ・シリコン膜の下にポリ
シリコン膜およびモリブデンシリサイド膜を設け、しか
もこの人を膜もしくはアルミ・シリコン膜とポリシリコ
ン膜、モリブデンシリサイド膜の下にはＰＳＧｙＸ″＆
たはＢＰＳＧ膜が存在しないように構成したので、ボン
ディング性の向上が計れるとともに、金−Ａｔ接合部の
早期劣化を防ぐことができ、これによって、半導体素子
の長期的信頼性を確保することが可能となる。As described above, according to the present invention, the structure of the bonding pad portion is such that a polysilicon film and a molybdenum silicide film are provided under an At film or an aluminum/silicon film, and the bonding pad portion is formed by forming a polysilicon film or a molybdenum silicide film under an At film or an aluminum/silicon film. Under the silicon film and molybdenum silicide film, PSGyX''&
Since the structure is configured so that no BPSG or BPSG film is present, it is possible to improve bonding properties and prevent early deterioration of the gold-At junction, thereby ensuring long-term reliability of the semiconductor device. It becomes possible.
第１図は本発明の一実施例による半導体装置のポンディ
ングパッド部を示す要部断面図、第２図は第１図の平面
図、第３図は従来の半導体装置のポンディングパッド部
の要部断面図、第４図は第３図の平面図である。
１・・・・シリコン基板、２・・・・フィールド酸化膜
、３・・・・ドープトポリシリコン膜、４・・・・二酸
化硅素膜、５・・・・ポリシリコン膜、６・・・・モリ
ブデンシリサイド膜、７・・・・ＰＳＧ膜、７ａ・・・
・開孔部、８・・・・アルミ・シリコン（ｈｔ−ｓｓ）
膜、９・・・・絶縁保護膜、９＆・・・・開孔部。FIG. 1 is a sectional view of a main part showing a bonding pad portion of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of FIG. 1, and FIG. 3 is a cross-sectional view of a bonding pad portion of a conventional semiconductor device. A sectional view of the main part, and FIG. 4 is a plan view of FIG. 3. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Field oxide film, 3... Doped polysilicon film, 4... Silicon dioxide film, 5... Polysilicon film, 6...・Molybdenum silicide film, 7...PSG film, 7a...
・Opening part, 8... Aluminum silicon (ht-ss)
Membrane, 9... Insulating protective film, 9 &... Opening portion.
Claims (1)
ドープトポリシリコン膜を形成し、該ドープトポリシリ
コン膜を覆うように形成された二酸化硅素膜上に第２ゲ
ートを設置する２層ゲート構造を備えた半導体装置にお
いて、前記第２ゲートは、前記二酸化硅素膜上に順次設
置されたリンをドープしたポリシリコン膜およびモリブ
デンシリサイド膜からなり、前記モリブデンシリサイド
膜の上にＰＳＧ膜またはＢＰＳＧ膜を設置して、このＰ
ＳＧ膜またはＢＰＳＧ膜のボンディングパッド部に相当
する部分のみをエッチングにより開孔させたうえ、その
部分にアルミニウム膜もしくはアルミ・シリコン膜を設
けてなることを特徴とする半導体装置。A two-layer gate structure is adopted in which a field oxide film and a doped polysilicon film are formed as a first gate on a silicon substrate, and a second gate is installed on a silicon dioxide film formed to cover the doped polysilicon film. In the semiconductor device, the second gate includes a phosphorus-doped polysilicon film and a molybdenum silicide film that are sequentially provided on the silicon dioxide film, and a PSG film or a BPSG film is provided on the molybdenum silicide film. Then, this P
A semiconductor device characterized in that a hole is formed by etching only a portion of an SG film or a BPSG film corresponding to a bonding pad portion, and an aluminum film or an aluminum/silicon film is provided in that portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21312386A JPS6367754A (en) | 1986-09-09 | 1986-09-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21312386A JPS6367754A (en) | 1986-09-09 | 1986-09-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6367754A true JPS6367754A (en) | 1988-03-26 |
| JPH0529139B2 JPH0529139B2 (en) | 1993-04-28 |
Family
ID=16633956
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21312386A Granted JPS6367754A (en) | 1986-09-09 | 1986-09-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6367754A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7679191B2 (en) | 2005-07-13 | 2010-03-16 | Nec Electronics Corporation | Polysilicon film with increased roughness |
-
1986
- 1986-09-09 JP JP21312386A patent/JPS6367754A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7679191B2 (en) | 2005-07-13 | 2010-03-16 | Nec Electronics Corporation | Polysilicon film with increased roughness |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0529139B2 (en) | 1993-04-28 |
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