JPH0565055B2 - - Google Patents
Info
- Publication number
- JPH0565055B2 JPH0565055B2 JP61179532A JP17953286A JPH0565055B2 JP H0565055 B2 JPH0565055 B2 JP H0565055B2 JP 61179532 A JP61179532 A JP 61179532A JP 17953286 A JP17953286 A JP 17953286A JP H0565055 B2 JPH0565055 B2 JP H0565055B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- diffusion prevention
- phosphorus
- phosphorus diffusion
- silicon dioxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 33
- 229910052698 phosphorus Inorganic materials 0.000 claims description 33
- 239000011574 phosphorus Substances 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 22
- 229910052782 aluminium Inorganic materials 0.000 claims description 22
- 238000009792 diffusion process Methods 0.000 claims description 21
- 230000002265 prevention Effects 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 18
- 235000012239 silicon dioxide Nutrition 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 claims description 7
- 229910021344 molybdenum silicide Inorganic materials 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- -1 gold-aluminum Chemical compound 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000003016 phosphoric acids Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01022—Titanium [Ti]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に関し、特に半導体素
子上のボンデイングパツド部の構造に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a bonding pad portion on a semiconductor element.
第３図は従来のボンデイングパツド部の構造を
示す断面図であり、１はシリコンからなる半導体
基板、２はこの上に形成されたフイールド酸化
膜、３はリンを含む二酸化ケイ素膜（PSG膜）、
４はアルミニウム膜、５はアルミニウム膜４上の
ボンデイング部のみ開口を設けた絶縁保護膜であ
る。
FIG. 3 is a cross-sectional view showing the structure of a conventional bonding pad section, in which 1 is a semiconductor substrate made of silicon, 2 is a field oxide film formed thereon, and 3 is a silicon dioxide film containing phosphorus (PSG film). ),
Reference numeral 4 indicates an aluminum film, and reference numeral 5 indicates an insulating protective film in which an opening is provided only at the bonding portion on the aluminum film 4.
従来の半導体装置は以上のような構造を有して
いるので、PSG膜中の不純物、特に、ガラスの
融点を下げ、カバリングを良くするために添加さ
れるリンのアルミニウム膜中への拡散が起こりや
すく、リンの影響による初期ボンデイング性の低
下、あるいはボンデイングワイヤを構成する金と
アルミニウムとの合金層の高温時の早期劣化、水
分の侵入によりリン酸が発生しアルミニウムを腐
食させるという耐湿性不良現象などの不具合を引
き起こす問題点を有していた。
Since conventional semiconductor devices have the structure described above, impurities in the PSG film, especially phosphorus, which is added to lower the melting point of glass and improve covering, diffuse into the aluminum film. Initial bonding performance deteriorates due to the influence of phosphorus, early deterioration occurs at high temperatures of the gold and aluminum alloy layer that makes up the bonding wire, and poor moisture resistance occurs when moisture enters and generates phosphoric acid, which corrodes aluminum. It had problems that caused problems such as:
この発明は上記のような問題点を解消するため
になされたもので、初期ボンデイング性の低下を
防ぐことができるとともに、膜の界面を通じて侵
入した水とPSG膜中のリンとの反応を抑制する
ことができ、さらに金−アルミニウム合金層に悪
影響を及ぼすリンの拡散を抑えることができる半
導体装置およびそのための製造方法を得ることを
目的とする。 This invention was made to solve the above-mentioned problems, and can prevent the initial bonding performance from deteriorating, and also suppresses the reaction between water that has entered through the film interface and phosphorus in the PSG film. It is an object of the present invention to provide a semiconductor device and a manufacturing method therefor that can further suppress the diffusion of phosphorus that adversely affects a gold-aluminum alloy layer.
本発明に係る半導体装置は、リンを含有する二
酸化ケイ素膜に開口を設け、この開口内にポリシ
リコン膜を形成し、この上チタンナイトライド膜
またはモリブデンシリサイド膜等のリン拡散防止
膜を形成し、このリン酸拡散防止膜上にボンデイ
ングパツドのアルミニウム膜を形成したものであ
る。
In the semiconductor device according to the present invention, an opening is provided in a silicon dioxide film containing phosphorus, a polysilicon film is formed in the opening, and a phosphorus diffusion prevention film such as a titanium nitride film or a molybdenum silicide film is formed thereon. , an aluminum film of a bonding pad is formed on this phosphoric acid diffusion prevention film.
また本発明に係る半導体装置の製造方法は、ボ
ンデイングパツド形成部にポリシリコン膜を形成
し、この上にリン拡散防止膜を形成した後、これ
を覆つてリンを含有する二酸化ケイ素膜を形成
し、次いでエツチングによりボンデイングパツド
形成部の上記二酸化ケイ素膜を除去し、露出した
上記リン拡散防止膜上にアルミニウム膜を形成す
るものである。 Further, in the method for manufacturing a semiconductor device according to the present invention, a polysilicon film is formed in a bonding pad formation area, a phosphorus diffusion prevention film is formed on this, and a silicon dioxide film containing phosphorus is then formed to cover this. Then, the silicon dioxide film in the bonding pad forming portion is removed by etching, and an aluminum film is formed on the exposed phosphorus diffusion prevention film.
アルミニウム膜の下にはリンを含む二酸化ケイ
素膜がなく、またチタンナイトライドまたはモリ
ブデンシリサイド等のリン拡散防止膜がバリアと
して作用するため、二酸化ケイ素膜内のリンがア
ルミニウム膜へ拡散することが阻止される。
There is no silicon dioxide film containing phosphorus under the aluminum film, and a phosphorus diffusion prevention film such as titanium nitride or molybdenum silicide acts as a barrier, preventing phosphorus in the silicon dioxide film from diffusing into the aluminum film. be done.
以下、本発明の一実施例を第１図（断面図）お
よび第２図（平面図）を用いて説明する。第１図
において、１はシリコンからなる半導体基板、２
はフイールド酸化膜、３はリンを含有する二酸化
ケイ素膜（PSG膜）、４はアルミニウム膜、５は
絶縁保護膜、６はフイールド酸化膜２とアルミニ
ウム膜４との間に設けられたポリシリコ膜、７は
同じくリン拡散防止膜であり、モリブデンシリサ
イド膜からなる。
An embodiment of the present invention will be described below with reference to FIG. 1 (cross-sectional view) and FIG. 2 (plan view). In FIG. 1, 1 is a semiconductor substrate made of silicon, 2
3 is a field oxide film, 3 is a silicon dioxide film containing phosphorus (PSG film), 4 is an aluminum film, 5 is an insulating protective film, 6 is a polysilico film provided between the field oxide film 2 and the aluminum film 4, Similarly, 7 is a phosphorus diffusion prevention film, which is made of a molybdenum silicide film.
このような構造は、次のようにして形成され
る。半導体基板上にフイールド酸化膜２を形成し
た後、選択的にポリシリコン膜６およびリン拡散
防止膜７を形成し、その上にリンを含有する二酸
化ケイ素膜３を前面に形成する。次いでエツチン
グによりリン拡散防止膜７上の二酸化ケイ素膜３
に開口を形成し、この開口内に露出した上記リン
拡散防止膜７上に、蒸着によりアルミニウム膜４
を形成する。その後、アルミニウム膜４上に開口
を有する絶縁保護膜５を形成する。 Such a structure is formed as follows. After forming a field oxide film 2 on a semiconductor substrate, a polysilicon film 6 and a phosphorus diffusion prevention film 7 are selectively formed, and a silicon dioxide film 3 containing phosphorus is formed thereon on the front surface. Next, the silicon dioxide film 3 on the phosphorus diffusion prevention film 7 is etched.
An opening is formed in the opening, and an aluminum film 4 is formed by vapor deposition on the phosphorus diffusion prevention film 7 exposed in the opening.
form. Thereafter, an insulating protective film 5 having an opening is formed on the aluminum film 4.
上記構成において、ボンデイングパツドとして
のアルミニウム膜４の下面は、リン拡散防止膜７
によつて覆われ、PSG膜３とは、外縁部におい
てわずかに接するのみで、アルミニウム膜４の下
方にはPSG膜３は存在しない。このため、PSG
膜３に含まれるリンのアルミニウム膜４中への拡
散はほとんど生じず、外縁部から拡散したとして
も、実際にボンデイングされる中央部から遠いた
め不具合を生じない。 In the above structure, the lower surface of the aluminum film 4 as a bonding pad is covered with a phosphorus diffusion prevention film 7.
The aluminum film 3 is covered with the aluminum film 4 and is only slightly in contact with the PSG film 3 at the outer edge, and the PSG film 3 does not exist below the aluminum film 4. For this reason, PSG
Phosphorus contained in the film 3 hardly diffuses into the aluminum film 4, and even if it diffuses from the outer edge, it will not cause any problems because it is far from the center where bonding is actually performed.
なお、ポリシリコン膜６は、ワイヤボンデイン
グ時に半導体基板１に過大な衝撃が加わることの
ないように、この衝撃を緩和するために設けたも
のである。このポリシリコン膜は、図では省略し
たが、他のゲート等の内部配線と同一工程で形成
することにより、特に工程数を増加させることは
ない。 It should be noted that the polysilicon film 6 is provided to reduce the impact so that an excessive impact is not applied to the semiconductor substrate 1 during wire bonding. Although this polysilicon film is omitted in the figure, it is formed in the same process as other internal interconnections such as gates, so that the number of process steps is not particularly increased.
モリブデンシリサイド膜の代りに、チタンナイ
トライド膜、あるいはこれらを積層してなる膜等
を用いても、同様に二酸化ケイ素膜３からアルミ
ニウム膜４へのリンの拡散を防止することができ
る。 Diffusion of phosphorus from the silicon dioxide film 3 to the aluminum film 4 can be similarly prevented by using a titanium nitride film or a film formed by laminating these films instead of the molybdenum silicide film.
以上のように、本発明によればボンデイングパ
ツド部の構造を、アルミニウム膜の下のチタンナ
イトライド膜またはモリブデンシリサイド膜等の
リン拡散防止膜を設け、しかもこれらアルミニウ
ム膜およびリン拡散防止膜の下にはPSG膜がな
いような構成にしたので、ボンデイング性の向上
が計れるとともに、金−アルミニウム接合部の早
期劣化を防ぐことができるため、半導体素子の長
期的信頼性を確保することが可能となる。
As described above, according to the present invention, the structure of the bonding pad portion is such that a phosphorus diffusion prevention film such as a titanium nitride film or a molybdenum silicide film is provided under the aluminum film, and that the bonding pad portion is further The structure has no PSG film underneath, which improves bonding performance and prevents early deterioration of the gold-aluminum joint, ensuring long-term reliability of the semiconductor device. becomes.
第１図は本発明の一実施例を示すボンデイング
パツド部の断面図、第２図はその平面図、第３図
は従来例を示す断面図、第４図はその平面図であ
る。
１……半導体基板、３……リンを含有する二酸
化ケイ素膜（PSG膜）、４……アルミニウム膜、
７……モリブデンシリサイド膜からなるリン拡散
防止膜。なお、図中、同一符号は同一または相当
部分を示す。
FIG. 1 is a sectional view of a bonding pad portion showing an embodiment of the present invention, FIG. 2 is a plan view thereof, FIG. 3 is a sectional view showing a conventional example, and FIG. 4 is a plan view thereof. 1...Semiconductor substrate, 3...Silicon dioxide film containing phosphorus (PSG film), 4...Aluminum film,
7...Phosphorus diffusion prevention film made of molybdenum silicide film. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ツド部に開口を有するリンを含有する二酸化ケイ
素膜と、この二酸化ケイ素膜の上記開口内に形成
されたポリシリコン膜と、このポリシリコン膜上
に形成されたリン拡散防止膜と、このリン拡散防
止膜上に形成されたボンデイングパツドのアルミ
ニウム膜とを有することを特徴とする半導体装
置。 ２ リン拡散防止膜はチタンナイトライドまたは
モリブデンシリサイドの少なくとも一方からなる
ことを特徴とする特許請求の範囲第１項記載の半
導体装置。 ３ 半導体基板上のボンデイングパツド形成部に
ポリシリコン膜を形成する工程と、このポリシリ
コン膜上にリン拡散防止膜を形成する工程と、こ
のリン拡散防止膜を覆つて半導体基板上にリンを
含有する二酸化ケイ素膜を形成する工程と、エツ
チングによりボンデイングパツド形成部の上記二
酸化ケイ素膜を除去する工程と、この除去部分に
露出した上記リン拡散防止膜上にアルミニウム膜
を形成する工程とを含むことを特徴とする半導体
装置の製造方法。[Claims] 1. A silicon dioxide film containing phosphorus having an opening in a bonding pad portion formed on a semiconductor substrate, a polysilicon film formed in the opening of the silicon dioxide film, and a polysilicon film formed in the opening of the silicon dioxide film. A semiconductor device comprising a phosphorus diffusion prevention film formed on a polysilicon film and an aluminum film of a bonding pad formed on the phosphorus diffusion prevention film. 2. The semiconductor device according to claim 1, wherein the phosphorus diffusion prevention film is made of at least one of titanium nitride and molybdenum silicide. 3. A step of forming a polysilicon film on the bonding pad forming area on the semiconductor substrate, a step of forming a phosphorus diffusion prevention film on this polysilicon film, and a step of forming a phosphorus diffusion prevention film on the semiconductor substrate by covering the phosphorus diffusion prevention film. a step of removing the silicon dioxide film in the bonding pad forming portion by etching, and a step of forming an aluminum film on the phosphorus diffusion prevention film exposed in the removed portion. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17953286A JPS6334939A (en) | 1986-07-29 | 1986-07-29 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17953286A JPS6334939A (en) | 1986-07-29 | 1986-07-29 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6334939A JPS6334939A (en) | 1988-02-15 |
| JPH0565055B2 true JPH0565055B2 (en) | 1993-09-16 |
Family
ID=16067398
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17953286A Granted JPS6334939A (en) | 1986-07-29 | 1986-07-29 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6334939A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0814018B2 (en) * | 1987-12-14 | 1996-02-14 | アルミニウム カンパニー オブ アメリカ | Heat treatment method for aluminum alloy |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58219741A (en) * | 1982-06-15 | 1983-12-21 | Nippon Gakki Seizo Kk | Semiconductor device |
-
1986
- 1986-07-29 JP JP17953286A patent/JPS6334939A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58219741A (en) * | 1982-06-15 | 1983-12-21 | Nippon Gakki Seizo Kk | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6334939A (en) | 1988-02-15 |
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