JPH033270A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the penetration of Al into a substrate from a wiring layer at the time of heat treatment, by constituting a barrier metal layer with a silicon-containing titanium layer and a high melting-point metal nitride layer. CONSTITUTION:A barrier metal layer 3 is constituted with a laminated film of a silicon-containing titanium layer 1 formed on a substrate 21 and having silicon content of 10 atomic percent or less, and a high melting-point metal nitride layer 2 formed on the silicon-containing titanium layer 1. Accordingly, even if there is a heat treatment process after the successive formation of the barrier metal layer 3 and wiring layer 26, a very small amount of Al having passed the grain boundary of the high melting-point metal nitride layer 2 penetrates into the silicon-containing titanium layer 1, reacts with Si contained in the silicon-containing titanium layer 1, and forms AlSi. So, it becomes possible to prevent the penetration of Al into the board 21 almost completely. Besides, contact resistance can be reduced as the silicon content of the silicon- containing titanium layer 1 is extremely small.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor device, and can be applied to a semiconductor device having a barrier metal layer between a Si substrate and an Al wiring layer. The present invention relates to a semiconductor device that can substantially prevent AJ from penetrating into a Si substrate from a wiring layer during heat treatment.

In recent years, as ICs have become highly integrated, high reliability has been particularly required for Al wiring.

For example, a semiconductor device is known in which an Al wiring is contacted to a Si substrate through a contact hole.
When a semiconductor device with this structure is subjected to heat treatment in a later process, Al infiltrates from the /l wiring into the Si substrate, resulting in Aj! There is a problem of so-called alloy spikes in which St alloy is formed and destroys the pn junction formed on the Si substrate.

For this reason, Al! [! There is a need for a semiconductor device having a structure that can prevent A1 from penetrating into the Si substrate from the wire.

[Conventional technology]

The prior art will be specifically explained below.

FIG. 3 is a sectional view showing the structure of an example of a conventional semiconductor device.

In this figure, 21 is a p-type substrate made of St, for example, and 22 is an n-type substrate diffusion layer, which can function as, for example, a source diffusion layer, a drain diffusion layer, or wiring. 23 is a field oxide film made of, for example, SiOz, 24 is an insulating film made of, for example, SiO□, 25 is a contact hole, 26 is a wiring layer of A1 or an alloy using A1 as a main component, and 27 is a cover film made of, for example, PSG. It is.

Note that a pn junction is formed between the substrate 21 and the substrate diffusion layer 22.

The semiconductor device shown in FIG. 3 first includes a field oxide film 23.
is formed by the well-known LOGO3 oxidation method, and after ion implantation is performed to form the substrate diffusion layer 22, a contact hole 25 is formed.
The wiring layer 2 is formed so as to be in contact with the substrate diffusion layer 22 through the contact hole 25.
6. However, the heat treatment (4) when forming the cover film 27 performed in the subsequent process
00°C or higher) or heat treatment (500°C) when bonding the device to the package, Al forming the wiring layer 26 diffuses into the base layer 21 and reacts with the Si forming the substrate 21 to form Aj'Si. An alloy (X1 section shown in FIG. 3, so-called alloy spike) is formed. When this alloy spike penetrates through the substrate diffusion layer 22 and reaches the substrate 21, the substrate 2
The pn junction formed between 1 and the substrate diffusion layer 22 is destroyed. For this reason, there is a problem in that when the pn junction is destroyed, a large amount of leakage current flows, which adversely affects IC characteristics.

As a conventional technique for solving the above problem, it is known that a barrier metal layer may be formed between the substrate 21 and the wiring layer 26. Hereinafter, this will be explained in detail with reference to the drawings.

FIG. 4 is a sectional view showing the structure of another example of a conventional semiconductor device.

In this figure, the same reference numerals as in FIG. 3 indicate the same or corresponding parts, 31 is a titanium (Ti) layer that does not contain silicon, and 32 is a titanium nitride (TiN) layer. 33
is a barrier metal layer composed of a titanium layer 31 and a titanium nitride layer 32.

In the semiconductor device shown in FIG. 4, a barrier metal layer 33 composed of a titanium layer 31 and a titanium nitride layer 32 is provided between the substrate 21 and the wiring layer 26. Barrier metal layer 33
The titanium nitride layer 32 forming the structure has a barrier property to prevent diffusion of A1 from the wiring layer 26 into the group vi21 during heat treatment. The titanium layer 31 has a lower barrier property than the titanium nitride layer 32, but if the barrier metal layer is made up of only the titanium nitride layer 32, the contact resistance will be high and the adhesion to the substrate 21 and the insulating film 24 will be poor, so the contact resistance will be lower. It is provided for the purpose of reducing the amount of heat and as an adhesive layer for bonding the substrate 21, the insulating film 24, and the titanium nitride layer 32 well.

[Problem to be solved by the invention]

The conventional semiconductor device shown in FIG. 4 has better barrier properties than the one without the barrier metal layer shown in FIG.
Although the diffusion of Al into the titanium nide layer 32 that constitutes the barrier metal layer 33 is small, even with the structure shown in FIG. 4, as shown in FIG.
A trace amount of AJ diffuses from part 2), penetrates into the substrate 21 through the titanium layer 31 having a weak barrier property, and reacts with St constituting the substrate 21 to form an AfSi alloy called an alloy spike. Along with this, such alloy spikes further progress during the same heating process, penetrate through the substrate diffusion layer 22, destroy the pn junction, and cause leakage current as in the case where no barrier metal is used. There was a problem that occurred.

In addition, as a means to improve the barrier property and solve the above problem, the titanium layer 31 is replaced with titanium silicide (Tisi2), and a stacked film of titanium silicide (TiSiz)/titanium nitride (T i N) is replaced with a barrier metal layer. It is known to be used as In this case, the penetration of l into the substrate 21 that occurs during heat treatment hardly occurs, compared to the case where a laminated film of titanium (Ti)/titanium nitride (TiN) that does not contain silicon is used as the barrier metal layer. Although the barrier properties are certainly improved, there is a problem in that the contact resistance becomes higher than when using a laminated film of titanium (Ti)/titanium nitride (TiN) that does not contain silicon.

Therefore, the present invention can almost eliminate the intrusion of A1 from the wiring layer into the substrate during heat treatment, make it difficult to cause breakdown voltage deterioration of the pn junction, and make leakage current difficult to occur, and contact resistance It is an object of the present invention to provide a semiconductor device that can realize reduction in cost.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention has a barrier metal layer between a semiconductor layer made of single crystal silicon or polysilicon and a wiring layer made of aluminum or an aluminum alloy. a silicon-containing titanium layer formed on the semiconductor layer and having a silicon content of more than 0 atomic percent and less than 10 atomic percent;
It is configured to have a high point metal layer or a high melting point metal nitride layer formed on the silicon-containing titanium layer.

[Effect]

In the present invention, as shown in FIG. 1, a barrier metal layer 3 is formed on a silicon-containing titanium layer 1 formed on a substrate 21 and having a silicon content of 2 atomic percent, and on a silicon-containing titanium layer l. It is constituted by a laminated film including a high melting point metal nitride layer 3.

Therefore, barrier metal layer 3. Even if a heat treatment step is performed after sequentially forming the wiring layers 26, a trace amount of A1 that has passed through the grain boundaries of the high-melting point metal nitride layer 2 will penetrate into the silicon-containing titanium layer 1, and the S contained in the silicon-containing titanium layer 1 will enter the silicon-containing titanium layer 1.
Since AlSi is formed by reacting with AlSi, the intrusion of Al into the substrate 21 can be almost eliminated.

Moreover, the silicon content in the silicon-containing titanium layer 1 is only 2 atomic percent, and the silicon content is only 2 atomic percent, and titanium (Ti)/titanium nitride (Ti) does not contain silicon.
Since it is possible to obtain a contact resistance that is almost the same as when the laminated film of N) is used as a barrier metal layer, it is possible to achieve a reduction in contact resistance.

[Example〕 Hereinafter, one embodiment of the present invention will be described based on the drawings.

1 and 2 are diagrams explaining one embodiment of a semiconductor device according to the present invention, FIG. 1 is a cross-sectional view showing the structure of one embodiment, and FIG. 2 is a diagram showing (a) and (b). FIG. 2 is a diagram illustrating a manufacturing method of one embodiment.

In these figures, the same reference numerals as in FIGS. 3 and 4 indicate the same or equivalent parts, 1 is a silicon-containing titanium layer with a silicon content of 2 atomic percent, 2 is a silicon-containing titanium layer, for example, T i N (WN, Z r (N etc. is also acceptable)
A high melting point metal nitride layer 3 is a barrier metal layer consisting of a silicon-containing titanium layer 1 and a high melting point metal nitride layer 2.

Next, the manufacturing method will be explained.

First, as shown in FIG. 2(a), for example, a known LOC
Field oxidation II! selectively oxidizes the P-type silicon substrate 21 using O3 oxidation method! After forming the substrate diffusion layer 22 by implanting impurity ions such as P (phosphorus) into the P-type silicon substrate 21 and performing heat treatment for activation, SiO□ is deposited on the entire surface by, for example, the CVD method. An insulating film 24 made of SiO□ is deposited. Then,
For example, RIE using CFa (carbon tetrafluoride) gas
(Reactive ion etching)
4 is selectively etched to form a contact hole 25, the natural oxide film formed on the substrate diffusion layer 22 within the contact hole 25 is removed by wet treatment using, for example, a hydrofluoric acid solution.

Next, as shown in FIG. 2(b), contact is made with the substrate diffusion layer 22 through the contact hole 25 by sputtering, for example, so that the silicon content is, for example, 2 atomic percent, and the film thickness is reduced. For example, after forming a silicon-containing titanium layer 1 of 200 nm thick, and forming a refractory metal nitride layer 2 made of TiN with a film thickness of 1500 nm on the silicon-containing titanium layer 1, for example, by sputtering, for example, A wiring layer 26 made of Al and having a film thickness of 111 m, for example, is formed on the ride layer 2 made of high melting point metal night.

After sequentially patterning the wiring layer 26, high melting point metal nitride layer 2, and silicon-containing titanium layer 1 by, for example, the RIE method, a cover film having a thickness of, for example, 0.8 μm is formed to cover the wiring layer 26 by, for example, the CVD method. By forming 27, a semiconductor device having a structure as shown in FIG. 1 is completed.

That is, in the above embodiment, as shown in FIG. 1, the barrier metal layer 3 is formed on the silicon-containing titanium layer 1 having a silicon content of 2 atomic percent and the silicon-containing titanium layer 1 formed on the substrate 21. Since the wiring layer 26 made of Af generated during heat treatment is made of a high melting point metal nitride layer 3, the wiring layer 26 made of silicon is removed from the substrate 2 made of silicon.
Figure 4 shows the penetration of AJ into the conventional barrier metal layer 3 made of titanium Jti31 that does not contain St.
pn
It is possible to make it difficult to cause breakdown voltage deterioration of the junction and to make it difficult to generate leakage current, and it is possible to make it difficult to cause leakage current.
It is possible to realize a reduction in contact resistance compared to the barrier metal layer composed of iz).

Here, from the AJ wiring layer 26 generated during heat treatment to the substrate 2
The infiltration of AJ into 1 can be almost eliminated by
Even if a small amount of A1 that has passed through the grain boundaries of the high melting point metal nitride layer 2 penetrates into the silicon-containing titanium layer 1, it reacts with the St contained in the silicon-containing titanium layer 1 and is alloyed with AJ2-Ti-3i. This is because it becomes .

In addition, contact resistance can be reduced because the silicon-containing titanium layer contains only 2 atomic percent silicon, making it possible to obtain a contact resistance that is almost the same as that of a titanium layer that does not contain silicon. It is from.

In the above embodiment, the high melting point metal nitride layer 2 made of TtN, for example, is used to form the barrier metal layer 3.
Although the present invention is not limited to this example, a high melting point metal layer such as W may be used in place of the high melting point metal nitride layer 2.

Further, in the above embodiment, the case where the silicon-containing titanium layer 1 containing 2 atomic percent of St is used to constitute the barrier metal layer 3 has been described, but the present invention is not limited to this. It is only necessary to use a silicon-containing titanium layer whose content exceeds O atomic percent and is not more than 10 atomic percent.

In a preferred embodiment from the viewpoint of barrier properties and contact resistance, the silicon content is 1 or more and 3 atomic percent or less. Note that the atomic percentage is IO
The following values are used for conventional Ti5j2 when it is larger than 10.
This is because the contact resistance increases as in the case of , which is undesirable.

Furthermore, the above embodiment has a single crystal silicon substrate 21 and a wiring layer 2.
Although the case where the barrier metal layer 3 is provided between the semiconductor layer 26 and the wiring layer 26 has been described, the present invention is not limited to this. It can also be applied to a case where the barrier metal layer 3 is provided.

〔Effect of the invention〕

According to the present invention, during heat treatment, it is possible to almost eliminate the intrusion of A1 from the wiring layer into the substrate, to make it difficult to cause breakdown voltage deterioration of the pn junction and to make it difficult to generate leakage current, and to make it difficult to cause leakage current. This has the effect that resistance can be reduced.

Fig. 2 is a diagram explaining the manufacturing method of one embodiment, Fig. 3 is a sectional view showing the structure of an example of the conventional example, Fig. 4 is a sectional view showing the structure of another example of the conventional example, and Fig. 5 FIG. 2 is a diagram illustrating the problems of the conventional example.

1... Silicon-containing titanium layer, 2...
High melting point metal nitride layer, 3... Barrier metal layer, 21... Substrate, 26... Wiring layer.

[Brief explanation of drawings]

1 and 2 are diagrams explaining one embodiment of a semiconductor device according to the present invention, and FIG. 1 is a cross-sectional view showing the structure of one embodiment, and FIG.

Claims (1)

[Claims] A semiconductor device having a barrier metal layer between a semiconductor layer made of single crystal silicon or polysilicon and a wiring layer made of aluminum or an aluminum-based alloy, wherein the barrier metal layer is formed on the semiconductor layer. formed, the silicon content exceeds 0 atomic percent, and 10
1. A semiconductor device comprising a silicon-containing titanium layer having an atomic percentage or less, and a high-melting point metal layer or a high-melting point metal nitride layer formed on the silicon-containing titanium layer.