JPH0316145A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0316145A
JPH0316145A JP1214852A JP21485289A JPH0316145A JP H0316145 A JPH0316145 A JP H0316145A JP 1214852 A JP1214852 A JP 1214852A JP 21485289 A JP21485289 A JP 21485289A JP H0316145 A JPH0316145 A JP H0316145A
Authority
JP
Japan
Prior art keywords
layer
barrier metal
oxide film
forming
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1214852A
Other languages
Japanese (ja)
Inventor
Kazuhisa Ikenoue
池ノ上 和久
Keiichi Abe
安部 啓一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP1214852A priority Critical patent/JPH0316145A/en
Publication of JPH0316145A publication Critical patent/JPH0316145A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05084Four-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To enhance a bonding strength by a method wherein a polysilicon layer or a polycide layer is formed between a barrier metal layer and an insulating oxide film. CONSTITUTION:A silicon oxide film 106a and a BPSG film 107a which have been patterned are formed to form a contact hole and an opening part in a bonding pad part. A barrier metal layer 108 is formed; the barrier metal layer is formed as a two-layer structure 108, 1082 of Ti/TiN. A formed metal electrode layer 109 and the barrier metal layer 108 are etched continuously to form a prescribed interconnection pattern. In addition, a passivation film 110 is formed in order to protect the surface. A hole for bonding use is made in a pad, and a wire 111 is bonded. Consequently, it is possible to obtain a bonding pad structure where a polycide layer 104a has been formed between the barrier metal layer 108 and an insulating oxide film 102. Thereby, it is possible to prevent a bonding pad from being exfoliated.

Description

【発明の詳細な説明】 [発明の目的コ (産業上の利用分野) 本発明はボンディングパッドの形成方法に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention (Field of Industrial Application) The present invention relates to a method of forming a bonding pad.

(従来の技術) ボンディングパッドは通常半導体装置の配線と同一の材
質、構造をもつ。St基板上にA4を用いて電極配線を
形成した場合、素子製造工程の温度上昇により、AJと
基板のSiとが相互拡散し、A℃が拡散層を突抜けてp
n接合を破壊するという問題があった。このAIの突抜
けを防止する手段としてAJ配t@層とSi基板の間に
バリアメタル層を介在させる方法を用いている。
(Prior Art) Bonding pads usually have the same material and structure as the wiring of semiconductor devices. When electrode wiring is formed using A4 on a St substrate, due to the temperature rise in the element manufacturing process, AJ and Si of the substrate interdiffuse, and A℃ penetrates the diffusion layer and P
There was a problem of destroying the n-junction. As a means to prevent this AI from breaking through, a method is used in which a barrier metal layer is interposed between the AJ layer and the Si substrate.

以下図面を参照してボンディングパッドの形成方法を説
明する。
A method for forming bonding pads will be described below with reference to the drawings.

第5図(a)〜(e)は従来技術によるボンディングパ
ッドの製造工程を説明する断面図である。
FIGS. 5(a) to 5(e) are cross-sectional views illustrating the manufacturing process of a bonding pad according to the prior art.

第5図(a)に示すように、P型シリコン基板(501
)の表面に選択酸化法により、フィールド酸化膜(50
2)を形成する。
As shown in FIG. 5(a), a P-type silicon substrate (501
) on the surface of the field oxide film (50 mm) by selective oxidation method.
2) Form.

続いて第5図(b)に示すように、同基板(501)の
素子領域に、ゲート酸化膜(503) 、ゲート電極(
504)を形成し、その後不純物のイオン注入によりn
型拡散層(505)を形成する。
Next, as shown in FIG. 5(b), a gate oxide film (503) and a gate electrode (
504) and then impurity ion implantation to form n
A type diffusion layer (505) is formed.

さらに第5図(e)に示すように、絶縁酸化膜(50B
)を形成し、コンタクトホールを形成する。
Furthermore, as shown in FIG. 5(e), an insulating oxide film (50B
) and form a contact hole.

第5図(d)に示すようにバリアメタル層(507)4
を形成する。バリアメタル層はT i / T i N
の2層構造となっており、まず、スバッタ法によりTi
層(5071 )を200人程度、その後TiN層(5
072 )を700人程度形成する。さらにN2雰囲気
中で約600℃のアニールを行なう。その後金a電極層
(508)としてA4層を形成する。金属電極層(50
8)とバリアメタル層(507)を連続的にエッチング
して所定の配線パターンを形成する。
As shown in FIG. 5(d), barrier metal layer (507) 4
form. The barrier metal layer is T i / T i N
It has a two-layer structure, and first, Ti is deposited using the sputtering method.
layer (5071) for about 200 people, then TiN layer (5
072) with approximately 700 people. Furthermore, annealing is performed at about 600° C. in an N2 atmosphere. Thereafter, an A4 layer is formed as a gold a electrode layer (508). Metal electrode layer (50
8) and the barrier metal layer (507) are successively etched to form a predetermined wiring pattern.

第5図(e)に示すように、パッシベーション膜(50
9)を形成し、ボンディングのための孔をパッドに開口
する。最後にこのパッドにワイヤー(510)をボンデ
ィングする。
As shown in FIG. 5(e), a passivation film (50
9), and holes for bonding are opened in the pads. Finally, a wire (510) is bonded to this pad.

このような形成方法によるボンディングパッド構造では
バリアメタル層により、コンタクト部分の、八4の突抜
けを防止することができる。
In the bonding pad structure formed by such a formation method, the barrier metal layer can prevent the contact portion from penetrating through.

しかしながら、バリアメタル層を用いたボンディングバ
ッドの場合ボンディング強度(引張り強度)が大幅に低
下し、ボンディングバッドがはがれる等の問題があった
。これはTiの強い還元性によるもので、従来のように
、絶縁酸化膜S i O 2 (5H)上にバリアメタ
ル層T i / T i N層(507)を形成すると
S i O 2 / T i界面では反応が起こり、T
i02等が生成され膜質の良くないもろい膜が形成され
るため、絶縁酸化膜(50B)とバリアメタル層(50
7)の機械的接合力(強度)は著しく低下し、ボンディ
ングパッドの剥離をまねいていた。
However, in the case of a bonding pad using a barrier metal layer, the bonding strength (tensile strength) is significantly reduced, and there are problems such as the bonding pad peeling off. This is due to the strong reducing property of Ti, and when a barrier metal layer Ti/TiN layer (507) is formed on an insulating oxide film SiO2 (5H) as in the conventional case, SiO2/T A reaction occurs at the i interface, and T
Since i02 etc. are generated and a brittle film with poor film quality is formed, the insulating oxide film (50B) and barrier metal layer (50B) are
The mechanical bonding force (strength) of 7) was significantly reduced, leading to peeling of the bonding pad.

ボンディングパッド部にバリアメタルを用いなければよ
いがボンディングバッド部のみにバリアメタルを形成し
ない製造工程は工程数が増えコストアップとなる。
Although it is possible not to use the barrier metal in the bonding pad portion, the manufacturing process in which the barrier metal is not formed only in the bonding pad portion increases the number of steps and costs.

(発明が解決しようとする課題) 上記のような従来の半導体装置の製造方法によるボンデ
ィングパッド構造では、A℃配線の際に形威されるバリ
アメタル層により、ボンディング強度が大幅に低下し、
ボンディングの信頼性が低下するという問題があった。
(Problems to be Solved by the Invention) In the bonding pad structure according to the conventional semiconductor device manufacturing method as described above, the bonding strength is significantly reduced due to the barrier metal layer formed during A degree Celsius wiring.
There was a problem that the reliability of bonding decreased.

本発明は上述した問題を考慮してなされたものでその目
的はバリアメタル層を用いたボンディングパッドのボン
ディング強度を向上させる半導体装置の製造方法を提供
することにある。
The present invention has been made in consideration of the above-mentioned problems, and an object thereof is to provide a method for manufacturing a semiconductor device that improves the bonding strength of a bonding pad using a barrier metal layer.

[発明の構成] (課題を解決するための手段) 上記目的を達戊するために本発明は、請求項第1記載の
半導体装置の製造方法においては、半導体基板上の絶縁
酸化膜上にポリシリコン層及び高融点金属シリサイド層
のうち少なくともどちらか一方より構成される層を形成
する工程と、この層上にチタン層とその上部のチタンナ
イトライド層とから成る積層及びチタン−タングステン
合金層のうちのどちらか一方より構成されるバリアメタ
ル層を形成する工程と、 このバリアメタル層上にアルミニウム及びアルミニウム
合金のうちどちらか一方より構成される金属電極層を形
成する工程と、 この金属電極層にワイヤーをボンディングする工程と、
を有する。
[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device according to claim 1, in which polyamide is formed on an insulating oxide film on a semiconductor substrate. A step of forming a layer consisting of at least one of a silicon layer and a refractory metal silicide layer, and a lamination of a titanium layer and a titanium nitride layer thereon on this layer, and a titanium-tungsten alloy layer. a step of forming a barrier metal layer made of either one of aluminum or an aluminum alloy; a step of forming a metal electrode layer made of either aluminum or an aluminum alloy on this barrier metal layer; and a step of forming a metal electrode layer made of either aluminum or an aluminum alloy. A process of bonding the wire to the
has.

又、本発明は、請求項第2記載の半導体装置の製造方法
においては、 半導体基板上の絶縁酸化膜上にシリケイトガラス膜を形
成して平坦化する工程と、 このシリケイトガラス膜上にポリシリコン層及び高融点
金属シリサイド層のうち少なくともどちらか一方より構
成される層を形成する工程と、この層上にチタン層と、
その上部のチタンナイトライド層とから成る積層及びチ
タン−タングステン合金層のうちのどちらか一方より構
成されるバリアメタル層を形成する工程と、 このバリアメタル層上にアルミニウム及びアルミニウム
合金のうちどちらか一方より構或される金属電極層を形
成する工程と、 この金属電極層にワイヤーをボンディングする工程とを
有する。
The present invention also provides a method for manufacturing a semiconductor device according to claim 2, which includes the steps of: forming and planarizing a silicate glass film on an insulating oxide film on a semiconductor substrate; and depositing polysilicon on the silicate glass film. a step of forming a layer consisting of at least one of a layer and a high melting point metal silicide layer, a titanium layer on this layer,
A step of forming a barrier metal layer consisting of either a laminated layer consisting of a titanium nitride layer on top of the layer or a titanium-tungsten alloy layer, and forming either aluminum or an aluminum alloy on the barrier metal layer. The method includes a step of forming a metal electrode layer composed of one side, and a step of bonding a wire to the metal electrode layer.

(作 用) 本発明の半導体装置の製造方法におけるボンディングパ
ッドの構造では、バリアメタル層及び絶縁酸化膜との間
に、ポリシリコン層あるいはポリサイド層を設けること
によりバリアメタル層とも絶縁酸化膜とも機械的に良好
な接合が得られボンディング強度が向上される。
(Function) In the structure of the bonding pad in the semiconductor device manufacturing method of the present invention, by providing a polysilicon layer or a polycide layer between the barrier metal layer and the insulating oxide film, both the barrier metal layer and the insulating oxide film can be mechanically bonded. This results in better bonding and improved bonding strength.

(実施例) 以下、図面を参照して本発明の実施例を詳細に説明する
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

第1図(a)〜(e)は本発明の第1の実施例の半導体
装置におけるボンディングパッド部のu H工程を説明
する断面図である。
FIGS. 1A to 1E are cross-sectional views illustrating the uH process of a bonding pad portion in a semiconductor device according to a first embodiment of the present invention.

第1図(a)に示すように、P型シリコン基板(101
)の表面に選択酸化法によりフィールド酸化膜(102
)を形成する。
As shown in FIG. 1(a), a P-type silicon substrate (101
) on the surface of the field oxide film (102
) to form.

続いて第1図(b)に示すように、同基板(101)の
素子領域に熱酸化によりシリコン酸化膜(3)を例えば
150入程度形威しさらに全面にまず厚さ約2000λ
程度のポリシリコン層(104r )を形成した後、モ
リブデンシリサイド層(1042 )を3000人程度
形威し、ポリサイド層(104)が形成される。
Next, as shown in FIG. 1(b), a silicon oxide film (3) of about 150 layers, for example, is formed by thermal oxidation on the element area of the substrate (101), and then a silicon oxide film (3) of about 2000 λ thickness is formed on the entire surface.
After forming a polysilicon layer (104r) of about 3,000 yen, a molybdenum silicide layer (1042) is formed by about 3,000 people to form a polycide layer (104).

第1図(C)に示すように、写真蝕刻法によりパターニ
ングしてゲート酸化膜(103a)及びゲート電極(1
04a)を形成し、同時にフィールド酸化膜(102)
上のボンディングパッド予定部にポリサイド層(104
b)を形成する。その後不純物のイオン注入によりソー
ス・ドレイン領域であるn型拡散層(105)を形成し
、CVD法により層間絶縁膜となるシリコン酸化膜(1
06)を形成する。さらに全面にBPSG膜(7)を形
成しりフローを行う。
As shown in FIG. 1(C), a gate oxide film (103a) and a gate electrode (103a) are patterned by photolithography.
04a) and at the same time form a field oxide film (102).
A polycide layer (104
b) form. Thereafter, an n-type diffusion layer (105) which is a source/drain region is formed by ion implantation of impurities, and a silicon oxide film (105) which becomes an interlayer insulating film is formed by a CVD method.
06) is formed. Furthermore, a BPSG film (7) is formed on the entire surface and a flow process is performed.

続いて第1図(d)に示すように、レジストをマスクに
してパターニングされたシリコン酸化膜(106a)及
びBPSG膜(107a)を形成することによりコンタ
クトホール及びボンディングパッド部の開口部を形成し
ている。
Subsequently, as shown in FIG. 1(d), a patterned silicon oxide film (106a) and a BPSG film (107a) are formed using a resist as a mask to form contact holes and openings for bonding pads. ing.

次に、第1図(e)に示すように、バリアメタル層(8
)を形成する。バリアメタル層はTi/TiNの2層構
造になっている。まず、スバッタ法によりTi層(10
8t )を200人程度形成し連続して化成スバッタ法
によりTiN層(1082 ) ヲ700λ程度形成す
る。さらにN2雰囲気中で約600℃のアニールを行な
う。この時コンタクト部のTi層(108. )は基板
S i (101)と反応してTiSi2となりコンタ
クトを取ることができる。
Next, as shown in FIG. 1(e), a barrier metal layer (8
) to form. The barrier metal layer has a two-layer structure of Ti/TiN. First, a Ti layer (10
About 200 people formed a TiN layer (1082) with a thickness of about 700λ using a chemical sputtering method. Furthermore, annealing is performed at about 600° C. in an N2 atmosphere. At this time, the Ti layer (108.) in the contact portion reacts with the substrate S i (101) and becomes TiSi2, allowing contact to be made.

その後金属電極層(109)としてA42層(又はAf
2合金Aj2−S i−Cu等)を8000人程度形成
する。金属電8iI層(109)とバリアメタル層(1
08)を連続的にエッチングして所定の配線パターンを
形成する。
Thereafter, the metal electrode layer (109) is an A42 layer (or Af
2 alloy Aj2-S i-Cu, etc.) will be formed by approximately 8,000 people. Metal conductor 8iI layer (109) and barrier metal layer (1
08) is continuously etched to form a predetermined wiring pattern.

さらに表面保護の目的でバッシベーション膜(110)
を形成しボンディングのための孔をパッドに開口する。
Furthermore, for the purpose of surface protection, a bashivation film (110)
and holes for bonding are opened in the pads.

最後にこのパッドにワイヤー(111)をボンディング
する。これによりバリアメタル層(10g>及び絶縁酸
化膜(ID2)との間にポリサイド層(4b)が設けら
れたボンディングバッド構造を有する半導体装置が完成
する。
Finally, a wire (111) is bonded to this pad. This completes a semiconductor device having a bonding pad structure in which the polycide layer (4b) is provided between the barrier metal layer (10g>) and the insulating oxide film (ID2).

この実施例によるボンディングパッドのボンディング強
度を調べるためにワイヤボンディングを行ないワイヤの
引張試験による引張強度とビールテストによるパッドは
がれ率の測定を行なった。
In order to examine the bonding strength of the bonding pad according to this example, wire bonding was performed, and the tensile strength was measured by a wire tensile test and the pad peeling rate was measured by a beer test.

その結果を従来技術の測定結果とともに第4図の表に示
す。
The results are shown in the table of FIG. 4 together with the measurement results of the prior art.

ワイヤの引張試験は、ワイヤのチップ部と外囲器部の中
心部分を鉛直方向に引張り上げる試験で、第3図に示す
結果はワイヤを20本測定した時の平均値である。従来
例ではIgf以下、実施例では7gfとなり、従来例よ
りも強度が増したことがわかる。また破断モードも従来
例の場合はすべてバリアメタル層と酸化膜との界面での
はがれによるのに対し実施例の場合はすべてチップ側ネ
ック部のワイヤの切断によるものであった。
The wire tensile test is a test in which the tip part and the central part of the envelope part of the wire are pulled up in the vertical direction, and the results shown in FIG. 3 are the average values when 20 wires were measured. In the conventional example, the strength was less than Igf, and in the example, it was 7 gf, indicating that the strength was increased compared to the conventional example. Furthermore, in the case of the conventional example, the failure mode was all due to peeling off at the interface between the barrier metal layer and the oxide film, whereas in the case of the example, it was all due to cutting of the wire at the neck portion on the chip side.

さらに、ワイヤをチップのパッドにのみボンディングし
て、ピンセットでワイヤをつまみ鉛直方向に引張り上げ
るビールテストの結果は、従来例の場合、バリアメタル
層と酸化膜との界面でのはがれ率を示し実施例の場合は
、バリアメタル層とポリサイド層との界面でのはがれ率
を示している。
Furthermore, the results of the Beer test, in which the wire is bonded only to the pad of the chip, the wire is grabbed with tweezers and pulled vertically, show the peeling rate at the interface between the barrier metal layer and the oxide film in the case of the conventional example. In the example, the peeling rate at the interface between the barrier metal layer and the polycide layer is shown.

ここで、はがれ率とは測定した全ワイヤ数を分母に、そ
の内はがれたワイヤ数を分子にとったものである。実施
例の場合のはがれ率はOであった。
Here, the peeling rate is calculated by taking the total number of measured wires as the denominator and the number of peeled wires as the numerator. The peeling rate in the example was O.

以上のことより、実施例のボンディングパッド構造によ
ればバリアメタル層と絶縁酸化膜の間にポリサイド層を
形成することによりバリアメタル層に対しても絶縁酸化
膜に対しても機械的に良好な接合が得られボンディング
強度を増すことがわかる。これによりボンディングの信
頼性が高まり、半導体装置の信頼性を高めることができ
る。また、このようなボンディングパッド構造を得るた
めに特別な工程を追加しなくても半導体素子の構成材料
となるポリシリコン/モリブデンシリサイド(ポリサイ
ド)層を用いれば良い。
From the above, according to the bonding pad structure of the example, by forming a polycide layer between the barrier metal layer and the insulating oxide film, it is possible to create a mechanically good structure for both the barrier metal layer and the insulating oxide film. It can be seen that a bond is obtained and the bonding strength is increased. This increases the reliability of bonding and improves the reliability of the semiconductor device. Further, in order to obtain such a bonding pad structure, a polysilicon/molybdenum silicide (polycide) layer, which is a constituent material of a semiconductor element, can be used without adding any special process.

このポリサイド層は、従来ボンディングパッド下の部分
は取り除いていたがこれを残すように加工すれば良くコ
ストは要らない。また、ポリサイド層の代わりにポリシ
リコン層のみを用いた場合でも同様の効果を得るこ=と
ができる。
Conventionally, the polycide layer was removed from the part under the bonding pad, but it can be processed to leave this part, and no cost is required. Further, similar effects can be obtained even when only a polysilicon layer is used instead of a polycide layer.

また、第2図(a)〜(f’)は本発明第2の実施例の
半導体装置におけるボンディングパッド部の製造工程を
説明する断面図である。
Further, FIGS. 2(a) to 2(f') are cross-sectional views illustrating the manufacturing process of a bonding pad portion in a semiconductor device according to a second embodiment of the present invention.

第2図(a)に示すように、第1の実施例同様P型シリ
コン基板(201)の表面にフィールド酸化膜(202
)を形成し、ゲート酸化膜(203)及びポリシリコン
層(2041) /モリブデンシリサイド層(2042
 )からなるゲート電極(204)を形成し、その後n
型拡散層(205)を形成する。
As shown in FIG. 2(a), as in the first embodiment, a field oxide film (202) is formed on the surface of a P-type silicon substrate (201).
), and gate oxide film (203) and polysilicon layer (2041)/molybdenum silicide layer (2042) are formed.
), and then a gate electrode (204) consisting of n
A type diffusion layer (205) is formed.

?$2図(b)に示すように、CVD法によりシリコン
酸化膜(206)を形成し、さらに表面を平坦化するた
めに全面にBPSG膜.(207)を形成する。
? $2 As shown in Figure (b), a silicon oxide film (206) is formed by the CVD method, and a BPSG film (206) is then formed on the entire surface to flatten the surface. (207) is formed.

この層間絶縁膜BPSG膜(207)上にポリシリコン
層(20g)をL P C V D (Low Pre
ssure CVD)法により例えば400人程度形成
する。
A polysilicon layer (20g) is formed on this interlayer insulating film BPSG film (207) using L P C V D (Low Pre
For example, about 400 people are formed using the CVD method.

第2図(C)に示すように、ポリシリコン層(20g)
上にレジスト(209)でコンタクトのパターンを形成
し、このレジスト(209)をマスクにCDHにより、
ポリシリコン膜(2(lI!)をエッチングし、続いて
BPSG膜(207)を一部、等方的にエッチングする
。さらにRIEでエッチングされたBPSC;膜(20
7a)、シリコン酸化膜(208a)によりコンタクト
ホール(210)・を形成する。
As shown in Figure 2(C), a polysilicon layer (20g)
A contact pattern is formed on top using a resist (209), and using this resist (209) as a mask, a contact pattern is formed using CDH.
The polysilicon film (2 (lI!) is etched, and then the BPSG film (207) is partially isotropically etched.The BPSC film (207) etched by RIE is further etched.
7a) A contact hole (210) is formed using a silicon oxide film (208a).

第2図(d)に示すように、レジスト(209)を剥離
した後、スパッタ法によりTi層(211)を200人
程度形成し、連続して化成スバッタ法によりTiN層(
212)を700人程度形成する。
As shown in FIG. 2(d), after peeling off the resist (209), about 200 Ti layers (211) are formed by sputtering, followed by a TiN layer (211) by chemical sputtering.
212) with approximately 700 people.

第2図(e)に示すように、窒素雰囲気中で600℃,
30分のアニールを行なう。この時コンタクト部のTi
層(211)は基板のStと反応しTiSi2となりコ
ンタクトを取ることができる。層間絶縁gBPsG膜(
207a)上のポリシリコン層(20g)はTi層(2
11)と反応し、TiSi2層(213)となる。
As shown in Figure 2(e), at 600°C in a nitrogen atmosphere,
Perform annealing for 30 minutes. At this time, the Ti of the contact part
The layer (211) reacts with the St of the substrate to form TiSi2 and can make contact. Interlayer insulation gBPsG film (
The polysilicon layer (20g) on top of the Ti layer (207a)
11) to form a TiSi2 layer (213).

次にA42合金(AJ−S i, AJ−S i−Cu
等) (214)をスバッタ法により8000人程度形
成する。
Next, A42 alloy (AJ-S i, AJ-S i-Cu
etc.) Form approximately 8,000 people (214) using the scattering method.

第2図(f)に示すように、AI2合金(214)上に
レジストで配線パターンを形成しRIE法でA4合金層
(214) 、T i N層(212)及びTiSi2
(213)積層膜をエッチングし、配線を形成する。
As shown in FIG. 2(f), a wiring pattern is formed using resist on the AI2 alloy (214), and then the A4 alloy layer (214), the TiN layer (212) and the TiSi2
(213) Etch the laminated film to form wiring.

このAJ2配線(215)上にパッシベーション膜とし
てPSG膜(21B)をCVD法で形成し最後にボンデ
ィングのための孔をパッドに開口する。このパッドにワ
イヤー(217)をボンディングする。
A PSG film (21B) is formed as a passivation film on this AJ2 wiring (215) by the CVD method, and finally a hole for bonding is opened in the pad. A wire (217) is bonded to this pad.

このような実施例の半導体装置の製造方法によるボンデ
ィングパッド構造では、ボンディングパッド部は、あら
かじめ形成されたポリシリコン層(208)と、バリア
メタル層であるTillとが反応し、T L S i 
2 (21B)となるため、ボンディング強度は増し、
ボンディングの信頼性が高まり、半導体装置の信頼性を
高めることができる。また、ボンディングバッドと基板
間には、従来どおりフィールド酸化膜と層間絶縁膜があ
りパッドの容量(入力容ffi)増加を防ぐことができ
、アブリケーション上の問題は起こらない。さらに、ボ
ンディングパッドは平坦化されたBPSG膜(207)
上に形成されているため、外部より電圧を印加した際、
電界集中などを防ぐことができ、より信頼性の高い半導
体装置を得ることができる。
In the bonding pad structure according to the semiconductor device manufacturing method of the embodiment, in the bonding pad portion, the polysilicon layer (208) formed in advance and Till, which is the barrier metal layer, react, and T L Si
2 (21B), the bonding strength increases,
The reliability of bonding is improved, and the reliability of the semiconductor device can be improved. Furthermore, since there is a field oxide film and an interlayer insulating film between the bonding pad and the substrate as in the past, it is possible to prevent an increase in the capacitance of the pad (input capacitance ffi), and no ablation problems occur. Furthermore, the bonding pad is a flattened BPSG film (207).
Because it is formed on the top, when voltage is applied from the outside,
Electric field concentration can be prevented, and a more reliable semiconductor device can be obtained.

尚、上記第2の実施例では、層間絶縁膜であるB P 
S G Ill! (207a)上に形成されたポリシ
リコン層(208)がその後の工程でTi層(211)
と反応し、TiSi2層(213)となっているが、第
2の実施例同様の半導体装置の製造方法において、形成
するポリシリコン層及びTi層の膜厚及び反応の状態に
より、ボンディングパッド部の構造が異なる場合がある
。それぞれのボンディングパッド部の構造断面図を第3
図(a)〜(C)に示す。
In the second embodiment, the interlayer insulating film B P
S G Ill! The polysilicon layer (208) formed on (207a) becomes a Ti layer (211) in a subsequent process.
However, in a method for manufacturing a semiconductor device similar to the second embodiment, the thickness of the bonding pad portion may vary depending on the thickness of the polysilicon layer and Ti layer to be formed and the state of the reaction. The structure may be different. The structural cross-sectional view of each bonding pad part is shown in the third figure.
Shown in Figures (a) to (C).

第3図(a)に示すように、基板(301)上にフィー
ルド酸化膜(302)が形成され、この上部にシリコン
酸化膜(303),BPSG膜(304) ,ポリシリ
コン層(305),TiSi2層(30B) , T 
i層(307) , T i N層(308),AJ2
層(309)が積層されており、これらをとり囲むよう
にパッシベーション膜(310)が形成され、AJ2層
(309)の上にボンディングワイヤー(311)が接
続された構造となる。
As shown in FIG. 3(a), a field oxide film (302) is formed on a substrate (301), and on top of this, a silicon oxide film (303), a BPSG film (304), a polysilicon layer (305), TiSi2 layer (30B), T
i layer (307), T i N layer (308), AJ2
The structure is such that layers (309) are stacked, a passivation film (310) is formed to surround these layers, and a bonding wire (311) is connected on top of the AJ2 layer (309).

また、第3図(b)に示すように、基板(301)上に
フィールド酸化膜(302)シリコン酸化膜(303)
 ,BPSG膜(3G4),TiSi2層(30B) 
, T i層(307) , T i N層(308)
 . A42層(309)が積層されており、これらを
とり囲むようにパッシベーションa (31G)が形成
され、AI2層(30’9)の上にボンディングワイヤ
ー(311)が接続された構造となる。
Further, as shown in FIG. 3(b), a field oxide film (302) and a silicon oxide film (303) are formed on the substrate (301).
, BPSG film (3G4), TiSi2 layer (30B)
, T i layer (307), T i N layer (308)
.. A42 layers (309) are stacked, passivation a (31G) is formed to surround them, and a bonding wire (311) is connected on top of the AI2 layer (30'9).

さらに、第3図(C)に示すように基板(301)上に
フィールド酸化膜(302) , シリコン酸化膜(3
03) B P S G膜(304) ,ポリシリコン
層(305) ,TiSi2層(30B) , T i
 N層(30g) , A J層(309)が積層され
ており、これらをとり囲むようにパッシベーション膜(
310)が形成されこのA4層(309)の上にボンデ
ィングワイヤー(Clll)が接続された構造となる。
Furthermore, as shown in FIG. 3(C), a field oxide film (302) and a silicon oxide film (3) are formed on the substrate (301).
03) BPSG film (304), polysilicon layer (305), TiSi2 layer (30B), Ti
N layer (30g) and AJ layer (309) are stacked, and a passivation film (
310) is formed, and a bonding wire (Cllll) is connected on top of this A4 layer (309).

以上のような構造においても、第2の実施例同様の効果
を得ることは言うまでもない。
It goes without saying that the above structure also provides the same effects as the second embodiment.

尚、本発明は、上記実施例に限られるものではない。例
えば、バリアメタル層としてTi/TiN層の代わりに
Ti−W合金を用いても上記実施例と同様の効果を得る
ことができる。
Note that the present invention is not limited to the above embodiments. For example, the same effect as in the above embodiment can be obtained by using a Ti--W alloy instead of the Ti/TiN layer as the barrier metal layer.

[発明の効果] 以上詳述したように本発明のボンディングパッド構造に
よれば、ボンディングパッドのはがれを防ぎ、信頼性の
高い半導体装置を得ることができる。
[Effects of the Invention] As detailed above, according to the bonding pad structure of the present invention, peeling of the bonding pad can be prevented and a highly reliable semiconductor device can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(e)は、本発明の第1の実施例による
半導体装置の製造工程を説明する断面図、第2図(a)
〜(r)は、本発明の第2の実施例による半導体装置の
製造工程を説明する断面図、第3図(a)〜(C)は、
本発明の実施例によるボンディングパッド部の構造を示
す断面図、第4図は、本発明の第1の実施例及び従来例
によるワイヤーの引張強度とパッドはがれ率を示す表、 第5図(a)〜(e)は、従来の半導体装置の製造工程
を説明する断面図である。 101,20L.3OL,501・・・P型シリコン基
板、102,202,302.502・・・フィールド
酸化膜、104. ,208.305・・・ポリシリコ
ン層、1042・・・モリブデンシリサイド層、104
,LO4b・・・ポリサイド層、10B.L06a,2
06,208a,303・・・シリコン酸化膜、107
.107a.207.207a,304・B P S 
G膜、10B1 ,211,307.5071・・・T
i層、1082 ,212,308.5072・・・T
iN層、213.30B・・・T i S i 2層、
109,215,309,508・・・金属電極層(A
J又は、AJ合金)、 110,218,310.509・・・バッシベーショ
ン膜、
FIGS. 1(a) to 1(e) are cross-sectional views illustrating the manufacturing process of a semiconductor device according to a first embodiment of the present invention, and FIG. 2(a) is
~(r) are cross-sectional views explaining the manufacturing process of a semiconductor device according to the second embodiment of the present invention, and FIGS. 3(a) to (C) are
FIG. 4 is a sectional view showing the structure of the bonding pad portion according to the embodiment of the present invention, and FIG. ) to (e) are cross-sectional views illustrating the manufacturing process of a conventional semiconductor device. 101,20L. 3OL, 501... P-type silicon substrate, 102, 202, 302.502... Field oxide film, 104. , 208.305... Polysilicon layer, 1042... Molybdenum silicide layer, 104
, LO4b...polycide layer, 10B. L06a,2
06, 208a, 303... silicon oxide film, 107
.. 107a. 207.207a, 304・B P S
G film, 10B1, 211, 307.5071...T
i layer, 1082, 212, 308.5072...T
iN layer, 213.30B...T i S i 2 layer,
109,215,309,508...metal electrode layer (A
J or AJ alloy), 110,218,310.509...basivation film,

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上の、絶縁酸化膜上にポリシリコン層
及び高融点金属シリサイド層のうち少なくともどちらか
一方より構成される層を形成する工程と、 この層上にチタン層とその上部のチタンナイトライド層
とから成る積層及びチタン−タングステン合金層のうち
のどちらか一方より構成されるバリアメタル層を形成す
る工程と、 このバリアメタル層上にアルミニウム及びアルミニウム
合金のうちどちらか一方より構成される金属電極層を形
成する工程と、 この金属電極層にワイヤーをボンディングする工程とを
有することを特徴とする半導体装置の製造方法。
(1) A step of forming a layer consisting of at least one of a polysilicon layer and a high melting point metal silicide layer on an insulating oxide film on a semiconductor substrate, and a titanium layer on this layer and a titanium layer on top of the layer. A step of forming a barrier metal layer made of either a laminated layer consisting of a nitride layer or a titanium-tungsten alloy layer, and a step of forming a barrier metal layer made of either aluminum or an aluminum alloy on the barrier metal layer. 1. A method for manufacturing a semiconductor device, comprising: forming a metal electrode layer; and bonding a wire to the metal electrode layer.
(2)半導体基板上の絶縁酸化膜上にシリケイトガラス
膜を形成して平坦化する工程と、 このシリケイトガラス膜上にポリシリコン層及び高融点
金属シリサイド層のうち少なくともどちらか一方より構
成される層を形成する工程と、この層上にチタン層と、
その上部のチタンナイトライド層とから成る積層及びチ
タン−タングステン合金層のうちのどちらか一方より構
成されるバリアメタル層を形成する工程と、 このバリアメタル層上にアルミニウム及びアルミニウム
合金のうちどちらか一方より構成される金属電極層を形
成する工程と、 この金属電極層にワイヤーをボンディングする工程とを
有することを特徴とする半導体装置の製造方法。
(2) A step of forming and planarizing a silicate glass film on an insulating oxide film on a semiconductor substrate, and forming at least one of a polysilicon layer and a high melting point metal silicide layer on this silicate glass film. a step of forming a layer, a titanium layer on this layer,
A step of forming a barrier metal layer consisting of either a laminated layer consisting of a titanium nitride layer on top of the layer or a titanium-tungsten alloy layer, and forming either aluminum or an aluminum alloy on the barrier metal layer. 1. A method for manufacturing a semiconductor device, comprising the steps of: forming a metal electrode layer composed of one metal electrode layer; and bonding a wire to the metal electrode layer.
JP1214852A 1989-03-14 1989-08-23 Manufacture of semiconductor device Pending JPH0316145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1214852A JPH0316145A (en) 1989-03-14 1989-08-23 Manufacture of semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1-59702 1989-03-14
JP5970289 1989-03-14
JP1214852A JPH0316145A (en) 1989-03-14 1989-08-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0316145A true JPH0316145A (en) 1991-01-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP1214852A Pending JPH0316145A (en) 1989-03-14 1989-08-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0316145A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130789A (en) * 1993-11-04 1995-05-19 Nec Corp Semiconductor device
US6417568B1 (en) 1999-03-12 2002-07-09 Nec Corporation Semiconductor device
JP2004128513A (en) * 2003-11-26 2004-04-22 Rohm Co Ltd Semiconductor device and its manufacturing method
US6794732B2 (en) 2001-07-25 2004-09-21 Rohn Co., Ltd. Semiconductor device and method of manufacturing the same
US7759803B2 (en) 2001-07-25 2010-07-20 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
CN105679813A (en) * 2014-12-03 2016-06-15 丰田自动车株式会社 Semiconductor device and manufacturing method therefor

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130789A (en) * 1993-11-04 1995-05-19 Nec Corp Semiconductor device
US6417568B1 (en) 1999-03-12 2002-07-09 Nec Corporation Semiconductor device
US6794732B2 (en) 2001-07-25 2004-09-21 Rohn Co., Ltd. Semiconductor device and method of manufacturing the same
US7244635B2 (en) 2001-07-25 2007-07-17 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
US7759803B2 (en) 2001-07-25 2010-07-20 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
US8049343B2 (en) 2001-07-25 2011-11-01 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
JP2004128513A (en) * 2003-11-26 2004-04-22 Rohm Co Ltd Semiconductor device and its manufacturing method
JP4740536B2 (en) * 2003-11-26 2011-08-03 ローム株式会社 Semiconductor device and manufacturing method thereof
CN105679813A (en) * 2014-12-03 2016-06-15 丰田自动车株式会社 Semiconductor device and manufacturing method therefor
JP2016111084A (en) * 2014-12-03 2016-06-20 トヨタ自動車株式会社 Semiconductor device and method of manufacturing the same
US9698103B2 (en) 2014-12-03 2017-07-04 Toyota Jidosha Kabushiki Kaisha Semiconductor device and manufacturing method therefor

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