JP2000208520A - Semiconductor integrated circuit device and its manufacture - Google Patents

Semiconductor integrated circuit device and its manufacture

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Publication number
JP2000208520A
JP2000208520A JP2000049519A JP2000049519A JP2000208520A JP 2000208520 A JP2000208520 A JP 2000208520A JP 2000049519 A JP2000049519 A JP 2000049519A JP 2000049519 A JP2000049519 A JP 2000049519A JP 2000208520 A JP2000208520 A JP 2000208520A
Authority
JP
Japan
Prior art keywords
film
barrier metal
depositing
wiring
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000049519A
Other languages
Japanese (ja)
Inventor
Masayasu Suzuki
正恭 鈴樹
Shinji Nishihara
晋治 西原
Masashi Sawara
政司 佐原
Shinichi Ishida
進一 石田
Hiromi Abe
宏美 阿部
Sonoko Toda
園子 遠田
Hiroyuki Uchiyama
博之 内山
Hideaki Tsugane
秀明 津金
Aimei Yoshiura
愛明 吉浦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP2000049519A priority Critical patent/JP2000208520A/en
Publication of JP2000208520A publication Critical patent/JP2000208520A/en
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
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Abstract

PROBLEM TO BE SOLVED: To enhance adhesion of a bonding pad to a wire. SOLUTION: In this semiconductor integrated circuit device, an Al wire 35 of an uppermost layer is constituted by a composite film, comprising a first barrier metal constituted by lamination films of a Ti film 30 and a TiN film 32, and a second barrier metal constituted by an Al-Si-Cu film 33 deposited on this barrier metal and a TiN film 34 deposited on the Al-Si-Cu film 33, thereby preventing deposition of a reaction product of Al and Ti on the surface of a bonding pad.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体集積回路装
置およびその製造技術に関し、特に、多層配線を有する
ＬＳＩの配線構造ならびに配線加工プロセスに適用して
有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique therefor, and more particularly to a technique effective when applied to a wiring structure and a wiring processing process of an LSI having a multilayer wiring.

【０００２】[0002]

【従来の技術】近年、ＬＳＩの集積化が進み、上層のＡ
ｌ配線と下層のＡｌ配線とを接続する接続孔のアスペク
ト比（接続孔の深さ／径）が増大していることから、接
続孔の内部でのＡｌ配線の導通を確保するために、接続
孔にＷ（タングステン）膜を埋め込む、いわゆるタング
ステンプラグ技術が利用されている。2. Description of the Related Art In recent years, the integration of LSIs has advanced, and A
Since the aspect ratio (depth / diameter of the connection hole) of the connection hole for connecting the 1 wiring and the lower Al wiring is increased, the connection is required to secure the conduction of the Al wiring inside the connection hole. A so-called tungsten plug technique for embedding a W (tungsten) film in a hole is used.

【０００３】接続孔にＷ膜を埋め込むには、接続孔を形
成した絶縁膜上の全面にＣＶＤ法でＷ膜を堆積し、次い
で、絶縁膜上のＷ膜をエッチバックで除去して接続孔の
内部のみにＷ膜を残す。このとき、Ｗ膜のエッチバック
にはＦ（フッ素）プラズマを用いるので、下地の絶縁膜
（酸化シリコン膜）がＦプラズマによって削られるのを
防止するために、あらかじめＷ膜の下にＴｉ膜とＴｉＮ
膜との積層膜で構成されたバリアメタルを敷いておく。In order to bury a W film in a connection hole, a W film is deposited on the entire surface of the insulating film in which the connection hole is formed by a CVD method, and then the W film on the insulation film is removed by etch-back. The W film is left only in the inside. At this time, F (fluorine) plasma is used for the etch back of the W film. Therefore, in order to prevent the underlying insulating film (silicon oxide film) from being etched by the F plasma, a Ti film is previously formed under the W film. TiN
A barrier metal composed of a laminated film with a film is laid.

【０００４】また、上記Ｔｉ／ＴｉＮ積層膜で構成され
たバリアメタルは、エレクトロマイグレーションやスト
レスマイグレーションに対する耐性が大きく、かつ露光
光によるフォトレジストのハレーション防止効果も高い
ことから、サブミクロン・オーダーのデザインルールで
製造されるＬＳＩの配線には、Ａｌ膜の上下にこのバリ
アメタルを積層したＡｌ複合膜（ＴｉＮ／Ｔｉ／Ａｌ−
Ｓｉ−Ｃｕ／Ｔｉ／ＴｉＮ）が用いられている。なお、
Ｔｉ／ＴｉＮ積層膜で構成されたバリアメタルについて
は、例えば株式会社プレスジャーナル、1992年11月20日
発行の「セミコンダクターワールド」p196〜p205などに
記載がある。The barrier metal composed of the Ti / TiN laminated film has a high resistance to electromigration and stress migration, and has a high effect of preventing photoresist from being halated by exposure light. The wiring of the LSI manufactured according to the rule includes an Al composite film (TiN / Ti / Al-) in which the barrier metal is laminated above and below the Al film.
(Si-Cu / Ti / TiN) is used. In addition,
The barrier metal composed of the Ti / TiN laminated film is described in, for example, “Semiconductor World”, published on November 20, 1992, pages 196 to 205, by Press Journal.

【０００５】[0005]

【発明が解決しようとする課題】本発明者が検討したと
ころによると、前記従来の技術には次のような問題点が
ある。 （１）接続孔にＷ膜を埋め込むプロセスでは、前述した
ようにＦ（フッ素）プラズマを用いたエッチバックで絶
縁膜上のＷ膜を除去するため、このエッチバックによっ
て露出した絶縁膜上のバリアメタル（Ｔｉ／ＴｉＮ積層
膜）の表面にプラズマ中のＦの一部が残留する。そのた
め、エッチバックに引き続いてこのバリアメタル上に上
層配線のバリアメタル（Ｔｉ膜）あるいはＡｌ膜を堆積
すると、この２層の膜の界面の接着力がＦ残渣の影響で
低下する。According to studies made by the present inventors, the above-mentioned prior art has the following problems. (1) In the process of embedding the W film in the connection hole, the W film on the insulating film is removed by the etch back using the F (fluorine) plasma as described above. Part of F in the plasma remains on the surface of the metal (Ti / TiN laminated film). Therefore, if a barrier metal (Ti film) or an Al film of the upper wiring is deposited on the barrier metal subsequent to the etch back, the adhesive force at the interface between the two layers is reduced by the influence of the F residue.

【０００６】特に、このような現象が最上層配線のバリ
アメタルとその下層のバリアメタルとの界面で起こる
と、最上層配線の一部によって構成されるボンディング
パッドにワイヤをボンディングした際の衝撃でボンディ
ングパッドが剥離することがある。 （２）また、接続孔にＷ膜を埋め込むプロセスでは、接
続孔の内部のみにＷ膜を残すために、絶縁膜上のＷ膜を
オーバーエッチングで完全に除去しなければならない。
このとき、接続孔内のＷ膜の表面もこのオーバーエッチ
ングで削られるため、絶縁膜の表面と接続孔内のＷ膜の
表面との間に段差が発生する。In particular, when such a phenomenon occurs at the interface between the barrier metal of the uppermost layer wiring and the barrier metal of the lower layer, the impact caused when the wire is bonded to the bonding pad formed by a part of the uppermost layer wiring is obtained. The bonding pad may peel off. (2) In the process of embedding the W film in the connection hole, the W film on the insulating film must be completely removed by overetching in order to leave the W film only inside the connection hole.
At this time, since the surface of the W film in the connection hole is also shaved by this over-etching, a step is generated between the surface of the insulating film and the surface of the W film in the connection hole.

【０００７】そのため、この絶縁膜上にＡｌ配線を形成
すると、上記段差に起因して接続孔の真上のＡｌ配線の
表面にも段差ができる。その結果、接続孔の真上の層間
絶縁膜に上記Ａｌ配線とさらに上層のＡｌ配線とを接続
する第２の接続孔を形成しようとすると、第２の接続孔
の加工精度が低下するため、接続孔の真上に上層の接続
孔を配置する、いわゆるスタックオンプラグ(Stack On
Plug) 構造を実現することができない。 （３）前述したように、Ａｌ配線は、Ａｌ膜の上下にバ
リアメタルを積層したＡｌ複合膜（ＴｉＮ／Ｔｉ／Ａｌ
−Ｓｉ−Ｃｕ／Ｔｉ／ＴｉＮ）で構成される。ところ
が、最上層配線をこのＡｌ複合膜で構成すると、最上層
配線を覆うパッシベーション膜の一部をエッチングで除
去してボンディングパッドを形成する際、Ａｌ膜とその
表面のバリアメタル（Ｔｉ／ＴｉＮ積層膜）との界面に
ＡｌとＴｉとが反応してできた化合物が析出し、その影
響でボンディングパッドとワイヤの接着力が低下する。 （４）Ａｌ配線は、スパッタ法で堆積したＡｌ複合膜を
ドライエッチングで加工して形成する。しかし、Ａｌ複
合膜を堆積する際に下地段差の影響でＡｌ膜のカバレー
ジが低下すると、ドライエッチングによる配線の加工精
度が低下する。そこで、その対策として、半導体基板を
高温に保ち、Ａｌ膜をその熱でリフローさせながら堆積
することによりカバレージを確保する、いわゆる高温Ａ
ｌスパッタ技術が提案されている。Therefore, when an Al wiring is formed on this insulating film, a step is formed on the surface of the Al wiring just above the connection hole due to the above-mentioned step. As a result, if it is attempted to form a second connection hole for connecting the Al wiring and the Al wiring in the upper layer in the interlayer insulating film immediately above the connection hole, the processing accuracy of the second connection hole is reduced. A so-called Stack-On-Plug (Stack On Plug) that arranges the upper layer connection hole directly above the connection hole
Plug) structure cannot be realized. (3) As described above, the Al wiring is made of an Al composite film (TiN / Ti / Al) in which a barrier metal is laminated above and below the Al film.
-Si-Cu / Ti / TiN). However, when the uppermost layer wiring is formed of this Al composite film, when a part of the passivation film covering the uppermost layer wiring is removed by etching to form a bonding pad, the Al film and a barrier metal (Ti / TiN laminate) on the surface thereof are formed. A compound formed by the reaction of Al and Ti precipitates at the interface with the film), and the adhesive force between the bonding pad and the wire is reduced due to the effect. (4) The Al wiring is formed by processing an Al composite film deposited by a sputtering method by dry etching. However, if the coverage of the Al film is reduced due to the influence of the step of the base when depositing the Al composite film, the processing accuracy of the wiring by dry etching is reduced. Therefore, as a countermeasure, a so-called high-temperature A is used in which the semiconductor substrate is kept at a high temperature and the Al film is deposited while being reflowed by the heat to secure coverage.
1 Sputter technology has been proposed.

【０００８】ところが、Ａｌ膜、特にＣｕを添加したＡ
ｌ−Ｓｉ−Ｃｕ膜やＡｌ−Ｃｕ膜を高温スパッタで堆積
すると、膜中に反応析出物が生じ、これがドライエッチ
ングによるＡｌ配線の加工精度を低下させる新たな原因
となる。However, an Al film, particularly, A
When an l-Si-Cu film or an Al-Cu film is deposited by high-temperature sputtering, reaction precipitates are generated in the film, and this is a new cause of lowering the processing accuracy of the Al wiring by dry etching.

【０００９】本発明の目的は、Ａｌ複合膜によって構成
されたボンディングパッドの剥離を防止することのでき
る技術を提供することにある。An object of the present invention is to provide a technique capable of preventing peeling of a bonding pad formed of an Al composite film.

【００１０】本発明の他の目的は、Ａｌ複合膜によって
構成されたボンディングパッドとワイヤの接着力を向上
させることのできる技術を提供することにある。Another object of the present invention is to provide a technique capable of improving the adhesive force between a bonding pad formed of an Al composite film and a wire.

【００１１】本発明の他の目的は、接続孔の真上の層間
絶縁膜に上層の接続孔を配置するスタックオンプラグ構
造を実現することのできる技術を提供することにある。Another object of the present invention is to provide a technique capable of realizing a stack-on-plug structure in which an upper-layer connection hole is arranged in an interlayer insulating film immediately above a connection hole.

【００１２】本発明の他の目的は、高温Ａｌスパッタ法
でＡｌ膜を堆積する際に、Ａｌ膜中に反応析出物が生じ
るのを防止することのできる技術を提供することにあ
る。Another object of the present invention is to provide a technique capable of preventing a reaction precipitate from being formed in an Al film when the Al film is deposited by a high-temperature Al sputtering method.

【００１３】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

【００１４】[0014]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
次のとおりである。 （１）本発明の半導体集積回路装置は、半導体基板上の
複数層のＡｌ配線のうち、最上層配線が、Ｔｉ膜とＴｉ
Ｎ膜との積層膜で構成される第１のバリアメタルと、前
記第１のバリアメタル上に堆積したＡｌ膜と、前記Ａｌ
膜上に堆積したＴｉＮ膜で構成される第２のバリアメタ
ルとの複合膜で構成され、他の配線層のＡｌ配線が、Ａ
ｌ膜の上下にＴｉ膜とＴｉＮ膜との積層膜で構成される
バリアメタルを積層した複合膜で構成されているもので
ある。 （２）本発明の半導体集積回路装置の製造方法は、
（ａ）接続孔を形成した絶縁膜上にＴｉ膜とＴｉＮ膜と
の積層膜で構成される第１のバリアメタルを堆積する工
程、（ｂ）前記第１のバリアメタル上にＷ膜を堆積した
後、フッ素を含んだプラズマで前記Ｗ膜をエッチバック
することにより、前記接続孔の内部のみに前記Ｗ膜を残
す工程、（ｃ）前記第１のバリアメタルの表面をスパッ
タエッチングすることにより、前記第１のバリアメタル
の表面に残ったフッ素を除去する工程、（ｄ）前記第１
のバリアメタル上に、Ｔｉ膜で構成される第３のバリア
メタルと、Ａｌ膜と、Ｔｉ膜とＴｉＮ膜との積層膜で構
成される第４のバリアメタルとを順次堆積した後、前記
第４のバリアメタル、前記Ａｌ膜、前記第３のバリアメ
タルおよび前記第１のバリアメタルをパターニングして
配線を形成する工程、を備えている。 （３）本発明の半導体集積回路装置の製造方法は、半導
体基板上にスパッタ法でＡｌ膜を堆積する際、低温、高
スパッタレートでＡｌ膜を堆積する第１の工程と、高
温、低スパッタレートでさらにＡｌ膜を堆積する第２の
工程とを備えている。 （４）本発明の半導体集積回路装置の製造方法は、
（ａ）接続孔を形成した絶縁膜上にＷ膜を堆積した後、
前記Ｗ膜をエッチバックすることにより、前記接続孔の
内部のみに前記Ｗ膜を残す工程、（ｂ）前記絶縁膜上に
スパッタ法でＡｌ膜を堆積する工程、（ｃ）前記Ａｌ膜
を高温でリフローする工程、（ｄ）前記Ａｌ膜をパター
ニングしてＡｌ配線を形成する工程、を備えている。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. (1) In a semiconductor integrated circuit device according to the present invention, among a plurality of layers of Al wiring on a semiconductor substrate, the uppermost layer wiring is composed of a Ti film and a Ti film.
A first barrier metal formed of a laminated film of an N film, an Al film deposited on the first barrier metal,
It is composed of a composite film with a second barrier metal composed of a TiN film deposited on the film, and the Al wiring of the other wiring layer is made of A
It is composed of a composite film in which a barrier metal composed of a laminated film of a Ti film and a TiN film is laminated above and below the l film. (2) The method for manufacturing a semiconductor integrated circuit device according to the present invention includes:
(A) a step of depositing a first barrier metal composed of a laminated film of a Ti film and a TiN film on an insulating film having connection holes formed therein, and (b) depositing a W film on the first barrier metal. After that, a step of leaving the W film only inside the connection hole by etching back the W film with a plasma containing fluorine, and (c) performing a sputter etching on a surface of the first barrier metal. Removing fluorine remaining on the surface of the first barrier metal; (d) removing the first barrier metal;
After sequentially depositing a third barrier metal composed of a Ti film, an Al film, and a fourth barrier metal composed of a laminated film of a Ti film and a TiN film on the barrier metal, 4) forming a wiring by patterning the barrier metal, the Al film, the third barrier metal, and the first barrier metal. (3) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, when an Al film is deposited on a semiconductor substrate by a sputtering method, a first step of depositing the Al film at a low temperature and a high sputter rate; A second step of further depositing an Al film at a rate. (4) The method of manufacturing a semiconductor integrated circuit device of the present invention
(A) After depositing a W film on the insulating film in which the connection hole is formed,
A step of leaving the W film only inside the connection hole by etching back the W film, (b) depositing an Al film on the insulating film by a sputtering method, and (c) heating the Al film at a high temperature. And (d) forming an Al wiring by patterning the Al film.

【００１５】上記した手段（１）によれば、最上層配線
の表面のバリアメタルをＴｉＮ膜で構成することによ
り、最上層配線を覆うパッシベーション膜の一部をエッ
チングで除去してボンディングパッドを形成する際、Ａ
ｌ膜とその表面のバリアメタルとの界面に反応物が析出
するのを防止することができる。According to the above means (1), by forming the barrier metal on the surface of the uppermost layer wiring by a TiN film, a part of the passivation film covering the uppermost layer wiring is removed by etching to form a bonding pad. When doing, A
It is possible to prevent a reactant from being deposited at the interface between the film and the barrier metal on the surface.

【００１６】上記した手段（２）によれば、第１のバリ
アメタルの表面をスパッタエッチングしてその表面に残
ったフッ素を除去することにより、このバリアメタルと
その上に堆積する上層配線のバリアメタルの界面の接着
力が向上する。According to the above-mentioned means (2), the surface of the first barrier metal is sputter-etched to remove fluorine remaining on the surface, whereby the barrier metal and the barrier of the upper wiring deposited thereon are removed. The adhesive strength at the metal interface is improved.

【００１７】上記した手段（３）によれば、低温、高ス
パッタレートでＡｌ膜を堆積する第１の工程と、高温、
低スパッタレートでさらにＡｌ膜を堆積する第２の工程
の２段階でＡｌ膜を堆積することにより、Ａｌ膜中に反
応物が析出するのを防止することができるので、カバレ
ージが良好で、かつ表面凹凸の少ないＡｌ膜が得られ
る。According to the above means (3), the first step of depositing an Al film at a low temperature and a high sputtering rate,
By depositing the Al film in two stages of the second step of further depositing the Al film at a low sputter rate, it is possible to prevent a reactant from being deposited in the Al film, so that the coverage is good and An Al film with less surface irregularities can be obtained.

【００１８】上記した手段（４）によれば、スパッタ法
でＡｌ膜を堆積した後、このＡｌ膜を高温でリフローす
ることにより、Ｗ膜を埋め込んだ接続孔の真上のＡｌ配
線の表面を平坦化することができる。According to the above means (4), after the Al film is deposited by the sputtering method, the Al film is reflowed at a high temperature, so that the surface of the Al wiring just above the connection hole in which the W film is embedded is removed. It can be planarized.

【００１９】[0019]

【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。なお、実施の形態を説明す
るための全図において同一機能を有するものは同一の符
号を付し、その繰り返しの説明は省略する。Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted.

【００２０】本実施の形態は、３層配線を備えたＭＯＳ
・ＬＳＩに適用したものであり、その製造方法を図１〜
図１７を用いて工程順に説明する。In this embodiment, a MOS having three-layer wiring
-Applied to LSI, and its manufacturing method is shown in Figs.
The steps will be described with reference to FIG.

【００２１】まず、図１に示すように、ｐ- 型の単結晶
シリコンからなる半導体基板１の主面にｐ型不純物（ホ
ウ素）をイオン注入してｐ型ウエル２を形成した後、ｐ
型ウエル２の主面に選択酸化（ＬＯＣＯＳ）法でフィー
ルド酸化膜３を形成する。続いて、フィールド酸化膜３
で囲まれたｐ型ウエル２の主面に熱酸化法でゲート酸化
膜５を形成した後、ｐ型ウエル２にｐ型不純物（ホウ
素）をイオン注入し、フィールド酸化膜３の下部を含む
ｐ型ウエル２にｐ型のチャネルストッパ層４を形成す
る。First, as shown in FIG. 1, a p-type impurity (boron) is ion-implanted into a main surface of a semiconductor substrate 1 made of p- type single crystal silicon to form a p-type well 2, and then a p-type well 2 is formed.
A field oxide film 3 is formed on the main surface of the mold well 2 by a selective oxidation (LOCOS) method. Subsequently, the field oxide film 3
After a gate oxide film 5 is formed by thermal oxidation on the main surface of the p-type well 2 surrounded by a circle, p-type impurities (boron) are ion-implanted into the p-type well 2 to form a p-type impurity including the lower portion of the field oxide film 3. A p-type channel stopper layer 4 is formed in the mold well 2.

【００２２】次に、半導体基板１上にＣＶＤ法で多結晶
シリコン膜および酸化シリコン膜９を順次堆積した後、
フォトレジストをマスクにしたドライエッチングで上記
２層の膜をパターニングすることにより、多結晶シリコ
ン膜でＭＩＳＦＥＴのゲート電極６を形成する。ゲート
電極６を構成する多結晶シリコン膜には、その抵抗値を
低減するためにｎ型の不純物（例えばＰ）を導入する。
なお、ゲート電極６は、多結晶シリコン膜の上部にＷＳ
ｉx 、ＭｏＳｉx 、ＴｉＳｉx 、ＴａＳｉx などの高融
点金属シリサイド膜を積層したポリサイド膜で構成して
もよい。Next, after a polycrystalline silicon film and a silicon oxide film 9 are sequentially deposited on the semiconductor substrate 1 by the CVD method,
The gate electrode 6 of the MISFET is formed of a polycrystalline silicon film by patterning the two layers by dry etching using a photoresist as a mask. An n-type impurity (for example, P) is introduced into the polycrystalline silicon film forming the gate electrode 6 in order to reduce the resistance value.
The gate electrode 6 has a WS
It may be constituted by a polycide film in which a high melting point metal silicide film such as ix, MoSix, TiSix, TaSix or the like is laminated.

【００２３】次に、半導体基板１上にＣＶＤ法で酸化シ
リコン膜を堆積した後、反応性イオンエッチング（ＲＩ
Ｅ）法でこの酸化シリコン膜を異方性エッチングするこ
とにより、ゲート電極６の側壁にサイドウォールスペー
サ９を形成する。Next, after depositing a silicon oxide film on the semiconductor substrate 1 by the CVD method, reactive ion etching (RI
The side wall spacer 9 is formed on the side wall of the gate electrode 6 by anisotropically etching the silicon oxide film by the method E).

【００２４】次に、ｐ型ウエル２にｎ型不純物（リン）
をイオン注入してゲート電極６の両側のｐ型ウエル２に
ＭＩＳＦＥＴのソース、ドレイン領域を構成するｎ型半
導体領域７，７を形成する。Next, an n-type impurity (phosphorus) is added to the p-type well 2.
Are implanted into the p-type well 2 on both sides of the gate electrode 6 to form n-type semiconductor regions 7 and 7 constituting source and drain regions of the MISFET.

【００２５】次に、図２に示すように、半導体基板１上
にＣＶＤ法で酸化シリコン膜１０およびＢＰＳＧ膜１１
を順次堆積した後、フォトレジストをマスクにしたドラ
イエッチングで上記ＢＰＳＧ膜１１、酸化シリコン膜１
０およびゲート酸化膜５をエッチングすることにより、
ＭＩＳＦＥＴの一方の半導体領域７に達する接続孔１２
を形成する。Next, as shown in FIG. 2, a silicon oxide film 10 and a BPSG film 11 are formed on the semiconductor substrate 1 by CVD.
BPSG film 11 and silicon oxide film 1 by dry etching using a photoresist as a mask.
0 and the gate oxide film 5 are etched,
Connection hole 12 reaching one semiconductor region 7 of MISFET
To form

【００２６】次に、図３に示すように、接続孔１２の内
部を含むＢＰＳＧ膜１１上にスパッタ法でＴｉ膜１３
（膜厚３０nm）およびＴｉＮ膜１４（膜厚７０nm）から
なるバリアメタルを堆積した後、ＴｉＮ膜１４上にＣＶ
Ｄ法でＷ膜１５（膜厚２５０nm）を堆積し、続いて図４
に示すように、フォトレジストをマスクにしたドライエ
ッチングで上記Ｗ膜１５、バリアメタル（ＴｉＮ膜１
４、Ｔｉ膜１３）をパターニングすることにより、第１
層目の配線であるＷ配線１６を形成する。Next, as shown in FIG. 3, a Ti film 13 is formed on the BPSG film 11 including the inside of the connection hole 12 by sputtering.
(Thickness 30 nm) and a barrier metal composed of a TiN film 14 (thickness 70 nm) are deposited.
A W film 15 (250 nm thick) is deposited by the D method.
As shown in FIG. 5, the W film 15 and the barrier metal (TiN film 1) are dry-etched using a photoresist as a mask.
4, by patterning the Ti film 13), the first
The W wiring 16 which is the wiring of the layer is formed.

【００２７】次に、図５に示すように、Ｗ配線１６の上
層に第１の層間絶縁膜１７を堆積する。層間絶縁膜１７
は、例えばＣＶＤ法で堆積した酸化シリコン膜、スピン
塗布法で堆積したスピンオングラス膜およびＣＶＤ法で
堆積した酸化シリコン膜の３層膜で構成する。Next, as shown in FIG. 5, a first interlayer insulating film 17 is deposited on the W wiring 16. Interlayer insulating film 17
Is composed of, for example, a three-layer film of a silicon oxide film deposited by a CVD method, a spin-on-glass film deposited by a spin coating method, and a silicon oxide film deposited by a CVD method.

【００２８】次に、フォトレジストをマスクにしたドラ
イエッチングでＷ配線１６上の層間絶縁膜１７に接続孔
１８を形成した後、接続孔１８の内部を含む層間絶縁膜
１７上にスパッタ法でＴｉ膜１９（膜厚３０nm）および
ＴｉＮ膜２０（膜厚１００nm）からなるバリアメタルを
堆積し、続いてＴｉＮ膜２０上にＣＶＤ法でＷ膜２１
（膜厚５００nm）を堆積する。Next, after a connection hole 18 is formed in the interlayer insulation film 17 on the W wiring 16 by dry etching using a photoresist as a mask, Ti is deposited on the interlayer insulation film 17 including the inside of the connection hole 18 by sputtering. A barrier metal comprising a film 19 (thickness 30 nm) and a TiN film 20 (thickness 100 nm) is deposited, and then a W film 21 is formed on the TiN film 20 by CVD.
(Thickness: 500 nm).

【００２９】次に、図６に示すように、Ｆ（フッ素）プ
ラズマを用いたエッチバックで層間絶縁膜１７上のＷ膜
２１を除去し、接続孔１８の内部にのみＷ膜２１を残
す。このとき、層間絶縁膜１７上のＷ膜２１を完全に除
去するためにＷ膜２１をオーバーエッチングするので、
接続孔１８の内部のＷ膜２１の表面もある程度削られ、
層間絶縁膜１７の表面との間に段差が発生する。Next, as shown in FIG. 6, the W film 21 on the interlayer insulating film 17 is removed by etch back using F (fluorine) plasma, and the W film 21 is left only inside the connection hole 18. At this time, since the W film 21 is over-etched to completely remove the W film 21 on the interlayer insulating film 17,
The surface of the W film 21 inside the connection hole 18 is also shaved to some extent,
A step occurs between the surface of the interlayer insulating film 17 and the surface.

【００３０】次に、図７に示すように、ＴｉＮ膜２０上
にスパッタ法でＴｉ膜２２（膜厚１０nm）およびＡｌ−
Ｓｉ−Ｃｕ膜２３（膜厚４００nm）を順次堆積する。こ
のとき、層間絶縁膜１７に形成された接続孔１８の真上
に位置するＡｌ−Ｓｉ−Ｃｕ膜２３の表面には、前述し
た層間絶縁膜１７の表面と接続孔１８内のＷ膜２１の表
面との段差に起因して段差が生じる。Next, as shown in FIG. 7, a Ti film 22 (10 nm thick) and an Al-
An Si-Cu film 23 (thickness: 400 nm) is sequentially deposited. At this time, the surface of the Al-Si-Cu film 23 located immediately above the connection hole 18 formed in the interlayer insulating film 17 has the surface of the interlayer insulating film 17 and the W film 21 in the connection hole 18 described above. A step occurs due to the step with the surface.

【００３１】そこで、本実施の形態では上記Ａｌ−Ｓｉ
−Ｃｕ膜２３を堆積した後、図８に示すように、半導体
基板１を加熱してＡｌ−Ｓｉ−Ｃｕ膜２３をリフローさ
せ、その表面を平坦化する。このときのリフロー条件
は、基板温度４５０℃、圧力１mTorr 、加熱時間１８０
秒であり、リフロー後のＡｌ−Ｓｉ−Ｃｕ膜２３の表面
の反射率は９１％（波長３６５nm）であった。Therefore, in the present embodiment, the above Al-Si
After depositing the -Cu film 23, as shown in FIG. 8, the semiconductor substrate 1 is heated to reflow the Al-Si-Cu film 23, and the surface thereof is planarized. The reflow conditions at this time are as follows: substrate temperature 450 ° C., pressure 1 mTorr, heating time 180
Seconds, and the reflectivity of the surface of the Al—Si—Cu film 23 after the reflow was 91% (wavelength 365 nm).

【００３２】次に、図９に示すように、Ａｌ−Ｓｉ−Ｃ
ｕ膜２３上にスパッタ法でＴｉ膜２４（膜厚１０nm）お
よびＴｉＮ膜２５（膜厚６０nm）からなるバリアメタル
を堆積した後、フォトレジストをマスクにしたドライエ
ッチングで上記ＴｉＮ膜２５、Ｔｉ膜２４、Ａｌ−Ｓｉ
−Ｃｕ膜２３、ＴｉＮ膜２０およびＴｉ膜１９をパター
ニングすることにより、第２層目の配線であるＡｌ配線
２６を形成する。Next, as shown in FIG.
After depositing a barrier metal comprising a Ti film 24 (thickness 10 nm) and a TiN film 25 (thickness 60 nm) on the u film 23 by a sputtering method, the TiN film 25 and the Ti film are dry-etched using a photoresist as a mask. 24, Al-Si
By patterning the Cu film 23, the TiN film 20, and the Ti film 19, an Al wiring 26 as a second layer wiring is formed.

【００３３】次に、図１０に示すように、Ａｌ配線２６
の上層に第２の層間絶縁膜２７を堆積する。層間絶縁膜
２７は、例えばＣＶＤ法で堆積した酸化シリコン膜、ス
ピン塗布法で堆積したスピンオングラス膜、ＣＶＤ法で
堆積した酸化シリコン膜の３層膜で構成する。Next, as shown in FIG.
A second interlayer insulating film 27 is deposited on the upper layer. The interlayer insulating film 27 is composed of, for example, a three-layer film of a silicon oxide film deposited by a CVD method, a spin-on glass film deposited by a spin coating method, and a silicon oxide film deposited by a CVD method.

【００３４】次に、フォトレジストをマスクにしたドラ
イエッチングで前記第１の層間絶縁膜１７に形成した接
続孔１８の真上に位置する層間絶縁膜２７に接続孔２８
を形成する。このとき、Ａｌ配線２６の表面（接続孔２
８の底部）は前記リフローによって平坦化されているの
で、接続孔１８の真上に接続孔２８を配置しても接続孔
２８の加工性が低下することはない。Next, a contact hole 28 is formed in the interlayer insulating film 27 located immediately above the contact hole 18 formed in the first interlayer insulating film 17 by dry etching using a photoresist as a mask.
To form At this time, the surface of the Al wiring 26 (connection hole 2
Since the bottom portion 8 is flattened by the reflow, the workability of the connection hole 28 does not decrease even if the connection hole 28 is arranged right above the connection hole 18.

【００３５】次に、図１１に示すように、接続孔２８の
内部を含む層間絶縁膜２７上にスパッタ法でＴｉ膜２９
（膜厚３０nm）およびＴｉＮ膜３０（膜厚１００nm）か
らなるバリアメタルを堆積した後、ＴｉＮ膜３０上にＣ
ＶＤ法でＷ膜３１（膜厚５００nm）を堆積する。続い
て、Ｆプラズマを用いたエッチバックで層間絶縁膜２７
上のＷ膜３１を除去し、接続孔２８の内部にのみＷ膜３
１を残す。このとき、エッチバックによって露出した層
間絶縁膜２７上のＴｉＮ膜３０の表面にプラズマ中のＦ
の一部が残留するので、ＴｉＮ膜３０の表面を熱酸化膜
（酸化シリコン膜）換算で１５nm程度スパッタエッチン
グしてＦを除去する。Next, as shown in FIG. 11, a Ti film 29 is formed on the interlayer insulating film 27 including the inside of the connection hole 28 by sputtering.
(Thickness: 30 nm) and a barrier metal composed of a TiN film 30 (thickness: 100 nm),
A W film 31 (thickness: 500 nm) is deposited by the VD method. Subsequently, the interlayer insulating film 27 is etched back using F plasma.
The upper W film 31 is removed, and the W film 3 is formed only inside the connection hole 28.
Leave one. At this time, the surface of the TiN film 30 on the interlayer insulating film 27 exposed by the etch back
Is removed, the surface of the TiN film 30 is sputter-etched by about 15 nm in terms of a thermal oxide film (silicon oxide film) to remove F.

【００３６】ここでＴｉＮ膜３０の表面をスパッタエッ
チングするのは、ＴｉＮ膜３０の表面がＦによって汚染
されると、その上に堆積する膜との界面の接着性が低下
し、後の工程でボンディングパッドにワイヤをボンディ
ングした際、ボンディングパッド直下の上記界面に剥離
が生じることを本発明者は見出したからである。Here, the reason why the surface of the TiN film 30 is sputter-etched is that when the surface of the TiN film 30 is contaminated with F, the adhesiveness of the interface with the film deposited thereon is reduced, and in a later step, This is because the present inventor has found that when the wire is bonded to the bonding pad, separation occurs at the interface immediately below the bonding pad.

【００３７】図１２は、スパッタエッチング前のＴｉＮ
膜３０の表面のＡＥＳ（オージェ電子分光）スペクトル
を示すグラフ図である。このスペクトル分析から、Ｔｉ
Ｎ膜３０の表面のＦ量は、１２atm ％と算出される。FIG. 12 shows TiN before sputter etching.
FIG. 3 is a graph showing an AES (Auger electron spectroscopy) spectrum of the surface of a film 30. From this spectral analysis,
The amount of F on the surface of the N film 30 is calculated as 12 atm%.

【００３８】図１３は、後述するように、ＴｉＮ膜３０
の上にスパッタ法でＴｉ膜３２、Ａｌ−Ｓｉ−Ｃｕ膜３
３を順次堆積した後にＳＩＭＳ分析で測定したＴｉＮ膜
３０とＴｉ膜３２の界面のＦイオン強度と上記スパッタ
エッチング量との関係を示すグラフ図である。ここでは
便宜上、ＴｉＮ膜３０のスパッタエッチング量を熱酸化
で形成した酸化シリコン膜のスパッタエッチング量に換
算して示す（ＴｉＮ膜のスパッタエッチング速度は、酸
化シリコン膜のスパッタエッチング速度の４０％）。こ
れにより、スパッタエッチングを行わなかったとき（図
中のＡ点）のＦ量は１２atm ％、スパッタエッチング量
が５nmのとき（図中のＢ点）のＦ量は６atm ％と算出さ
れる。FIG. 13 shows a TiN film 30 as will be described later.
Film 32, Al-Si-Cu film 3 by sputtering
3 is a graph showing the relationship between the F ion intensity at the interface between the TiN film 30 and the Ti film 32 measured by SIMS analysis after sequentially depositing No. 3 and the amount of sputter etching. Here, for convenience, the sputter etching amount of the TiN film 30 is shown in terms of the sputter etching amount of a silicon oxide film formed by thermal oxidation (the sputter etching rate of the TiN film is 40% of the sputter etching rate of the silicon oxide film). As a result, the amount of F when the sputter etching is not performed (point A in the figure) is calculated as 12 atm%, and the amount of F when the sputter etching amount is 5 nm (point B in the figure) is calculated as 6 atm%.

【００３９】図１４は、上記図１２のＡＥＳスペクトル
と図１３のＳＩＭＳ分析の結果から求めたＴｉＮ膜３０
／Ｔｉ膜３２界面のＦ量とスパッタエッチング量（酸化
シリコン膜換算）との関係を示すグラフ図である。ま
た、このスパッタエッチング量とボンディング不良との
関係を表１に示す。FIG. 14 shows the TiN film 30 obtained from the AES spectrum of FIG. 12 and the result of the SIMS analysis of FIG.
FIG. 6 is a graph showing the relationship between the amount of F at the interface of the / Ti film 32 and the amount of sputter etching (in terms of a silicon oxide film). Table 1 shows the relationship between the sputter etching amount and the bonding failure.

【００４０】[0040]

【表１】 [Table 1]

【００４１】表１から明らかなように、ＴｉＮ膜３０の
表面をスパッタエッチングしなかったときはボンディン
グパッドの剥がれが発生したが、スパッタエッチング量
が５、１０、２０、３０、５０nmのときはいずれもボン
ディングパッドの剥がれが発生しなかった。以上のこと
から、ＴｉＮ膜３０／Ｔｉ膜３２界面のＦ量が６atm％
以下（スパッタエッチング量が５nm以上）になるまでス
パッタエッチングを行うことにより、ボンディングパッ
ドの剥離を防止できることが判明した。As is apparent from Table 1, when the surface of the TiN film 30 was not sputter-etched, peeling of the bonding pad occurred. However, when the sputter-etching amount was 5, 10, 20, 30, or 50 nm, any Also, peeling of the bonding pad did not occur. From the above, the F content at the interface between the TiN film 30 and the Ti film 32 is 6 atm%.
It has been found that by performing sputter etching until the amount becomes less than or equal to (the sputter etching amount is 5 nm or more), peeling of the bonding pad can be prevented.

【００４２】なお、前記第２層目の配線（Ａｌ配線２
６）にはボンディングパッドを形成しないので上記のよ
うな問題は生じないが、Ｔｉ膜１９の表面がＦで汚染さ
れると、その上に堆積するＴｉＮ膜２０との界面の接着
力が低下する。従って、ＴｉＮ膜２０を堆積する前にＴ
ｉ膜１９の表面をスパッタエッチングすることが望まし
い。また、Ｆによる接着力の低下は、Ｔｉ膜の上にＴｉ
Ｎ膜を堆積する場合にのみ生じるとは限らず、例えばＴ
ｉ膜の上に直接Ａｌ−Ｓｉ−Ｃｕ膜を堆積するような場
合にも生じる可能性が高い。従って、この場合も、Ａｌ
−Ｓｉ−Ｃｕ膜を堆積する前にＴｉ膜の表面をスパッタ
エッチングすることが望ましい。The second layer wiring (Al wiring 2)
In 6), since no bonding pad is formed, the above problem does not occur. However, when the surface of the Ti film 19 is contaminated with F, the adhesive force at the interface with the TiN film 20 deposited thereon is reduced. . Therefore, before depositing the TiN film 20, T
It is desirable to sputter-etch the surface of the i-film 19. Also, the decrease in the adhesive force due to F is caused by the Ti film on the Ti film.
This does not necessarily occur only when an N film is deposited.
This is also likely to occur when depositing an Al-Si-Cu film directly on the i-film. Therefore, also in this case, Al
It is desirable to sputter-etch the surface of the Ti film before depositing the -Si-Cu film.

【００４３】次に、図１５に示すように、ＴｉＮ膜３０
上にスパッタ法でＴｉ膜３２（膜厚２０nm）およびＡｌ
−Ｓｉ−Ｃｕ膜３３（膜厚６００nm）を順次堆積する。
このとき、本実施の形態ではＡｌ−Ｓｉ−Ｃｕ膜３３の
堆積を２段階に分けて行う。具体的には、まず半導体基
板１の温度を１５０℃以下に保ち、スパッタレート１３
００〜１７００nm/min程度で１段階目の堆積を行う（膜
厚３００nm）。続いて半導体基板１の温度を２５０〜３
５０℃に保ち、スパッタレート４００〜８００nm/min程
度で２段階目の堆積を行う（膜厚３００nm）。Next, as shown in FIG.
Ti film 32 (thickness 20 nm) and Al
-An Si-Cu film 33 (600 nm thick) is sequentially deposited.
At this time, in the present embodiment, the deposition of the Al—Si—Cu film 33 is performed in two stages. Specifically, first, the temperature of the semiconductor substrate 1 is kept at 150 ° C. or lower, and the
The first-stage deposition is performed at about 00 to 1700 nm / min (thickness: 300 nm). Subsequently, the temperature of the semiconductor substrate 1 is set to 250 to 3
The second-stage deposition is performed at a sputtering rate of about 400 to 800 nm / min while maintaining the temperature at 50 ° C. (thickness: 300 nm).

【００４４】上記の条件で堆積したＡｌ−Ｓｉ−Ｃｕ膜
３３のシート抵抗と反射率とを表２に示す。表２のＡは
基板温度を１６５℃に保ち、１段階でＡｌ−Ｓｉ−Ｃｕ
膜３３を堆積した場合である。また、Ｂ，Ｃ，Ｄは基板
温度をそれぞれ２５０℃、３００℃、３５０℃に保ち、
２段階でＡｌ−Ｓｉ−Ｃｕ膜３３を堆積した場合であ
る。Table 2 shows the sheet resistance and the reflectance of the Al—Si—Cu film 33 deposited under the above conditions. A in Table 2 indicates that the substrate temperature was maintained at 165 ° C., and Al—Si—Cu
This is the case where the film 33 is deposited. B, C, and D maintain the substrate temperature at 250 ° C., 300 ° C., and 350 ° C., respectively.
This is a case where the Al—Si—Cu film 33 is deposited in two stages.

【００４５】[0045]

【表２】 [Table 2]

【００４６】この結果、低温（１６５℃）、高スパッタ
レート（１５００nm/min）および高温（２５０〜３５０
℃）、低スパッタレート（６００nm/min）の２段階スパ
ッタでＡｌ−Ｓｉ−Ｃｕ膜３３を堆積した場合（Ｂ，
Ｃ，Ｄ）は、いずれもシート抵抗および反射率が１段階
スパッタの場合（Ａ）と同程度で、しかも表面凹凸や膜
中の反応析出物が少なく、カバレージの良好なＡｌ−Ｓ
ｉ−Ｃｕ膜３３が得られた。As a result, a low temperature (165 ° C.), a high sputter rate (1500 nm / min), and a high temperature (250 to 350
° C), and the Al-Si-Cu film 33 is deposited by two-step sputtering at a low sputtering rate (600 nm / min) (B,
C and D) have the same sheet resistance and reflectivity as those in the case of one-step sputtering (A), and have less surface irregularities and reaction precipitates in the film, and have good coverage, and have good coverage.
An i-Cu film 33 was obtained.

【００４７】次に、図１６に示すように、Ａｌ−Ｓｉ−
Ｃｕ膜３３上にバリアメタルを堆積する。このバリアメ
タルは、スパッタ法で堆積したＴｉＮ膜３４（膜厚６０
nm）の単層で構成する。なお、Ａｌ−Ｓｉ−Ｃｕ膜３３
を堆積した後、前述したリフローを行ってその表面をさ
らに平坦化してもよい。また、Ａｌ−Ｓｉ−Ｃｕ膜３３
を堆積した後、半導体基板１を一旦スパッタ装置の外に
取り出し、Ａｌ−Ｓｉ−Ｃｕ膜３３を大気に曝してその
表面に酸化膜を形成してからバリアメタル（ＴｉＮ膜３
４）を堆積してもよい。Next, as shown in FIG.
A barrier metal is deposited on the Cu film 33. This barrier metal is formed of a TiN film 34 (film thickness 60) deposited by a sputtering method.
nm). Note that the Al—Si—Cu film 33
After depositing, the surface may be further flattened by performing the above-described reflow. The Al-Si-Cu film 33
Is deposited, the semiconductor substrate 1 is once taken out of the sputtering apparatus, the Al-Si-Cu film 33 is exposed to the air to form an oxide film on the surface thereof, and then the barrier metal (TiN film 3) is formed.
4) may be deposited.

【００４８】次に、フォトレジストをマスクにしたドラ
イエッチングで上記ＴｉＮ膜３４、Ａｌ−Ｓｉ−Ｃｕ膜
３３、Ｔｉ膜３２、ＴｉＮ膜３０およびＴｉ膜２９をパ
ターニングすることにより、最上層の配線であるＡｌ配
線３５を形成した後、Ａｌ配線３５の上層にパッシベー
ション膜３６を堆積する。パッシベーション膜３６は、
例えばＣＶＤ法で堆積した酸化シリコン膜とＣＶＤ法で
堆積した窒化シリコン膜の２層膜で構成する。Next, the TiN film 34, the Al—Si—Cu film 33, the Ti film 32, the TiN film 30, and the Ti film 29 are patterned by dry etching using a photoresist as a mask, so that the uppermost wiring is formed. After a certain Al wiring 35 is formed, a passivation film 36 is deposited on the Al wiring 35. The passivation film 36
For example, it is composed of a two-layer film of a silicon oxide film deposited by a CVD method and a silicon nitride film deposited by a CVD method.

【００４９】次に、図１７に示すように、フォトレジス
トをマスクにしたドライエッチングでパッシベーション
膜３６の一部を開孔し、Ａｌ配線３５の一部を露出させ
ることにより、ボンディングパッド３７を形成する。こ
のとき、ボンディングパッド３７（Ａｌ配線３５）の表
面のバリアメタルがＴｉＮ膜（３４）の単層（Ａｌ−Ｓ
ｉ−Ｃｕ膜３３の表面を酸化した場合は、ＴｉＮ膜と酸
化膜）で構成されているので、このバリアメタルをＴｉ
Ｎ膜とＴｉ膜の積層膜で構成した場合と異なり、ボンデ
ィングパッド３７の表面にＡｌとＴｉの化合物が析出す
るようなことはない。Next, as shown in FIG. 17, a portion of the passivation film 36 is opened by dry etching using a photoresist as a mask, and a portion of the Al wiring 35 is exposed to form a bonding pad 37. I do. At this time, the barrier metal on the surface of the bonding pad 37 (Al wiring 35) is a single layer (Al-S) of the TiN film (34).
When the surface of the i-Cu film 33 is oxidized, it is composed of a TiN film and an oxide film.
Unlike the case where the semiconductor device is constituted by a laminated film of the N film and the Ti film, the compound of Al and Ti does not precipitate on the surface of the bonding pad 37.

【００５０】従って、本実施の形態によれば、ボンディ
ングパッド３７の表面にＡｕのワイヤ３８をボンディン
グしたときに、ボンディングパッド３７とワイヤ３８の
接着力を十分に確保することができる。Therefore, according to the present embodiment, when the Au wire 38 is bonded to the surface of the bonding pad 37, the bonding strength between the bonding pad 37 and the wire 38 can be sufficiently ensured.

【００５１】また、本実施の形態によれば、最上層のＡ
ｌ配線３５の一部を構成するＴｉＮ膜３０の表面のＦを
スパッタエッチングで除去したことにより、ＴｉＮ膜３
０とその上に堆積したＴｉ膜３２の界面の接着力を十分
に確保することができるので、ボンディングパッド３７
の表面にワイヤ３８をボンディングしたときの衝撃など
によってボンディングパッド３７が剥離することもな
い。According to the present embodiment, the uppermost layer A
By removing the F on the surface of the TiN film 30 forming a part of the l wiring 35 by sputter etching, the TiN film 3
0 and the Ti film 32 deposited thereon can sufficiently secure the adhesive force at the interface.
The bonding pad 37 does not peel off due to an impact when the wire 38 is bonded to the surface of the bonding pad 37.

【００５２】以上、本発明者によってなされた発明を実
施の形態に基づき具体的に説明したが、本発明は前記実
施の形態に限定されるものではなく、その要旨を逸脱し
ない範囲で種々変更可能であることはいうまでもない。Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

【００５３】前記実施の形態では、３層配線を備えたＭ
ＯＳ・ＬＳＩに適用した場合について説明したが、４層
またはそれ以上の多層配線を備えたＬＳＩにも広く適用
することができる。In the above embodiment, M
Although the case where the present invention is applied to an OS / LSI has been described, the present invention can be widely applied to an LSI having four or more multi-layer wirings.

【００５４】[0054]

【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下の通りである。 （１）本発明によれば、ボンディングパッドとワイヤの
接着力が増加するため、ボンディングパッドとワイヤの
接続信頼性が向上する。 （２）本発明によれば、最上層配線のバリアメタルの界
面の接着力が増加するため、ボンディングパッドの剥離
を防止することができる。 （３）本発明によれば、カバレージが良好で、かつ表面
凹凸の少ないＡｌ膜が得られるので、Ａｌ配線の加工性
が向上する。 （４）本発明によれば、接続孔の真上の層間絶縁膜に上
層の接続孔を配置するスタックオンプラグ構造を実現す
ることができるので、チップ面積を縮小することができ
る。Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows. (1) According to the present invention, since the bonding force between the bonding pad and the wire increases, the connection reliability between the bonding pad and the wire improves. (2) According to the present invention, the bonding force at the interface of the barrier metal of the uppermost layer wiring is increased, so that peeling of the bonding pad can be prevented. (3) According to the present invention, an Al film having good coverage and small surface irregularities can be obtained, so that the workability of the Al wiring is improved. (4) According to the present invention, it is possible to realize a stack-on-plug structure in which an upper-layer connection hole is arranged in an interlayer insulating film immediately above a connection hole, so that a chip area can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施の形態である半導体集積回路装
置の製造方法を示す半導体基板の要部断面図である。FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

【図２】本発明の一実施の形態である半導体集積回路装
置の製造方法を示す半導体基板の要部断面図である。FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図３】本発明の一実施の形態である半導体集積回路装
置の製造方法を示す半導体基板の要部断面図である。FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図４】本発明の一実施の形態である半導体集積回路装
置の製造方法を示す半導体基板の要部断面図である。FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図５】本発明の一実施の形態である半導体集積回路装
置の製造方法を示す半導体基板の要部断面図である。FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図６】本発明の一実施の形態である半導体集積回路装
置の製造方法を示す半導体基板の要部断面図である。FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図７】本発明の一実施の形態である半導体集積回路装
置の製造方法を示す半導体基板の要部断面図である。FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図８】本発明の一実施の形態である半導体集積回路装
置の製造方法を示す半導体基板の要部断面図である。FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図９】本発明の一実施の形態である半導体集積回路装
置の製造方法を示す半導体基板の要部断面図である。FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図１０】本発明の一実施の形態である半導体集積回路
装置の製造方法を示す半導体基板の要部断面図である。FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図１１】本発明の一実施の形態である半導体集積回路
装置の製造方法を示す半導体基板の要部断面図である。FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図１２】スパッタエッチングを行う前のＴｉＮ膜の表
面のＡＥＳスペクトルを示すグラフ図である。FIG. 12 is a graph showing an AES spectrum of the surface of the TiN film before performing sputter etching.

【図１３】スパッタエッチング量とＴｉ／ＴｉＮ膜界面
のＦ量との関係を示すグラフ図である。FIG. 13 is a graph showing the relationship between the amount of sputter etching and the amount of F at the interface of the Ti / TiN film.

【図１４】スパッタエッチング量とＴｉ／ＴｉＮ膜界面
のＦイオン強度との関係を示すグラフ図である。FIG. 14 is a graph showing a relationship between a sputter etching amount and an F ion intensity at a Ti / TiN film interface.

【図１５】本発明の一実施の形態である半導体集積回路
装置の製造方法を示す半導体基板の要部断面図である。FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図１６】本発明の一実施の形態である半導体集積回路
装置の製造方法を示す半導体基板の要部断面図である。FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【図１７】本発明の一実施の形態である半導体集積回路
装置の製造方法を示す半導体基板の要部断面図である。FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the semiconductor integrated circuit device according to one embodiment of the present invention;

【符号の説明】[Explanation of symbols]

１ 半導体基板 ２ ｐ型ウエル ３ フィールド酸化膜 ４ チャネルストッパ領域 ５ ゲート酸化膜 ６ ゲート電極 ７ ｎ型半導体領域（ソース、ドレイン領域） ８ サイドウォールスペーサ ９ 酸化シリコン膜 １０ 酸化シリコン膜 １１ ＢＰＳＧ膜 １２ 接続孔 １３ Ｔｉ膜 １４ ＴｉＮ膜 １５ Ｗ膜 １６ Ｗ配線 １７ 層間絶縁膜 １８ 接続孔 １９ Ｔｉ膜 ２０ ＴｉＮ膜 ２１ Ｗ膜 ２２ Ｔｉ膜 ２３ Ａｌ−Ｓｉ−Ｃｕ膜 ２４ Ｔｉ膜 ２５ ＴｉＮ膜 ２６ Ａｌ配線 ２７ 層間絶縁膜 ２８ 接続孔 ２９ Ｔｉ膜 ３０ ＴｉＮ膜 ３１ Ｗ膜 ３２ Ｔｉ膜 ３３ Ａｌ−Ｓｉ−Ｃｕ膜 ３４ ＴｉＮ膜 ３５ Ａｌ配線 ３６ パッシベーション膜 ３７ ボンディングパッド ３８ ワイヤ Reference Signs List 1 semiconductor substrate 2 p-type well 3 field oxide film 4 channel stopper region 5 gate oxide film 6 gate electrode 7 n-type semiconductor region (source / drain region) 8 sidewall spacer 9 silicon oxide film 10 silicon oxide film 11 BPSG film 12 connection Hole 13 Ti film 14 TiN film 15 W film 16 W wiring 17 Interlayer insulating film 18 Connection hole 19 Ti film 20 TiN film 21 W film 22 Ti film 23 Al-Si-Cu film 24 Ti film 25 TiN film 26 Al wiring 27 interlayer Insulating film 28 Connection hole 29 Ti film 30 TiN film 31 W film 32 Ti film 33 Al-Si-Cu film 34 TiN film 35 Al wiring 36 Passivation film 37 Bonding pad 38 Wire

───────────────────────────────────────────────────── フロントページの続き (72)発明者 西原 晋治 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 佐原 政司 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 石田 進一 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 阿部 宏美 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 遠田 園子 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 内山 博之 東京都小平市上水本町５丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 津金 秀明 東京都小平市上水本町５丁目20番１号 日 立超エル・エス・アイ・エンジニアリング 株式会社内 (72)発明者 吉浦 愛明 東京都小平市上水本町５丁目22番１号 株 式会社日立マイコンシステム内 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shinji Nishihara 5-20-1, Kamisumihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. No. 20-1, Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Shinichi Ishida 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Incorporated Hitachi Semiconductor Co., Ltd. (72) Inventor Hiromi Abe Tokyo 5-20-1, Josuihonmachi, Kodaira-shi, Semiconductor Division, Hitachi, Ltd. (72) Inventor Sonoko Toda 5-2-1, Josuihoncho, Kodaira-shi, Tokyo, Semiconductor Division, Hitachi, Ltd. (72) Inventor Hiroyuki Uchiyama 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Inventor Hideaki Tsugane Tokyo Hitachi, Ltd. 5-2-1, Joami Honcho, Kochidaira, Tokyo 5-72-1, Kamizuhoncho, Kodaira-shi, Tokyo In microcomputer system

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上に複数層のＡｌ配線を有す
る半導体集積回路装置であって、前記半導体基板の最上
層配線は、Ｔｉ膜とＴｉＮ膜との積層膜で構成される第
１のバリアメタルと、前記第１のバリアメタル上に堆積
したＡｌ膜と、前記Ａｌ膜上に堆積したＴｉＮ膜で構成
される第２のバリアメタルとの複合膜で構成され、他の
配線層のＡｌ配線は、Ａｌ膜の上下に前記Ｔｉ膜とＴｉ
Ｎ膜との積層膜で構成される第１のバリアメタルを積層
した複合膜で構成されていることを特徴とする半導体集
積回路装置。1. A semiconductor integrated circuit device having a plurality of layers of Al wiring on a semiconductor substrate, wherein an uppermost layer wiring of the semiconductor substrate is a first barrier composed of a laminated film of a Ti film and a TiN film. A metal, an Al film deposited on the first barrier metal, and a composite film of a second barrier metal composed of a TiN film deposited on the Al film; Means that the Ti film and Ti
A semiconductor integrated circuit device comprising a composite film in which a first barrier metal composed of a laminated film with an N film is laminated. 【請求項２】 請求項１記載の半導体集積回路装置であ
って、前記第１のバリアメタルの表面のフッ素量が６．
０atm％以下であることを特徴とする半導体集積回路装
置。2. The semiconductor integrated circuit device according to claim 1, wherein the amount of fluorine on the surface of said first barrier metal is 6.
A semiconductor integrated circuit device characterized by being at most 0 atm%. 【請求項３】 請求項１記載の半導体集積回路装置の製
造方法であって、前記最上層配線は、前記第１のバリア
メタル上に前記Ａｌ膜を堆積した後、前記Ａｌ膜上に前
記ＴｉＮ膜を直接堆積することにより形成し、前記他の
配線層のＡｌ配線は、前記第１のバリアメタル上に前記
Ａｌ膜を堆積した後、前記Ａｌ膜上に前記Ｔｉ膜とＴｉ
Ｎ膜とを連続して堆積することにより形成することを特
徴とする半導体集積回路装置の製造方法。3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said uppermost layer wiring comprises: depositing said Al film on said first barrier metal; and forming said TiN film on said Al film. A film is formed by directly depositing a film, and the Al wiring of the other wiring layer is formed by depositing the Al film on the first barrier metal, and then forming the Ti film and the Ti film on the Al film.
A method for manufacturing a semiconductor integrated circuit device, wherein the method is formed by continuously depositing an N film. 【請求項４】 請求項１記載の半導体集積回路装置の製
造方法であって、前記最上層配線は、前記第１のバリア
メタル上に前記Ａｌ膜を堆積した後、前記Ａｌ膜の表面
を酸化し、次いで前記Ａｌ膜上に前記第２のバリアメタ
ルを堆積することにより形成することを特徴とする半導
体集積回路装置の製造方法。4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said uppermost layer wiring oxidizes a surface of said Al film after depositing said Al film on said first barrier metal. Forming the second barrier metal on the Al film by depositing the second barrier metal on the Al film. 【請求項５】 次の工程（ａ）〜（ｄ）を含むことを特
徴とする半導体集積回路装置の製造方法。 （ａ）接続孔を形成した絶縁膜上にＴｉ膜とＴｉＮ膜と
の積層膜で構成される第１のバリアメタルを堆積する工
程、（ｂ）前記第１のバリアメタル上にＷ膜を堆積した
後、フッ素を含んだプラズマで前記Ｗ膜をエッチバック
することにより、前記接続孔の内部のみに前記Ｗ膜を残
す工程、（ｃ）前記第１のバリアメタルの表面をスパッ
タエッチングすることにより、前記第１のバリアメタル
の表面に残ったフッ素を除去する工程、（ｄ）前記第１
のバリアメタル上に、Ｔｉ膜で構成される第３のバリア
メタルと、Ａｌ膜と、Ｔｉ膜とＴｉＮ膜との積層膜で構
成される第４のバリアメタルとを順次堆積した後、前記
第４のバリアメタル、前記Ａｌ膜、前記第３のバリアメ
タルおよび前記第１のバリアメタルをパターニングして
配線を形成する工程。5. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps (a) to (d). (A) a step of depositing a first barrier metal composed of a laminated film of a Ti film and a TiN film on an insulating film in which a connection hole is formed; (b) depositing a W film on the first barrier metal After that, a step of leaving the W film only in the inside of the connection hole by etching back the W film with a plasma containing fluorine, and (c) sputter etching the surface of the first barrier metal. Removing fluorine remaining on the surface of the first barrier metal; and (d) removing the first barrier metal.
After sequentially depositing a third barrier metal composed of a Ti film, an Al film, and a fourth barrier metal composed of a laminated film of a Ti film and a TiN film on the barrier metal, And 4. forming a wiring by patterning the barrier metal, the Al film, the third barrier metal, and the first barrier metal. 【請求項６】 次の工程（ａ）〜（ｄ）を含むことを特
徴とする半導体集積回路装置の製造方法。 （ａ）接続孔を形成した絶縁膜上にＴｉ膜とＴｉＮ膜と
の積層膜で構成される第１のバリアメタルを堆積する工
程、（ｂ）前記第１のバリアメタル上にＷ膜を堆積した
後、フッ素を含んだプラズマで前記Ｗ膜をエッチバック
することにより、前記接続孔の内部のみに前記Ｗ膜を残
す工程、（ｃ）前記第１のバリアメタルの表面をスパッ
タエッチングすることにより、前記第１のバリアメタル
の表面に残ったフッ素を除去する工程、（ｄ）前記第１
のバリアメタル上に、Ａｌ膜と、Ｔｉ膜とＴｉＮ膜との
積層膜で構成される第４のバリアメタルとを順次堆積し
た後、前記第４のバリアメタル、前記Ａｌ膜および前記
第１のバリアメタルをパターニングして配線を形成する
工程。6. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps (a) to (d). (A) a step of depositing a first barrier metal composed of a laminated film of a Ti film and a TiN film on an insulating film in which a connection hole is formed; (b) depositing a W film on the first barrier metal After that, a step of leaving the W film only in the inside of the connection hole by etching back the W film with a plasma containing fluorine, and (c) sputter etching the surface of the first barrier metal. Removing fluorine remaining on the surface of the first barrier metal; and (d) removing the first barrier metal.
After sequentially depositing an Al film and a fourth barrier metal composed of a laminated film of a Ti film and a TiN film on the barrier metal, the fourth barrier metal, the Al film and the first A step of forming wiring by patterning a barrier metal. 【請求項７】 次の工程（ａ）〜（ｄ）を含むことを特
徴とする半導体集積回路装置の製造方法。 （ａ）接続孔を形成した絶縁膜上にＷ膜を堆積した後、
前記Ｗ膜をエッチバックすることにより、前記接続孔の
内部のみに前記Ｗ膜を残す工程、（ｂ）前記絶縁膜上に
スパッタリング法でＡｌ膜を堆積する工程、（ｃ）前記
Ａｌ膜を高温でリフローする工程、（ｄ）前記Ａｌ膜を
パターニングすることにより、Ａｌ配線を形成する工
程。7. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps (a) to (d). (A) After depositing a W film on the insulating film in which the connection hole is formed,
A step of leaving the W film only inside the connection hole by etching back the W film, (b) depositing an Al film on the insulating film by a sputtering method, and (c) heating the Al film at a high temperature. And (d) forming an Al wiring by patterning the Al film. 【請求項８】 請求項７記載の半導体集積回路装置の製
造方法であって、半導体基板を４５０℃程度に保って前
記Ａｌ膜をリフローすることを特徴とする半導体集積回
路装置の製造方法。8. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the Al film is reflowed while keeping a semiconductor substrate at about 450 ° C.
JP2000049519A 2000-01-01 2000-02-25 Semiconductor integrated circuit device and its manufacture Pending JP2000208520A (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
JP2000049519A JP2000208520A (en) 2000-01-01 2000-02-25 Semiconductor integrated circuit device and its manufacture

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JP7002551A Division JPH08191104A (en) 1995-01-11 1995-01-11 Semiconductor integrated circuit device and manufacturing method thereof

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005019696A (en) * 2003-06-26 2005-01-20 Seiko Epson Corp Semiconductor device and method of manufacturing the same
JP2009027167A (en) * 2007-07-23 2009-02-05 Natl Semiconductor Corp <Ns> Pad lower side esd and bond pad stack for pad lower side active bonding
CN105720103A (en) * 2014-12-22 2016-06-29 三菱电机株式会社 Semiconductor device and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005019696A (en) * 2003-06-26 2005-01-20 Seiko Epson Corp Semiconductor device and method of manufacturing the same
JP2009027167A (en) * 2007-07-23 2009-02-05 Natl Semiconductor Corp <Ns> Pad lower side esd and bond pad stack for pad lower side active bonding
CN105720103A (en) * 2014-12-22 2016-06-29 三菱电机株式会社 Semiconductor device and method for manufacturing the same
JP2016119393A (en) * 2014-12-22 2016-06-30 三菱電機株式会社 Semiconductor device and manufacturing method of the same

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