JPH09326490A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make sufficient recovery feasible in the hydrogen annealing process for any step damage recovery. SOLUTION: An insulating film 14 is formed covering a transistor after the formation of a MOS transistor. Next, a polysilicon layer is deposited on the film 14 and after making connecting holes in these laminated layers, a Ti layer and a TiN layer are successively formed covering the connecting holes and the poly Si layer. Next, a TiSix layer is formed by the reaction between the Si layer and the Ti layer so as to form a conductive material layer 16' including the Ti layer inside the connecting holes and the TiSix layer outside the connecting holes as well as the TiN later covering these layers. Next, after depositing Al alloy, etc., covering the connecting holes and the layer 16', wiring layers 18Q, 18S, 18D are formed by patterning process. Finally, after hydrogen annealing the transistor, a passivation film 22 is formed through the intermediary of another insulating film 19, etc. In such a constitution, most of the Ti layer is silicified, thereby enabling the hydrogen absorption by the Ti in hydrogen annealing process to be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a MOS transistor is subjected to a heat treatment (hydrogen annealing treatment) in a hydrogen-containing atmosphere in order to recover process damage. The layer is silicidized to suppress hydrogen absorption by Ti, thereby enabling sufficient recovery.

[0002]

2. Description of the Related Art Conventionally, MOS has been used to recover process damage.
As the hydrogen annealing process applied to the transistor,
Hydrogen concentration of 5 to 20 in an atmosphere containing hydrogen and nitrogen
[%], Temperature 350 to 450 [° C.], time 10 to 130
It is known that heat treatment is performed under the condition of [minute] (for example, see JP-A-7-74167).

FIG. 18 shows an example of a conventional MOS type transistor, in which a field insulating film 2 is formed on the surface of a semiconductor substrate 1 made of silicon and an insulating film 2 is formed.
A MOS transistor T is formed on the semiconductor surface in the element hole. The transistor T includes a gate insulating film F, a gate electrode layer G, and side spacers H on both sides of the electrode layer G.
And a source region S ₁ and a drain region D ₁ having a relatively low impurity concentration and a source region S and a drain region D having a relatively high impurity concentration, so-called LDD (Li
ghtly Doped Drain) structure.

An interlayer insulating film 3 is formed on the insulating film 2 so as to cover the transistor T, and the insulating film 3 is provided with connection holes 3S corresponding to the source region S and the drain region D by photolithography and dry etching. , 3
D is formed. Then, an Al alloy is deposited on the upper surface of the substrate and patterned to form the source wiring layer 4S and the drain wiring layer 4D.

Next, the transistor T is subjected to the above-mentioned hydrogen annealing treatment in order to recover process damage due to etching or the like. The wiring layer 4S,
A PSG (phosphosilicate glass) film 5a is formed to cover 4D by a CVD (Chemical Vapor Deposition) method. Then, a silicon nitride film 5b is formed on the PSG film 5a by the plasma CVD method. The passivation film 5 is composed of films 5a and 5b.

According to the hydrogen annealing treatment as described above, process damage can be recovered.

[0007]

According to the above-mentioned hydrogen annealing treatment, it has been found that the process damage is not sufficiently recovered when the wiring material layer including the Ti layer is present above the MOS transistor.

FIG. 19 shows a state in which the same MOS type transistors T ₁ and T ₂ as those described in FIG. 18 are formed on the surface of the semiconductor substrate 1. An interlayer insulating film 6 is formed on the upper surface of the substrate 1 so as to cover the transistors T ₁ and T ₂ , and a wiring material layer 4 is formed on the insulating film 6 above the transistor T ₁ . The wiring material layer 4 is made of, for example, an Al alloy, and has a Ti layer 4a as the lowermost layer. Transistor T ₁ ,
After T ₂ is subjected to the above-mentioned hydrogen annealing treatment, a passivation film 7 of silicon nitride or the like is formed on the insulating film 6 so as to cover the wiring material layer 4.

According to such a manufacturing method, although the transistor T ₂ not covered with the wiring material layer 4 was sufficiently recovered from the process damage by the hydrogen annealing treatment,
Regarding the transistor T ₁ covered with the wiring material layer 4, it was not confirmed that the process damage was sufficiently recovered even if the hydrogen annealing treatment was performed. The inventor of the present application believes that the process damage is not sufficiently recovered because the Ti layer 4a absorbs hydrogen and therefore dangling bonds are not sufficiently terminated at the interface between the substrate and the gate insulating film. .

In order to deal with such a situation, an invention has been made whose gist is to set the hydrogen concentration in the annealing atmosphere to a high value in consideration of the hydrogen storage amount by the Ti layer. A person has already filed a patent application.

An object of the present invention is to provide a method for manufacturing a new semiconductor device capable of sufficiently recovering process damage without increasing the hydrogen concentration in the annealing atmosphere.

[0012]

A first method of manufacturing a semiconductor device according to the present invention comprises a step of forming a MOS type transistor on the surface of a semiconductor substrate, and a step of insulating the surface of the semiconductor substrate by covering the MOS type transistor. The step of forming a film, the step of forming a polysilicon layer on the insulating film, and the step of forming the polysilicon film on the insulating film and the polysilicon layer.
A step of forming a connection hole leading to the OS type transistor;
A step of forming a titanium layer and a barrier conductive layer in order from the bottom so as to cover the connection hole and the polysilicon layer; a step of reacting the polysilicon layer and the titanium layer to form a titanium silicide layer; Forming a conductive material layer over the connection hole and the barrier conductive layer after forming a silicide layer, and patterning a wiring material layer including the titanium silicide layer, the barrier conductive layer and the conductive material layer And forming the first and second wiring layers each made of the wiring material layer, the first wiring layer being formed so as to be connected to the MOS transistor through the connection hole, and Forming the second wiring layer so as to be separated from the first wiring layer so as to overlap the gate portion of the MOS transistor, the insulating film, and the first and second wiring layers The method includes a step of forming a passivation film so as to cover, and a step of subjecting the MOS type transistor to heat treatment in an atmosphere containing hydrogen for recovery of process damage after the patterning and before or after forming the passivation film. .

In the method of manufacturing the first semiconductor device according to the present invention, the second wiring layer is omitted and the first wiring layer is formed by MO.
It may be formed so as to overlap the gate portion of the S-type transistor.

According to the first method for manufacturing a semiconductor device of the present invention, the titanium layer as the lower layer of the barrier conductive layer is converted into the titanium silicide layer at the portions other than the connection holes, and the titanium layer remains at the connection. Only inside the hole. Therefore, in the hydrogen annealing treatment, hydrogen absorption by titanium is suppressed to a negligible level, and the process damage can be sufficiently recovered. The titanium layer remaining inside the contact hole after silicidation helps reduce the contact resistance.

A second method of manufacturing a semiconductor device according to the present invention comprises a step of forming a MOS type transistor on the surface of a semiconductor substrate, and a step of forming an insulating film on the surface of the semiconductor substrate to cover the MOS type transistor. A step of forming a connection hole in the insulating film leading to the MOS transistor, a step of forming a polysilicon layer, a titanium layer and a barrier conductive layer in order from the bottom to cover the connection hole and the insulating film; A step of reacting a polysilicon layer and the titanium layer to form a titanium silicide layer; a step of forming the titanium silicide layer and then forming a conductive material layer covering the connection hole and the barrier conductive layer; A wiring material layer including the titanium silicide layer, the barrier conductive layer, and the conductive material layer is patterned to form first and second wiring layers, respectively. A step of forming a layer, wherein the first wiring layer is formed so as to be connected to the MOS type transistor through the connection hole, and is separated from the first wiring layer, and the gate portion of the MOS type transistor is formed. Forming the second wiring layer so as to overlap with the above, a step of forming a passivation film covering the insulating film and the first and second wiring layers, and forming the passivation film after the patterning. Before or after the formation, the MOS transistor is subjected to a heat treatment in an atmosphere containing hydrogen in order to recover process damage.

In the method of manufacturing the second semiconductor device according to the present invention, the second wiring layer is omitted and the first wiring layer is formed by MO.
It may be formed so as to overlap the gate portion of the S-type transistor.

According to the second semiconductor device manufacturing method of the present invention, the titanium layer as the lower layer of the barrier conductive layer is entirely converted into the titanium silicide layer including the inside and the outside of the connection hole. Therefore, in the hydrogen annealing treatment, hydrogen absorption by titanium does not occur at all, and the process damage can be sufficiently recovered.

[0018]

1 to 7 show a method of manufacturing a semiconductor device according to the present invention, and steps (1) to (7) corresponding to the respective drawings will be sequentially described.

(1) The surface of a P-type semiconductor substrate 10 made of, for example, silicon is selectively oxidized to form a field insulating film 12 made of silicon oxide. The insulating film 12 has an element hole 12A. An N channel MOS type transistor T is formed in the element hole 12A. Transistor T
Is an LDD structure similar to that described in FIG.
The same parts as those in FIG. 18 are designated by the same reference numerals, and detailed description thereof will be omitted.

Next, an interlayer insulating film 14 is formed on the insulating film 12 so as to cover the transistor T. The insulating film 14 is, for example, BPSG (boron.
CVD (Chemical Vapor)
It is formed by a deposition method or the like. And the insulating film 1
A poly-Si (silicon) layer 15 is formed on the surface 4 by a sputtering method or the like. As the thickness of the poly-Si layer 15, a thickness sufficient to silicify a Ti layer described later is selected,
For example, it is set to 20 nm.

(2) Source and drain connection holes 14S and 14D are formed in the lamination of the insulating film 14 and the poly-Si layer 15 by well-known photolithography and dry etching.
To form

(3) Connection holes 14S, 14D and poly-Si
A conductive material layer 16 is formed over the layer 15. Conductive material layer 16
The Ti layer (16a in FIG. 8) and the TiN layer (FIG. 8)
16b) are sequentially formed by the sputtering method. The thicknesses of the Ti layer and the TiN layer are, for example, 10 nm and 1 respectively.
It can be 00 nm. The Ti layer serves to reduce contact resistance, and the TiN layer serves as a barrier conductive layer. TiON instead of TiN layer
Layers may be used.

(4) By reacting the poly-Si layer 15 with the Ti layer in the conductive material layer 16, titanium silicide (T
iSi _x: to form x = 1~2) layer 15A. For silicidation, for example, a lamp annealing treatment at 600 ° C. for 60 seconds can be performed. As a result of the silicidation process, a titanium silicide layer 15A is obtained as shown in the enlarged view of the drain portion in FIG. 8, while T is formed in the connection hole 14D.
The i layer 16a and the TiN layer 16b are left stacked, and the TiN layer 16b is left on the silicide layer 15A.
The Ti layer and TiN layer 1 similar to 16a are also formed in the connection hole 14S.
Although the stack with 6b is left, the illustration is omitted. Connection hole 1
Ti layers such as 16a in 4S and 14D and connection holes 14S and
The titanium silicide layer 15A outside 14D and these Ti
A layer including the layer and the TiN layer 16b covering the layer 15A is referred to as a conductive material layer 16 ′.

[0024] In the same manner also in a part of the source region S with TiSi _x layer 15D reacts with the substrate silicon and the Ti layer 16a is a silicidation process in this case a part of the drain region D are formed TiSi _x The layer 15S is formed.

Next, a conductive material layer 17 is formed so as to cover the connection holes 14S and 14D and the conductive material layer 16 '. Conductive material layer 17
As shown in FIG. 8, an Al alloy (Al-Si-C
u) The layer 17a and the TiN layer 17b are sequentially formed by the sputtering method. As an example, the thicknesses of the Al alloy layer 17a and the TiN layer 17b can be 400 nm and 40 nm, respectively. The Al alloy layer 17a is a main component of wiring, and the TiN layer 17b is for preventing light reflection during photolithography. A TiON layer may be used instead of the TiN layer 17b. The wiring material layer 18 is formed by stacking the conductive material layer 16 ′ and the conductive material layer 17.

(5) The wiring material layer 18 is patterned by photolithography and dry etching to form the wiring layer 18Q, the source wiring layer 18S, and the drain wiring layer 18D, which are all the wiring material layer 18.
The dry etching is performed by using a gas flow rate of Cl ₂ / BC as an example.
It can be performed under the conditions of l ₃ = 30/30 sccm and a pressure of 10 mTorr. Wiring layers 18Q, 18S, 18D
The plane pattern of can be the pattern shown in FIG. 9 as an example. FIG. 5 corresponds to a cross section taken along line XX ′ of FIG. In FIG. 9, SC, DC and GC indicate a source contact portion, a drain contact portion and a gate contact portion, respectively. The wiring layer 18Q relates to a circuit element different from the transistor T, and includes the wiring layers 18S, 1
It is formed so as to be separated from 8D and overlap the gate portion T _G of the transistor T.

Next, the substrate of FIG. 5 is inserted into the processing chamber of the annealing device, and the transistor T is subjected to hydrogen annealing.
The hydrogen annealing treatment at this time can be performed under the conditions of 400 to 450 ° C. for 30 minutes in an atmosphere containing hydrogen and nitrogen.

(6) Wiring layers 18Q, 1 on the insulating film 14
An interlayer insulating film 19 is formed so as to cover 8S and 18D. The insulating film 19 is formed by the following method as an example. That is, 50 by the plasma CVD method using TEOS.
After forming the silicon oxide film 19a having a thickness of 0 nm, the SOG (spin spin film) having a thickness of 500 nm is formed on the film 19a.
On glass) film 19b is formed, and film 19b is formed to 500n.
The film 19a and the remaining S are etched back by a thickness of m.
Plasma CVD using TEOS to cover the OG film 19b
The silicon oxide film 19 with a thickness of 500 nm by
Form c. The etching back of the film 19b can be omitted.

(7) After forming desired connection holes in the insulating film 19, the wiring layer 20 is formed on the insulating film 19. And
A passivation film 22 is formed on the insulating film 19 so as to cover the wiring layer 20. As the passivation film 20,
As an example, a 1000-nm-thick silicon nitride film can be formed by a plasma CVD method.

According to the manufacturing method described above with reference to FIGS.
Since the Ti layer below the TiN layer 16b is converted into the titanium silicide layer 15A in the portions other than the connection holes 14S and 14D,
The Ti layer exists only inside the connection holes 14A and 14D. Therefore, in the hydrogen annealing treatment of FIG. 5, hydrogen absorption due to Ti is suppressed, and the process damage can be sufficiently recovered.

10 to 13 show a method of manufacturing a semiconductor device according to another embodiment of the present invention.

In the step of FIG. 10, the insulating film 12, the transistor T, and the insulating film 12 are formed on the surface of the semiconductor substrate 10 in the same manner as described above.
After forming the insulating film 14 and the like, the connection hole 14 is formed in the insulating film 14 by well-known photolithography and dry etching.
S, 14D are formed. Then, the conductive material layer 24 is formed on the insulating film 14 so as to cover the connection holes 14S and 14D.

As an example of the conductive material layer 24, FIG.
As shown in the enlarged view of the drain part, a poly-Si layer 24a having a thickness of 20 nm and a Ti layer 24b having a thickness of 10 nm and 1
A TiN layer 24c having a thickness of 00 nm is sequentially formed by a sputtering method.

Next, in the step of FIG. 11, the poly-Si layer 24a is subjected to the lamp annealing treatment in the same manner as described in FIG.
And the Ti layer 24b are reacted with each other to form a titanium silicide layer 24A as shown in FIG. In this case, connection hole 1
The silicidation also progresses inside 4S and 14D. The silicide layer 24A and the TiN layer 24c are stacked to form the conductive material layer 2
4 '.

Next, the conductive material layer 24 'is covered to cover the conductive material layer 2'.
6 is formed. The conductive material layer 36 is, for example, 40
0 nm thick Al alloy (Al-Si-Cu) layer and 40
A TiN layer having a thickness of nm is sequentially formed by the sputtering method. A wiring material layer 27 is a stack of the conductive material layer 24 ′ and the conductive material layer 26.

In the process of FIG. 12, the wiring material layer 27 is patterned in the same manner as described with reference to FIG. 5 to form the wiring layer 27Q, the source wiring layer 27S and the drain wiring layer 27D. Then, the hydrogen annealing process is performed on the transistor T in the same manner as described with reference to FIG.

Next, in the step of FIG. 13, the wiring layers 27Q, 27S, 2 are formed on the insulating film 14 in the same manner as described in FIGS.
The insulating film 1 is formed while covering the 7D and the interlayer insulating film 19 is formed.
A passivation film 22 is formed on the wiring 9 via the wiring layer 20.

According to the manufacturing method described above with reference to FIGS. 10 to 15, the Ti layer below the TiN layer 24c is formed into the connection holes 14S and 14S.
Since it was converted to the titanium silicide layer 24A inside and outside D,
The Ti layer is no longer present. Therefore, in the hydrogen annealing treatment of FIG. 12, hydrogen absorption by Ti is eradicated, and the process damage can be sufficiently recovered.

FIG. 16 shows a MOS transistor according to still another embodiment of the present invention, which is indicated by Y- in FIG.
It corresponds to the cross section along the line Y '. In FIGS. 16 and 17,
1 to 9 are denoted by the same reference numerals and detailed description thereof will be omitted.

The feature of the embodiment of FIGS. 16 and 17 is that the wiring layer 18Q is eliminated and the source wiring layer 18S and the drain wiring layer 18D are replaced by the gate portion T _{G of the} transistor T.
It has been placed on top of. As the lower layers of the wiring layers 18S and 18D, the Ti layer inside the contact hole, the titanium silicide layer outside the contact hole, and the T layer covering these layers, as in FIG.
A conductive material layer 16 'including an iN layer is provided, and the same hydrogen annealing treatment as described in FIG. 5 is performed. In this case, instead of the conductive material layer 16 ', a conductive material layer 27' as described in FIG. 11 may be provided. In any case, the hydrogen storage amount in the vicinity of the transistor T can be significantly reduced, and the process damage can be sufficiently recovered.

The present invention is not limited to the above-described embodiment, but can be implemented in various modified forms. For example, the following changes are possible.

(1) The present invention can be applied not only when there are a plurality of layers of wiring above the insulating film 14, but also when there is only one layer of wiring.

(2) The hydrogen annealing treatment is performed before the passivation film 22 is formed. However, if the passivation film is a hydrogen permeable film such as PSG, the hydrogen annealing treatment is performed after the passivation film is formed. Good. Even when the passivation film is a plasma nitride film (silicon nitride film formed by a plasma CVD method), hydrogen annealing treatment can be performed after the passivation film is formed. In this case, hydrogen annealing can be used to desorb hydrogen from the plasma nitride film, and hydrogen will not be absorbed in the lower layer of the barrier conductive layer.

[0044]

As described above, according to the present invention, the titanium layer is partially or wholly converted into the titanium silicide layer prior to the hydrogen annealing treatment. Is suppressed or eradicated, and the effect that the process damage can be sufficiently recovered can be obtained.

[Brief description of drawings]

FIG. 1 is a substrate cross-sectional view showing a poly-Si layer forming step in a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a substrate cross-sectional view showing a connection hole forming step that follows the step of FIG.

FIG. 3 is a substrate cross-sectional view showing a conductive material layer forming step following the step of FIG.

4 is a substrate cross-sectional view showing a silicidation process and a conductive material layer formation process following the process of FIG.

5 is a substrate cross-sectional view showing a wiring patterning step and a hydrogen annealing step that follow the step of FIG.

6 is a substrate cross-sectional view showing an interlayer insulating film formation step following the step of FIG.

7 is a substrate cross-sectional view showing a wiring forming step and a passivation film forming step following the step of FIG.

FIG. 8 is an enlarged cross-sectional view of a drain portion for explaining the process of FIG. 4 in detail.

FIG. 9 is a plan view showing a wiring arrangement of the transistor of FIG.

FIG. 10 is a substrate cross-sectional view showing a conductive material layer forming step in a method for manufacturing a semiconductor device according to another embodiment of the present invention.

11 is a substrate cross-sectional view showing a silicidation process and a conductive material layer formation process following the process of FIG.

12 is a substrate cross-sectional view showing a wiring patterning process that follows the process of FIG.

13 is a step of forming an interlayer insulating film following the step of FIG. 12;
It is a board sectional view showing a wiring formation process and a passivation film formation process.

FIG. 14 is an enlarged cross-sectional view of a drain portion showing details of deposition of a conductive material in the process of FIG.

FIG. 15 is an enlarged cross-sectional view of a drain portion showing a silicidation state in the process of FIG.

FIG. 16 is a MOS according to still another embodiment of the present invention.
It is sectional drawing which shows a type transistor.

17 is a plan view showing a source wiring layer and a drain wiring layer of the transistor of FIG.

FIG. 18 is a cross-sectional view of a substrate showing a conventional MOS transistor.

FIG. 19 is a cross-sectional view of a substrate for explaining problems in a conventional hydrogen annealing process.

[Explanation of symbols]

10: semiconductor substrate, 12, 14, 19: insulating film, 15:
Poly-Si layer, 15A, 24A: Titanium silicide layer, 1
6, 17, 24, 26: conductive material layer, 18, 27: wiring material layer, 18Q, 27Q: wiring layer, 18S, 27S: source wiring layer, 18D, 27D: drain wiring layer, 22: passivation film, T: MOS type transistor.

Claims (4)

[Claims] 1. A step of forming a MOS transistor on a surface of a semiconductor substrate, a step of forming an insulating film on the surface of the semiconductor substrate so as to cover the MOS transistor, and a polysilicon layer on the insulating film. The step of forming, and the MOS on the stack of the insulating film and the polysilicon layer.
Forming a connection hole leading to the transistor, forming a titanium layer and a barrier conductive layer in order from the bottom to cover the connection hole and the polysilicon layer, and react the polysilicon layer and the titanium layer. Forming a titanium silicide layer by forming a titanium silicide layer, forming a titanium silicide layer, and then forming a conductive material layer covering the connection hole and the barrier conductive layer, and the titanium silicide layer and the barrier conductive layer. A step of patterning a wiring material layer including the conductive material layer to form a first wiring layer and a second wiring layer, each of which is composed of the wiring material layer, and is connected to the MOS transistor through the connection hole. The first wiring layer is formed on the first wiring layer, and the second wiring layer is formed so as to be separated from the first wiring layer and overlap the gate portion of the MOS transistor. A step of forming a passivation film to cover the insulating film and the first and second wiring layers, and a step of forming the passivation film after the patterning or before or after the passivation film is formed in the MOS transistor. A method of manufacturing a semiconductor device, including a step of performing heat treatment in an atmosphere containing hydrogen to recover damage. 2. A step of forming a MOS transistor on a surface of a semiconductor substrate, a step of forming an insulating film on the surface of the semiconductor substrate so as to cover the MOS transistor, and a polysilicon layer on the insulating film. The step of forming, and the MOS on the stack of the insulating film and the polysilicon layer.
Forming a connection hole leading to the transistor, forming a titanium layer and a barrier conductive layer in order from the bottom to cover the connection hole and the polysilicon layer, and react the polysilicon layer and the titanium layer. Forming a titanium silicide layer by forming a titanium silicide layer, forming a titanium silicide layer and then forming a conductive material layer covering the connection hole and the barrier conductive layer, and the titanium silicide layer and the barrier conductive layer. A step of patterning a wiring material layer including the conductive material layer to form a wiring layer composed of the wiring material layer, wherein the wiring layer is connected to the MOS type transistor through the connection hole and
Forming the wiring layer so as to overlap the gate portion of the OS transistor, forming a passivation film covering the insulating film and the wiring layer, and after forming the passivation film, or And a step of performing heat treatment on the MOS type transistor in an atmosphere containing hydrogen to recover the process damage after the formation of the semiconductor device. 3. A step of forming a MOS type transistor on the surface of a semiconductor substrate, a step of forming an insulating film on the surface of the semiconductor substrate to cover the MOS type transistor, and a step of connecting the insulating film to the MOS type transistor. Forming a contact hole; forming a polysilicon layer, a titanium layer and a barrier conductive layer in order from the bottom to cover the contact hole and the insulating film; reacting the polysilicon layer with the titanium layer; Forming a titanium silicide layer by forming a titanium silicide layer, forming a titanium silicide layer and then forming a conductive material layer covering the connection hole and the barrier conductive layer, and the titanium silicide layer and the barrier conductive layer. A step of patterning a wiring material layer including the conductive material layer to form first and second wiring layers each comprising the wiring material layer; The first wiring layer is formed so as to be connected to the MOS type transistor via the first wiring layer and the second wiring layer is formed so as to be separated from the first wiring layer and overlap the gate portion of the MOS type transistor. And a step of forming a passivation film covering the insulating film and the first and second wiring layers, and a step of forming the passivation film after the patterning or before or after forming the passivation film. A method of manufacturing a semiconductor device, including a step of performing heat treatment in an atmosphere containing hydrogen to recover damage. 4. A step of forming a MOS transistor on the surface of a semiconductor substrate, a step of forming an insulating film on the surface of the semiconductor substrate so as to cover the MOS transistor, and a step of connecting the insulating film to the MOS transistor. Forming a contact hole; forming a polysilicon layer, a titanium layer and a barrier conductive layer in order from the bottom to cover the contact hole and the insulating film; reacting the polysilicon layer with the titanium layer; Forming a titanium silicide layer by forming a titanium silicide layer, forming a titanium silicide layer and then forming a conductive material layer covering the connection hole and the barrier conductive layer, and the titanium silicide layer and the barrier conductive layer. A step of patterning a wiring material layer including the conductive material layer to form a wiring layer composed of the wiring material layer, wherein the MO layer is formed through the connection hole. And the M lead to type transistor
Forming the wiring layer so as to overlap the gate portion of the OS transistor, forming a passivation film covering the insulating film and the wiring layer, and after forming the passivation film, or And a step of performing heat treatment on the MOS type transistor in an atmosphere containing hydrogen to recover the process damage after the formation of the semiconductor device.