JP2976931B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2976931B2
JP2976931B2 JP9146478A JP14647897A JP2976931B2 JP 2976931 B2 JP2976931 B2 JP 2976931B2 JP 9146478 A JP9146478 A JP 9146478A JP 14647897 A JP14647897 A JP 14647897A JP 2976931 B2 JP2976931 B2 JP 2976931B2
Authority
JP
Japan
Prior art keywords
film
semiconductor device
plasma
insulating film
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP9146478A
Other languages
Japanese (ja)
Other versions
JPH10335657A (en
Inventor
直彦 君塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP9146478A priority Critical patent/JP2976931B2/en
Priority to KR1019980020614A priority patent/KR19990006655A/en
Publication of JPH10335657A publication Critical patent/JPH10335657A/en
Application granted granted Critical
Publication of JP2976931B2 publication Critical patent/JP2976931B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02115Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、MOSFET(メ
タル−オキサイド−シリコン電界効果型トランジスタ)
等の製造方法に関し、特にプラズマ工程により受けるダ
メージをアニールにより低減する方法に関する。
The present invention relates to a MOSFET (metal-oxide-silicon field-effect transistor).
In particular, the present invention relates to a method for reducing damage caused by a plasma process by annealing.

【0002】[0002]

【従来の技術】従来より微細MOS・LSI製造プロセ
スにおいて金属配線材料をパターニングする工程では、
垂直加工性に優れることから反応性イオンエッチングが
通常用いられている。また、配線層間の絶縁膜の成膜に
は、埋め込み性に優れることから高密度プラズマ酸化膜
が用いられている。しかし、反応性イオンエッチング工
程またはプラズマ酸化膜の成膜工程中に、半導体基板は
プラズマ雰囲気に曝されることになる。このとき、ゲー
ト電極に接続された配線がプラズマに対する一種のアン
テナとして作用してMOSFETに電荷が蓄積され、ゲ
ート絶縁膜が劣化したり、ゲート絶縁膜の界面準位が増
加する現象(以下、プラズマダメージという。)が起き
る。そこで、ゲート絶縁膜に加えられたダメージを緩和
させるために、従来より、この配線層の形成後、半導体
装置の最終製造工程において、水素ガス雰囲気中で半導
体基板を加熱する水素アニール処理が行われている。
2. Description of the Related Art Conventionally, in the process of patterning a metal wiring material in a fine MOS / LSI manufacturing process,
Reactive ion etching is usually used because of its excellent vertical workability. In addition, a high-density plasma oxide film is used for forming an insulating film between wiring layers because of its excellent embedding property. However, the semiconductor substrate is exposed to a plasma atmosphere during the reactive ion etching process or the plasma oxide film forming process. At this time, the wiring connected to the gate electrode acts as a kind of antenna for the plasma, and charges are accumulated in the MOSFET, thereby deteriorating the gate insulating film or increasing the interface state of the gate insulating film (hereinafter, referred to as plasma). Damage). Therefore, in order to alleviate the damage applied to the gate insulating film, conventionally, after the formation of the wiring layer, a hydrogen annealing process for heating the semiconductor substrate in a hydrogen gas atmosphere is performed in a final manufacturing process of the semiconductor device. ing.

【0003】しかしながら、通常配線層の下層や上層に
用いられるチタン等のバリア層は、水素を吸収する性質
を有するので、バリア層がMOSFETを覆うように存
在する場合、水素アニールによりプラズマダメージが除
去される効果が十分に得られないという問題が生じる。
例えば、S・Hirade等は1995年のVMIC
(proceeding P376)において、MOS
FETのゲート電極の直上に大面積の配線材が存在する
場合、配線材下部にバリアメタルとして存在するチタン
膜が水素を吸収し、十分なプラズマダメージの除去が行
えないことを報告している。
However, a barrier layer such as titanium, which is usually used as a lower layer or an upper layer of a wiring layer, has a property of absorbing hydrogen. Therefore, when a barrier layer exists so as to cover a MOSFET, plasma damage is removed by hydrogen annealing. However, there arises a problem that the effect obtained is not sufficiently obtained.
For example, S. Hirade et al.
(Processed P376)
It has been reported that when a large-area wiring material is present immediately above a gate electrode of a FET, a titanium film existing as a barrier metal below the wiring material absorbs hydrogen and cannot sufficiently remove plasma damage.

【0004】例えば通常の半導体装置が具備する入出力
バッファー回路では、電源供給ラインには他の部分より
線幅の広い配線が通常用いられる。この場合、従来の方
法ではその電源ラインの直下に存在するMOSFETの
ゲート絶縁膜近傍まで水素が拡散しないことがあり、プ
ラズマダメージの除去が不十分になり、所望の特性を有
するMOSFETを得ることができなくなる。
[0004] For example, in an input / output buffer circuit provided in a normal semiconductor device, a wiring having a line width wider than other parts is usually used for a power supply line. In this case, in the conventional method, hydrogen may not diffuse to the vicinity of the gate insulating film of the MOSFET located immediately below the power supply line, and the plasma damage may not be sufficiently removed, and a MOSFET having desired characteristics may be obtained. become unable.

【0005】また近年になり配線間容量を低減させて回
路遅延時間を抑えることを目的として、層間絶縁膜に低
誘電率膜を適用することが試みられている。しかし、こ
の低誘電率膜は、一般に有機分子より合成される膜であ
るために耐熱性が悪く、従来の400〜500℃の処理
温度で水素アニール処理を行うことが不可能である。例
えばフッ化アモルファスカーボンを層間絶縁膜に適用し
た場合、300℃以上に加熱するとアモルファスカーボ
ン膜が分解してフッ化カーボン系のガスに気化すること
がEndo等によって報告されている(Appl・Ph
ys・Lett・68(20),13May199
6)。従って、このような耐熱性の悪い層間絶縁膜を用
いる場合には、従来より低温でありながら十分にプラズ
マダメージを除去する方法が求められていた。
In recent years, an attempt has been made to apply a low dielectric constant film to an interlayer insulating film for the purpose of suppressing the circuit delay time by reducing the capacitance between wirings. However, since this low dielectric constant film is generally a film synthesized from organic molecules, it has poor heat resistance, and it is impossible to perform hydrogen annealing at a conventional processing temperature of 400 to 500 ° C. For example, it has been reported by Endo and others that when fluorinated amorphous carbon is applied to an interlayer insulating film, the amorphous carbon film is decomposed and vaporized into a carbon fluoride-based gas when heated to 300 ° C. or more (Appl.Ph).
ys ・ Lett ・ 68 (20) 、 13May199
6). Therefore, when such an interlayer insulating film having poor heat resistance is used, a method of sufficiently removing plasma damage at a lower temperature than in the past has been required.

【0006】特開昭57−118635号公報には、従
来の水素ガスの代わりにプラズマ発生装置より発生させ
た水素イオンを用いてアニールする方法が記載されてい
る。この公報によれば、基板温度を比較的低い温度に設
定しても水素アニール効果が現れるとしている。しかし
ながら、この方法では、高周波電力により発生させた水
素イオンを用いることから、この工程で新たにプラズマ
ダメージを発生させる場合があり、その結果十分なダメ
ージ除去が行えない問題があった。
Japanese Patent Application Laid-Open No. 57-118635 describes a method of annealing using hydrogen ions generated by a plasma generator instead of a conventional hydrogen gas. According to this publication, even if the substrate temperature is set to a relatively low temperature, the hydrogen annealing effect is exhibited. However, in this method, since hydrogen ions generated by high-frequency power are used, plasma damage may be newly generated in this step, and as a result, there has been a problem that sufficient damage cannot be removed.

【0007】一方、特開平2−177542号公報に
は、シリコンウェハを水素雰囲気中加圧下でアニールす
ることにより、シリコンウェハ表面に形成される酸化膜
の耐圧特性を向上させる方法が記載されている。しかし
ながら、この方法は酸化膜形成時の熱誘起結晶欠陥を減
少させることを目的として、酸化膜形成前に加圧水素ア
ニールを行うものである。従って、ゲート酸化膜を形成
し、層間絶縁膜や配線まで形成した後にプラズマダメー
ジを減少させる方法は、依然としてまったく知られてい
なかったのである。
On the other hand, Japanese Patent Application Laid-Open No. Hei 2-177542 describes a method for improving the breakdown voltage characteristics of an oxide film formed on the surface of a silicon wafer by annealing the silicon wafer under pressure in a hydrogen atmosphere. . However, in this method, pressurized hydrogen annealing is performed before forming an oxide film for the purpose of reducing thermally induced crystal defects at the time of forming an oxide film. Therefore, a method of reducing plasma damage after forming a gate oxide film and forming an interlayer insulating film and wiring has not been known at all.

【0008】[0008]

【発明が解決しようとする課題】本発明は、上記の問題
点に鑑みてなされたものであり、MOSFET等の半導
体装置において、金属配線層下部に、チタン膜あるいは
窒化チタン膜のような水素を吸収する物質でバリア層が
設けられ、それが絶縁膜の直上に大面積で存在する場合
でも、十分にプラズマダメージを除去し、MOSFET
の特性および信頼性を向上する半導体装置の製造方法を
提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems. In a semiconductor device such as a MOSFET, hydrogen such as a titanium film or a titanium nitride film is formed under a metal wiring layer. Even if a barrier layer is provided with a substance to be absorbed and exists in a large area immediately above the insulating film, the plasma damage is sufficiently removed and the MOSFET is removed.
It is an object of the present invention to provide a method of manufacturing a semiconductor device which improves characteristics and reliability of the semiconductor device.

【0009】また、本発明は、従来より低いアニール温
度を用いても十分にプラズマダメージを除去しうる半導
体装置の製造方法を提供することを目的とする。
Another object of the present invention is to provide a method of manufacturing a semiconductor device which can sufficiently remove plasma damage even when an annealing temperature lower than that of the related art is used.

【0010】[0010]

【課題を解決するための手段】本発明は、製造工程中に
少なくとも1回のプラズマを用いる工程を有する製造工
程により、ゲート絶縁膜、電極、金属配線および層間絶
縁膜を形成した半導体基板を、加圧水素雰囲気中で加熱
することを特徴とする半導体装置の製造方法に関する。
According to the present invention, a semiconductor substrate on which a gate insulating film, an electrode, a metal wiring, and an interlayer insulating film are formed by a manufacturing process including at least one process using plasma during the manufacturing process is provided. The present invention relates to a method for manufacturing a semiconductor device, characterized by heating in a pressurized hydrogen atmosphere.

【0011】[0011]

【発明の実施の形態】本発明では、半導体基板表面に、
ゲート絶縁膜、電極、金属配線および層間絶縁膜を形成
した後に、これらの工程中に受けたプラズマダメージを
除去するために加圧水素雰囲気中で水素アニールを行う
ものである。従って、加圧水素雰囲気中で加熱する工程
は、なるべく半導体製造の最終工程に近い工程で行うの
が好ましい。また、その半導体基板上には、ゲート絶縁
膜、電極、金属配線および層間絶縁膜の他に必要に応じ
てその他の層が形成されていてもよい。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a semiconductor substrate has
After forming a gate insulating film, an electrode, a metal wiring, and an interlayer insulating film, hydrogen annealing is performed in a pressurized hydrogen atmosphere in order to remove plasma damage received during these steps. Therefore, the step of heating in a pressurized hydrogen atmosphere is preferably performed as close as possible to the final step of semiconductor manufacturing. Further, on the semiconductor substrate, other layers may be formed as necessary in addition to the gate insulating film, the electrodes, the metal wirings, and the interlayer insulating films.

【0012】本発明では、水素アニールを加圧水素雰囲
気、好ましくは0.5MPa以上の加圧水素雰囲気で行
うことにより、従来より多量の水素を層間絶縁膜中およ
び半導体基板に供給する。この結果、線幅が広く、下層
および/または上層にチタン等の水素吸収性の材料を有
する配線の直下にMOSFETが存在する場合において
もプラズマダメージを除去することができる。但し、あ
まりに水素分圧を上げると爆発等の危険性があるので、
通常は例えば5MPa程度以下で行うことが好ましい。
水素ガスは適当な不活性ガスで希釈されていてもよい。
In the present invention, a larger amount of hydrogen is supplied into the interlayer insulating film and to the semiconductor substrate than in the prior art by performing hydrogen annealing in a pressurized hydrogen atmosphere, preferably in a pressurized hydrogen atmosphere of 0.5 MPa or more. As a result, plasma damage can be removed even in the case where the MOSFET is present immediately below a wiring having a wide line width and having a hydrogen absorbing material such as titanium in the lower layer and / or the upper layer. However, if the hydrogen partial pressure is too high, there is a danger of explosion, etc.
Usually, for example, it is preferable to carry out at about 5 MPa or less.
Hydrogen gas may be diluted with a suitable inert gas.

【0013】金属配線は、必要に応じてその下層および
/または上層に高融点金属または高融点金属の窒化物か
らなる膜を設けてもよい。このような材料は、通常水素
吸収性であるが、本発明はこのような材料を金属配線の
下層および/または上層に設けた場合に特に大きな効果
を発揮しうるものである。高融点金属または高融点金属
の窒化物としては、チタンおよび窒化チタン等を挙げる
ことができる。
The metal wiring may be provided with a film made of a high melting point metal or a nitride of a high melting point metal as a lower layer and / or an upper layer as necessary. Such a material is generally hydrogen-absorbing, but the present invention can exert a particularly great effect when such a material is provided in a lower layer and / or an upper layer of a metal wiring. Examples of the high melting point metal or the nitride of the high melting point metal include titanium and titanium nitride.

【0014】また、通常水素アニールの処理温度を低温
化すると、層間膜中の水素の拡散係数が低下し、ゲート
絶縁膜近傍まで水素を拡散しにくくなる。しかし本発明
においては、層間膜表面近傍の水素分圧を上げるので、
低温化しても拡散速度を高くすることで、水素を十分に
拡散させることができる。従って、処理温度を低温化し
てもプラズマダメージの除去ができる。
Further, when the processing temperature of the normal hydrogen annealing is lowered, the diffusion coefficient of hydrogen in the interlayer film decreases, and it becomes difficult to diffuse hydrogen to the vicinity of the gate insulating film. However, in the present invention, since the hydrogen partial pressure near the interlayer film surface is increased,
By increasing the diffusion rate even at low temperatures, hydrogen can be sufficiently diffused. Therefore, even if the processing temperature is lowered, plasma damage can be removed.

【0015】また本発明ではプラズマが存在しない雰囲
気で水素アニール処理を行うので新たなダメージを加え
ることなく、十分なプラズマダメージ除去効果が得られ
る。
In the present invention, since the hydrogen annealing treatment is performed in an atmosphere in which no plasma exists, a sufficient plasma damage removing effect can be obtained without adding new damage.

【0016】[0016]

【実施例】【Example】

[実施例1]次に本発明の実施例について図面を参照し
て説明する。
Embodiment 1 Next, an embodiment of the present invention will be described with reference to the drawings.

【0017】図1〜図4は本実施例の半導体装置の製造
方法を説明する図である。本実施例では第2層目の金属
配線11が入出力バッファー回路への電源供給用に用い
られており、通常の線幅より広く、かつMOSFETを
覆うように配置されている。図1がその平面図であり、
図2は、図1中のA−B間の断面図を示したものであ
る。
1 to 4 are views for explaining a method of manufacturing a semiconductor device according to the present embodiment. In the present embodiment, the second-layer metal wiring 11 is used for supplying power to the input / output buffer circuit, and is arranged so as to be wider than a normal line width and to cover the MOSFET. FIG. 1 is a plan view thereof,
FIG. 2 is a cross-sectional view taken along a line AB in FIG.

【0018】図2に示すように、シリコン基板1上に素
子分離膜2、ソース電極14、ドレイン電極15、ゲー
ト絶縁膜30およびゲート電極16が設けられており、
さらにその上を、プラズマCVD法により成膜された7
00nm厚のプラズマ酸化シリコン膜3が層間絶縁膜と
して形成されている。
As shown in FIG. 2, an element isolation film 2, a source electrode 14, a drain electrode 15, a gate insulating film 30, and a gate electrode 16 are provided on a silicon substrate 1.
Further, a film 7 was formed thereon by a plasma CVD method.
A plasma silicon oxide film 3 having a thickness of 00 nm is formed as an interlayer insulating film.

【0019】このプラズマシリコン酸化膜3は所定位置
にソース電極14およびドレイン電極15に達する開孔
が設けられており、この開孔を通してソース電極14お
よびドレイン電極15とコンタクトをとるタングステン
プラグ4が設けられ、このタングステンプラグに第1層
金属配線31が接続されている。第1層金属配線はチタ
ン膜5/窒化チタン膜6/アルミ・銅合金膜7/窒化チ
タン膜8の積層膜で構成されており、それぞれの膜厚は
60nm/100nm/500nm/100nmであ
る。尚、ソース電極14およびドレイン電極15とのコ
ンタクト面は、シリサイド化しチタンシリサイド膜17
が形成されている。
An opening reaching the source electrode 14 and the drain electrode 15 is provided at a predetermined position in the plasma silicon oxide film 3, and a tungsten plug 4 for making contact with the source electrode 14 and the drain electrode 15 is provided through the opening. The first layer metal wiring 31 is connected to the tungsten plug. The first layer metal wiring is composed of a laminated film of titanium film 5 / titanium nitride film 6 / aluminum / copper alloy film 7 / titanium nitride film 8, and their thickness is 60 nm / 100 nm / 500 nm / 100 nm. The contact surface between the source electrode 14 and the drain electrode 15 is silicidized to form a titanium silicide film 17.
Are formed.

【0020】この第1層金属配線の上を覆ってプラズマ
CVD法により成膜された500nm厚のプラズマ酸化
シリコン膜13が層間絶縁膜として形成され、その上に
第2層金属配線32が設けられている。第2層金属配線
も同様に、チタン膜9/窒化チタン膜10/アルミ・銅
合金膜11/窒化チタン膜12の積層膜で構成されてお
り、それぞれの膜厚は60nm/100nm/500n
m/100nmである。第2層金属配線32の線幅は1
0μmと広く、図1に示すように、MOSFETを大き
く覆っている。
A 500 nm-thick plasma silicon oxide film 13 formed by a plasma CVD method is formed as an interlayer insulating film over the first layer metal wiring, and a second layer metal wiring 32 is provided thereon. ing. Similarly, the second-layer metal wiring is also composed of a laminated film of titanium film 9 / titanium nitride film 10 / aluminum / copper alloy film 11 / titanium nitride film 12, each having a thickness of 60 nm / 100 nm / 500 n.
m / 100 nm. The line width of the second-layer metal wiring 32 is 1
It is as wide as 0 μm, and largely covers the MOSFET as shown in FIG.

【0021】このように形成された基板をアニールする
には次のように行う。
The annealing of the substrate thus formed is performed as follows.

【0022】図2の第2層金属配線までが形成された基
板上に、図3に示すように膜厚400nmのプラズマ酸
化シリコン膜18を成膜し、引き続き1MPaの加圧水
素ガス雰囲気中に導入し、400℃で20分間加熱して
アニールした。
As shown in FIG. 3, a 400 nm-thick plasma silicon oxide film 18 is formed on the substrate on which the metal wiring up to the second layer in FIG. 2 is formed, and then introduced into a 1 MPa pressurized hydrogen gas atmosphere. Then, it was annealed by heating at 400 ° C. for 20 minutes.

【0023】次に図4に示すように膜厚300nmのプ
ラズマ窒化酸化シリコン膜19を成膜する。プラズマ窒
化酸化シリコン膜19を成膜する工程において配線層は
全て絶縁膜で覆われており、MOSFETは成膜雰囲気
に存在するプラズマによるダメージを受けない。
Next, as shown in FIG. 4, a plasma silicon nitride oxide film 19 having a thickness of 300 nm is formed. In the step of forming the plasma silicon oxynitride film 19, the entire wiring layer is covered with the insulating film, and the MOSFET is not damaged by plasma existing in the film formation atmosphere.

【0024】この工程の後、カバー膜の成膜およびボン
ディングパッドの開口、組み立てを行うことにより所望
の半導体装置を得た。
After this step, a desired semiconductor device was obtained by forming a cover film, opening bonding pads, and assembling.

【0025】この実施例では、第2層金属配線の線幅が
広くしかも金属配線の下層にチタンおよび窒化チタンの
層が設けられているため、従来の水素アニールでは、層
間絶縁膜形成時に発生したプラズマダメージを十分に除
去することができなかったが、本実施例では、多量の水
素を層間膜中に拡散させることができプラズマダメージ
を除去することができた。
In this embodiment, since the line width of the second-layer metal wiring is wide and a layer of titanium and titanium nitride is provided below the metal wiring, the conventional hydrogen anneal occurs during the formation of an interlayer insulating film. Although plasma damage could not be sufficiently removed, in the present example, a large amount of hydrogen could be diffused into the interlayer film and plasma damage could be removed.

【0026】[実施例2]この実施例では、まず図5
(a)に示すようにシリコン基板1上に素子分離膜2、
ソース電極14、ドレイン電極15、ゲート絶縁膜30
およびゲート電極16を形成し、次に層間絶縁膜として
プラズマ酸化シリコン膜3を成膜し、引き続きリソグラ
フイーおよびエッチング技術を用いてコンタクトホール
を開孔した。次に、図5(b)に示すようにチタンおよ
び窒化チタンをスパッタした後、タングステンプラグ4
をコンタクトホール開孔に埋め込み、続いて金属配線材
をスパッタし、フォトリソグラフイーおよびエッチング
技術を用いたパターニングにより第1層金属配線31を
形成した。第1層金属配線は実施例1と同じ4層構造よ
りなるが図示は省略した。
[Embodiment 2] In this embodiment, first, FIG.
As shown in FIG. 1A, an element isolation film 2 is formed on a silicon substrate 1.
Source electrode 14, drain electrode 15, gate insulating film 30
Then, a gate electrode 16 was formed, and then a plasma silicon oxide film 3 was formed as an interlayer insulating film, and subsequently a contact hole was formed by using lithographic and etching techniques. Next, after sputtering titanium and titanium nitride as shown in FIG.
Was embedded in the contact hole opening, and subsequently, a metal wiring material was sputtered, and a first layer metal wiring 31 was formed by patterning using photolithography and etching techniques. The first-layer metal wiring has the same four-layer structure as in the first embodiment, but is not shown.

【0027】次に、図5(c)に示すようにCVD法に
より酸化シリコン膜35を堆積し、次にプラズマCVD
法によりフッ化アモルファスカーボン膜36を堆積し
た。その上に、再度CVD法により酸化シリコン膜37
を堆積した後、化学機械研磨(CMP)により酸化シリ
コン膜を研磨し表面を平坦化した。
Next, a silicon oxide film 35 is deposited by a CVD method as shown in FIG.
A fluorinated amorphous carbon film 36 was deposited by the method. Then, the silicon oxide film 37 is again formed by the CVD method.
Then, the silicon oxide film was polished by chemical mechanical polishing (CMP) to flatten the surface.

【0028】次に図6(a)に示すように酸化シリコン
膜35、フッ化アモルファスカーボン膜36および酸化
シリコン膜37からなる層間絶縁膜に、第1および第2
層金属配線を接続するスルーホールの開孔を行い、第1
層金属配線の形成と同様にして、タングステンプラグ2
0と第2層金属配線32を形成した。第2層金属配線も
実施例1と同じ4層構造よりなるが図示は省略した。
Next, as shown in FIG. 6A, the first and second interlayer insulating films including the silicon oxide film 35, the fluorinated amorphous carbon film 36 and the silicon oxide film 37 are formed.
The through holes for connecting the metal wiring layers are opened, and the first
In the same manner as the formation of the layer metal wiring, the tungsten plug 2
0 and the second layer metal wiring 32 were formed. The second-layer metal wiring also has the same four-layer structure as in the first embodiment, but is not shown.

【0029】次に、図6(b)に示すように膜厚400
nmのプラズマ酸化シリコン膜21を成膜し、この半導
体基板を2MPaの加圧水素ガス雰囲気中に導入し、3
00℃で20分間アニール処理を行った。引き続きプラ
ズマ窒化酸化シリコン膜およびポリイミド膜を成膜し、
続いてボンディングパッドの開孔を行い、更に組み立て
を行うことで所望の半導体装置を得た。
Next, as shown in FIG.
A plasma silicon oxide film 21 having a thickness of 3 nm is formed, and the semiconductor substrate is introduced into a pressurized hydrogen gas atmosphere of 2 MPa.
Annealing was performed at 00 ° C. for 20 minutes. Subsequently, a plasma silicon nitride oxide film and a polyimide film are formed,
Subsequently, a bonding pad was opened, and further assembly was performed to obtain a desired semiconductor device.

【0030】この場合も第1の実施例と同様に、プラズ
マ窒化酸化シリコン膜を成膜する工程において金属配線
層はすべての部分で絶縁膜に覆われており、MOSFE
Tは成膜雰囲気に存在するプラズマによるダメージを受
けない。
Also in this case, as in the first embodiment, in the step of forming the plasma silicon oxynitride film, the metal wiring layer is entirely covered with the insulating film, and
T is not damaged by plasma existing in the film formation atmosphere.

【0031】このようにこの実施例では、配線間の容量
低減を目的として層間絶縁膜に低誘電率膜であるフッ化
アモルファスカーボン膜を用いたが、従来より低い温度
で水素アニールができたため、フッ化アモルファスカー
ボン膜を損傷することなく、十分にプラズマダメージを
低減することができた。
As described above, in this embodiment, although the amorphous carbon fluoride film, which is a low dielectric constant film, is used as the interlayer insulating film for the purpose of reducing the capacitance between wirings, hydrogen annealing can be performed at a lower temperature than in the prior art. The plasma damage was sufficiently reduced without damaging the fluorinated amorphous carbon film.

【0032】[0032]

【発明の効果】本発明によれば、MOSFET等の半導
体装置において、金属配線層上部および/または下部に
バリア層としてチタン膜、あるいは窒化チタン膜のよう
な水素を吸収する物質が用いられ、絶縁膜の直上に大面
積で存在する場合でも、十分にプラズマダメージを除去
し、MOSFETの特性および信頼性が向上した半導体
装置を製造することができる。
According to the present invention, in a semiconductor device such as a MOSFET, a material that absorbs hydrogen, such as a titanium film or a titanium nitride film, is used as a barrier layer above and / or below a metal wiring layer. Even in the case where a large area exists immediately above the film, plasma damage can be sufficiently removed, and a semiconductor device with improved MOSFET characteristics and reliability can be manufactured.

【0033】また、本発明によれば、従来より低いアニ
ール温度を用いても十分にプラズマダメージを除去した
半導体装置を製造することができる。
Further, according to the present invention, it is possible to manufacture a semiconductor device from which plasma damage has been sufficiently removed even if an annealing temperature lower than that of the related art is used.

【図面の簡単な説明】[Brief description of the drawings]

【図1】加圧水素雰囲気でアニールを行う半導体基板の
構造を示す平面図である。
FIG. 1 is a plan view showing a structure of a semiconductor substrate to be annealed in a pressurized hydrogen atmosphere.

【図2】図1のA−B間の断面図である。FIG. 2 is a cross-sectional view taken along a line AB in FIG.

【図3】加圧水素雰囲気でアニールを行う半導体基板を
示す図である。
FIG. 3 is a view showing a semiconductor substrate to be annealed in a pressurized hydrogen atmosphere.

【図4】加圧水素雰囲気でアニール工程に続く半導体装
置の製造工程を示す図である。
FIG. 4 is a diagram showing a semiconductor device manufacturing process following an annealing process in a pressurized hydrogen atmosphere.

【図5】実施例2示した製造工程を示す図である。FIG. 5 is a view showing a manufacturing process shown in Example 2.

【図6】図5に引き続き実施例2示した製造工程を示す
図である。
FIG. 6 is a view showing a manufacturing step shown in Example 2 following FIG. 5;

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 素子分離膜 3 プラズマ酸化シリコン膜 4 タングステンプラグ 5 チタン膜 6 窒化チタン膜 7 アルミ・銅合金膜 8 窒化チタン膜 9 チタン膜 10 窒化チタン膜 11 アルミ・銅合金膜 12 窒化チタン膜 13 プラズマ酸化シリコン膜 14 ソース電極 15 ドレイン電極 16 ゲート電極 17 チタンシリサイド膜 18 プラズマ酸化シリコン膜 19 プラズマ窒化酸化シリコン膜 20 タングステンプラグ 21 プラズマ酸化シリコン膜 30 ゲート絶縁膜 31 第1層金属配線 32 第2層金属配線 35 酸化シリコン膜 36 フッ化アモルファスカーボン膜 37 酸化シリコン膜 Reference Signs List 1 silicon substrate 2 element isolation film 3 plasma silicon oxide film 4 tungsten plug 5 titanium film 6 titanium nitride film 7 aluminum / copper alloy film 8 titanium nitride film 9 titanium film 10 titanium nitride film 11 aluminum / copper alloy film 12 titanium nitride film 13 Plasma silicon oxide film 14 Source electrode 15 Drain electrode 16 Gate electrode 17 Titanium silicide film 18 Plasma silicon oxide film 19 Plasma silicon nitride oxide film 20 Tungsten plug 21 Plasma silicon oxide film 30 Gate insulating film 31 First layer metal wiring 32 Second layer Metal wiring 35 silicon oxide film 36 fluorinated amorphous carbon film 37 silicon oxide film

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 製造工程中に少なくとも1回のプラズマ
を用いる工程を有する製造工程により、ゲート絶縁膜、
電極、金属配線および層間絶縁膜を形成した半導体基板
を、加圧水素雰囲気中で加熱することを特徴とする半導
体装置の製造方法。
In a manufacturing process including a process using plasma at least once during the manufacturing process, a gate insulating film,
A method for manufacturing a semiconductor device, comprising: heating a semiconductor substrate on which an electrode, a metal wiring, and an interlayer insulating film are formed, in a pressurized hydrogen atmosphere.
【請求項2】 前記金属配線は、下層および/または上
層に高融点金属または高融点金属の窒化物からなる層を
有する積層構造であることを特徴とする請求項1記載の
半導体装置の製造方法。
2. The method for manufacturing a semiconductor device according to claim 1, wherein said metal wiring has a laminated structure having a layer made of a high melting point metal or a nitride of a high melting point metal in a lower layer and / or an upper layer. .
【請求項3】 前記層間絶縁膜の少なくとも1つは、プ
ラズマシリコン酸化膜であることを特徴とする請求項1
または2に記載の半導体装置の製造方法。
3. The semiconductor device according to claim 1, wherein at least one of said interlayer insulating films is a plasma silicon oxide film.
Or a method for manufacturing a semiconductor device according to item 2.
【請求項4】 前記層間絶縁膜の少なくとも1つは、フ
ッ化アモルファスカーボン層を含む層間絶縁膜である請
求項1または2に記載の半導体装置の製造方法。
4. The method according to claim 1, wherein at least one of the interlayer insulating films is an interlayer insulating film including a fluorinated amorphous carbon layer.
【請求項5】 前記加圧水素雰囲気の温度は、300〜
400℃であることを特徴とする請求項4記載の半導体
装置の製造方法。
5. The temperature of the pressurized hydrogen atmosphere is 300 to
The method according to claim 4, wherein the temperature is 400 ° C.
【請求項6】 前記加圧水素雰囲気の水素分圧は0.5
MPa以上であることを特徴とする請求項1〜5のいず
れかに記載の半導体装置の製造方法。
6. The hydrogen partial pressure of the pressurized hydrogen atmosphere is 0.5
The method for manufacturing a semiconductor device according to claim 1, wherein the pressure is at least MPa.
JP9146478A 1997-06-04 1997-06-04 Method for manufacturing semiconductor device Expired - Fee Related JP2976931B2 (en)

Priority Applications (2)

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KR1019980020614A KR19990006655A (en) 1997-06-04 1998-06-03 How to manufacture a semiconductor device

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JP9146478A JP2976931B2 (en) 1997-06-04 1997-06-04 Method for manufacturing semiconductor device

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JP2976931B2 true JP2976931B2 (en) 1999-11-10

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US10622214B2 (en) * 2017-05-25 2020-04-14 Applied Materials, Inc. Tungsten defluorination by high pressure treatment
US10276411B2 (en) 2017-08-18 2019-04-30 Applied Materials, Inc. High pressure and high temperature anneal chamber
JP6947914B2 (en) 2017-08-18 2021-10-13 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Annealing chamber under high pressure and high temperature
WO2019055415A1 (en) 2017-09-12 2019-03-21 Applied Materials, Inc. Apparatus and methods for manufacturing semiconductor structures using protective barrier layer
KR102585074B1 (en) 2017-11-11 2023-10-04 마이크로머티어리얼즈 엘엘씨 Gas delivery system for high pressure processing chamber
JP2021503714A (en) 2017-11-17 2021-02-12 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Capacitor system for high pressure processing system
SG11202008256WA (en) 2018-03-09 2020-09-29 Applied Materials Inc High pressure annealing process for metal containing materials
US10950429B2 (en) 2018-05-08 2021-03-16 Applied Materials, Inc. Methods of forming amorphous carbon hard mask layers and hard mask layers formed therefrom
US10748783B2 (en) 2018-07-25 2020-08-18 Applied Materials, Inc. Gas delivery module
KR20210077779A (en) 2018-11-16 2021-06-25 어플라이드 머티어리얼스, 인코포레이티드 Film Deposition Using Enhanced Diffusion Process
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JPH10335657A (en) 1998-12-18

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