KR20030057719A - Metal interconnection of semiconductor device and method of forming the same - Google Patents

Metal interconnection of semiconductor device and method of forming the same Download PDF

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Publication number
KR20030057719A
KR20030057719A KR1020010087795A KR20010087795A KR20030057719A KR 20030057719 A KR20030057719 A KR 20030057719A KR 1020010087795 A KR1020010087795 A KR 1020010087795A KR 20010087795 A KR20010087795 A KR 20010087795A KR 20030057719 A KR20030057719 A KR 20030057719A
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South Korea
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film
metal
forming
contact hole
titanium
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KR1020010087795A
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Korean (ko)
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KR100443363B1 (en
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채광기
배영헌
박수영
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주식회사 하이닉스반도체
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Priority to KR10-2001-0087795A priority Critical patent/KR100443363B1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

PURPOSE: A metal line of a semiconductor device and a method for forming the same are provided to be capable of preventing bridge and damage of a metal line by using a titanium silicide(TiSix) layer as a barrier metal film. CONSTITUTION: An interlayer dielectric(21) having a contact hole is formed on a semiconductor substrate(21). A polysilicon layer, a titanium film and a titanium nitride layer(24) are sequentially formed on the resultant structure including the contact hole. A tungsten film is entirely filled into the contact hole. A titanium silicide layer(25) is formed by reacting the polysilicon layer and the titanium film using annealing. A plug(26) is then formed by the etch-back of the tungsten film to expose the titanium nitride layer(24). After forming an aluminum film(27) on the resultant structure, a metal line is formed by sequentially etching the aluminum film, the titanium nitride layer and the titanium silicide layer.

Description

반도체 소자의 금속배선 및 그 형성방법{METAL INTERCONNECTION OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME}Metal interconnection of semiconductor device and method of forming the same {METAL INTERCONNECTION OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME}

본 발명은 반도체 소자의 금속배선 및 그 형성방법에 관한 것으로, 특히 배리어 금속막이 적용된 반도체 소자의 금속배선 및 그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal wiring of semiconductor devices and methods of forming the same, and more particularly to metal wiring of semiconductor devices to which a barrier metal film is applied and methods of forming the same.

반도체 소자 제조시, 소자간이나 소자와 외부회로 사이를 전기적으로 연결시키기 위하여 배선을 형성하며, 특히 낮은 저항이 요구되는 부분에는 알루미늄, 텅스텐 및 구리 등의 금속을 주 배선물질로 이용하는 금속배선을 형성한다. 또한, 금속배선의 형성 시에서는, 주 배선 물질 이외에도 배선 이외의 영역인 실리콘 활성영역이나 절연막 등으로 금속 원자들이 확산침투하는 것을 방지하기 위하여, 금속배선과 절연막 또는 활성영역 사이에 티타늄막/티타늄질화막(Ti/TiN)의 배리어(barrier) 금속막을 형성한다.In the manufacture of semiconductor devices, wirings are formed to electrically connect between devices or between devices and external circuits.In particular, metal wirings using metals such as aluminum, tungsten, and copper as main wiring materials are formed in areas where low resistance is required. do. In the formation of the metal wiring, a titanium film / titanium nitride film is formed between the metal wiring and the insulating film or the active region in order to prevent diffusion of metal atoms into the silicon active region, the insulating film, or the like other than the main wiring material. A barrier metal film of (Ti / TiN) is formed.

도 1은 상기 배리어 금속막이 적용된 종래의 반도체 소자의 배선을 나타낸 단면도로서, 도 1을 참조하여 그 형성방법을 간략하게 설명한다.FIG. 1 is a cross-sectional view illustrating a wiring of a conventional semiconductor device to which the barrier metal film is applied, and a method of forming the same will be briefly described with reference to FIG. 1.

도 1을 참조하면, 반도체 기판(10) 상에 층간절연막(11)을 형성하고, 기판(10)의 일부가 노출되도록 층간절연막(11)을 식각하여 콘택홀을 형성한다. 그 다음, 콘택홀 표면 및 층간절연막(11) 상에 배리어 금속막으로서 Ti막(12) 및 TiN막(13)을 적층한다. 그 후, 배리어 금속막이 형성된 콘택홀에 매립되도록 기판 전면 상에 플러그용 금속막으로서 텅스텐막을 증착하고 TiN막(13)의 표면이 노출되도록 전면 식각하여 플러그(14)를 형성한다. 그 다음, 기판 전면 상에 배선용 금속막으로서 알루미늄막(15)을 증착하고, Cl2 개스를 이용하여 알루미늄막(15), TiN막(13), 및 Ti막(12)을 식각하여 금속배선을 형성한다.Referring to FIG. 1, an interlayer insulating layer 11 is formed on a semiconductor substrate 10, and a contact hole is formed by etching the interlayer insulating layer 11 to expose a portion of the substrate 10. Then, a Ti film 12 and a TiN film 13 are laminated as a barrier metal film on the contact hole surface and the interlayer insulating film 11. Thereafter, a tungsten film is deposited as a plug metal film on the entire surface of the substrate so as to be filled in the contact hole in which the barrier metal film is formed, and the plug 14 is formed by etching the entire surface so that the surface of the TiN film 13 is exposed. Then, an aluminum film 15 is deposited as the metal film for wiring on the entire surface of the substrate, and the metal film is formed by etching the aluminum film 15, the TiN film 13, and the Ti film 12 using Cl2 gas. do.

그러나, Cl2 개스를 이용한 식각시, 알루미늄막(15)의 높은 식각속도에 의해 알루미늄막(15)은 빨리 식각되는 반면, TiN/Ti막의 상대적으로 느린 식각속도에 의해, 도 1에 도시된 바와 같이, 식각 종료 후에도 Ti막(12)이 잔류하여, 인접 배선과의 브리지를 유발하는 원인으로 작용한다. 또한, 이러한 Ti막(12)을 완전히 제거하기 위하여 과도식각(over etch)을 충분하게 수행하게 되면, 브리지 현상을 방지할 수는 있으나 알루미늄막(15)의 손상을 야기시켜, 결국 배선의 신뢰성을 저하시킨다.However, when etching with Cl2 gas, the aluminum film 15 is quickly etched by the high etching speed of the aluminum film 15, while the relatively slow etching speed of the TiN / Ti film is, as shown in FIG. After the etching is finished, the Ti film 12 remains, which acts as a cause of causing a bridge with the adjacent wiring. In addition, if the over etching is sufficiently performed to completely remove the Ti film 12, the bridge phenomenon may be prevented, but the aluminum film 15 may be damaged, resulting in reliability of the wiring. Lowers.

본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 배리어 금속막에 티타늄실리사이드(TiSix)막을 적용하여 배선형성을 위한 식각시 배리어 금속막의 잔류로 인한 브리지 현상 및 배선 손상 등을 방지할 수 있는 반도체 소자의 금속배선 및 그 제조방법을 제공하는데 그 목적이 있다.The present invention is proposed to solve the above problems of the prior art, by applying a titanium silicide (TiSix) film to the barrier metal film to prevent bridge phenomenon and wiring damage due to the residual of the barrier metal film during etching for wiring formation. It is an object of the present invention to provide a metal wiring of a semiconductor device and a method of manufacturing the same.

도 1은 종래의 반도체 소자의 금속배선을 나타낸 단면도.1 is a cross-sectional view showing a metal wiring of a conventional semiconductor device.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도.2A to 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

※도면의 주요부분에 대한 부호의 설명※ Explanation of symbols for main parts of drawing

20 : 반도체 기판 21 : 층간절연막20 semiconductor substrate 21 interlayer insulating film

22 : 폴리실리콘막 23 : Ti막22 polysilicon film 23 Ti film

24 : TiN막 25 : TiSix막24: TiN film 25: TiSix film

26 : 플러그 27 : 알루미늄막26 plug 27 aluminum film

상기의 기술적 과제를 달성하기 위한 본 발명의 일 측면에 따르면, 상기의 본 발명의 목적은 반도체 기판; 기판 상에 형성되고 기판의 일부를 노출시키는 콘택홀을 구비한 층간절연막; 콘택홀에 매립된 텅스텐 플러그; 플러그 및 층간절연막 상에 형성된 알루미늄막의 금속배선; 및 금속배선 및 플러그와, 콘택홀 사이에 개재된 배리어 금속막을 포함하고, 배리어 금속막이 티타늄실리사이드막과 티타늄질화막이 순차적으로 적층된 구조로 이루어진 반도체 소자의 금속배선에 의해 달성될 수 있다.According to an aspect of the present invention for achieving the above technical problem, the object of the present invention is a semiconductor substrate; An interlayer insulating film formed on the substrate and having a contact hole exposing a portion of the substrate; A tungsten plug embedded in the contact hole; Metal wiring of the aluminum film formed on the plug and the interlayer insulating film; And a barrier metal film interposed between the metal wiring and the plug and the contact hole, and the barrier metal film may be achieved by metal wiring of a semiconductor device having a structure in which a titanium silicide film and a titanium nitride film are sequentially stacked.

또한, 상기의 기술적 과제를 달성하기 위한 본 발명의 다른 측면에 따르면,상기의 본 발명의 목적은 반도체 기판 상에 층간절연막을 형성하는 단계; 층간절연막을 식각하여 기판의 일부를 노출시키는 콘택홀을 형성하는 단계; 콘택홀 표면 및 층간절연막 상에 배리어 금속막으로서 폴리실리콘막, 티타늄막, 및 티타늄질화막을 순차적으로 형성하는 단계; 배리어 금속막이 형성된 콘택홀에 매립되도록 기판 전면 상에 텅스텐막을 형성하는 단계; 텅스텐막이 형성된 기판을 열처리하여 폴리실리콘막과 티타늄막을 반응시켜 티타늄실리사이드막을 형성하는 단계; 티타늄질화막이 노출되도록 텅스텐막을 전면식각하여 플러그를 형성하는 단계; 플러그가 형성된 기판 전면 상에 알루미늄막을 형성하는 단계; 및 알루미늄막, 티타늄질화막, 및 티타늄실리사이드막을 식각하여 금속배선을 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성방법에 의해 달성될 수 있다.In addition, according to another aspect of the present invention for achieving the above technical problem, the object of the present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate; Etching the interlayer insulating film to form a contact hole exposing a portion of the substrate; Sequentially forming a polysilicon film, a titanium film, and a titanium nitride film as a barrier metal film on the contact hole surface and the interlayer insulating film; Forming a tungsten film on the entire surface of the substrate to be buried in the contact hole in which the barrier metal film is formed; Heat-treating the substrate on which the tungsten film is formed to react the polysilicon film with the titanium film to form a titanium silicide film; Forming a plug by etching the tungsten film over the entire surface so that the titanium nitride film is exposed; Forming an aluminum film on the entire surface of the substrate on which the plug is formed; And forming a metal wiring by etching the aluminum film, the titanium nitride film, and the titanium silicide film.

바람직하게, 폴리실리콘막은 530 내지 570℃의 온도에서 50 내지 200Å의 두께로 형성하고, 열처리는 급속열처리 공정으로 800 내지 1000℃의 온도에서 30 내지 200초 동안 수행한다.Preferably, the polysilicon film is formed to a thickness of 50 to 200 kPa at a temperature of 530 to 570 ℃, heat treatment is carried out for 30 to 200 seconds at a temperature of 800 to 1000 ℃ in a rapid heat treatment process.

이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도이다.2A through 2C are cross-sectional views illustrating a method of forming metal wirings in a semiconductor device according to an embodiment of the present invention.

도 2a를 참조하면, 반도체 기판(20) 상에 층간절연막(21)을 형성하고, 기판(20)의 일부가 노출되도록 층간절연막(21)을 식각하여 콘택홀을 형성한다. 그다음, 콘택홀 표면 및 층간절연막(21) 상에 배리어 금속막으로서 폴리실리콘막(22), Ti막(23), 및 TiN막(23)을 순차적으로 형성한다. 바람직하게, 폴리실리콘막(22)은 530 내지 570℃의 온도에서 50 내지 200Å의 두께로 형성한다.Referring to FIG. 2A, an interlayer insulating layer 21 is formed on a semiconductor substrate 20, and a contact hole is formed by etching the interlayer insulating layer 21 to expose a portion of the substrate 20. Then, the polysilicon film 22, the Ti film 23, and the TiN film 23 are sequentially formed on the contact hole surface and the interlayer insulating film 21 as a barrier metal film. Preferably, the polysilicon film 22 is formed to a thickness of 50 to 200 kPa at a temperature of 530 to 570 ℃.

도 2b를 참조하면, 배리어 금속막이 형성된 콘택홀에 매립되도록 기판 전면 상에 플러그용 금속막으로서 텅스텐막을 증착한다. 그 다음, 텅스텐막이 증착된 상기 기판을 열처리하여 폴리실리콘막(22)과 Ti막(23)을 반응시켜 티타늄실리사이드(TiSix)막(25)을 형성한다. 바람직하게, 열처리는 급속열처리(Rapid Thermal Annealing; RTA) 공정으로 800 내지 1000℃의 온도에서 30 내지 200초 동안 수행한다. 그 다음, TiN막(24)의 표면이 노출되도록 텅스텐막을 전면 식각하여 플러그(26)를 형성한다.Referring to FIG. 2B, a tungsten film is deposited as a plug metal film on the entire surface of a substrate so as to be buried in a contact hole in which a barrier metal film is formed. Next, the substrate on which the tungsten film is deposited is heat-treated to react the polysilicon film 22 with the Ti film 23 to form a titanium silicide (TiSix) film 25. Preferably, the heat treatment is carried out in a rapid thermal annealing (RTA) process for 30 to 200 seconds at a temperature of 800 to 1000 ℃. Then, the tungsten film is etched entirely so that the surface of the TiN film 24 is exposed to form a plug 26.

도 2c를 참조하면, 플러그(26)가 형성된 기판 전면 상에 배선용 금속막으로서 알루미늄막(27)을 증착하고, 종래와 같은 Cl2 개스를 이용하여, 알루미늄막(27), TiN막(24), 및 TiSix막(25)을 식각하여 금속배선을 형성한다.Referring to Fig. 2C, an aluminum film 27 is deposited as a metal film for wiring on the entire surface of the substrate on which the plug 26 is formed, and the aluminum film 27, the TiN film 24, using Cl2 gas as in the prior art, And the TiSix film 25 is etched to form metal wiring.

상기 실시예에 의하면, 배리어 금속막에 폴리실리콘을 적용하여 티타늄막을 티타늄실리사이드(TiSix)의 조성을 갖도록 하여 Cl2 개스에 대한 식각속도를 향상시켜 알루미늄막과의 식각속도차를 감소시킴으로써, 배선형성을 위한 식각 후 종래와 같은 배리어 금속막의 잔류를 방지할 있다. 따라서, 이러한 배리어 금속막의 잔류로 인한 브리지를 방지할 수 있을 뿐만 아니라 과도식각을 수행할 필요가 없기 때문에 배선의 손상 등도 방지할 수 있다.According to the above embodiment, by applying polysilicon to the barrier metal film to make the titanium film have a composition of titanium silicide (TiSix) to improve the etching rate for Cl2 gas to reduce the etching rate difference with the aluminum film, thereby forming a wiring After etching, it is possible to prevent the residual of the barrier metal film as in the prior art. Therefore, not only the bridge due to the residual of the barrier metal film can be prevented, but also the damage of the wiring and the like can be prevented because it is not necessary to perform the over etching.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

전술한 본 발명은 배리어 금속막에 티타늄실리사이드막을 적용하여 배선형성을 위한 식각시 배리어 금속막의 잔류로 인한 브리지 현상 및 배선 손상 등을 방지함으로써, 배선의 신뢰성을 향상시킬 수 있다.According to the present invention, a titanium silicide film is applied to the barrier metal film to prevent bridge phenomenon and wiring damage due to the residual of the barrier metal film during etching for forming the wiring, thereby improving the reliability of the wiring.

Claims (9)

반도체 기판;Semiconductor substrates; 상기 기판 상에 형성되고 상기 기판의 일부를 노출시키는 콘택홀을 구비한 층간절연막;An interlayer insulating film formed on the substrate and having a contact hole exposing a portion of the substrate; 상기 콘택홀에 매립된 금속막의 플러그;A plug of the metal film embedded in the contact hole; 상기 플러그 및 층간절연막 상에 형성된 금속배선; 및A metal wiring formed on the plug and the interlayer insulating film; And 상기 금속배선 및 플러그와, 상기 콘택홀 사이에 개재된 배리어 금속막을 포함하고,A barrier metal film interposed between the metal wire and the plug and the contact hole; 상기 배리어 금속막은 티타늄실리사이드막과 티타늄질화막이 순차적으로 적층된 구조로 이루어진 것을 특징으로 하는 반도체 소자의 금속배선.The barrier metal film has a structure in which a titanium silicide film and a titanium nitride film are sequentially stacked. 제 1 항에 있어서,The method of claim 1, 상기 금속배선을 알루미늄막으로 이루어진 것을 특징으로 하는 반도체 소자의 금속배선.The metal wiring of the semiconductor device, characterized in that the metal wiring is made of an aluminum film. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 금속 플러그는 텅스텐막으로 이루어진 것을 특징으로 하는 반도체 소자의 금속배선.The metal plug is a metal wiring of the semiconductor device, characterized in that consisting of a tungsten film. 반도체 기판 상에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on the semiconductor substrate; 상기 층간절연막을 식각하여 상기 기판의 일부를 노출시키는 콘택홀을 형성하는 단계;Etching the interlayer insulating layer to form a contact hole exposing a portion of the substrate; 상기 콘택홀 표면 및 상기 층간절연막 상에 배리어 금속막으로서 폴리실리콘막, 티타늄막, 및 티타늄질화막을 순차적으로 형성하는 단계;Sequentially forming a polysilicon film, a titanium film, and a titanium nitride film as barrier metal films on the contact hole surface and the interlayer insulating film; 상기 배리어 금속막이 형성된 상기 콘택홀에 매립되도록 상기 기판 전면 상에 플러그용 제 1 금속막을 형성하는 단계;Forming a first metal film for plug on the entire surface of the substrate to be filled in the contact hole in which the barrier metal film is formed; 상기 제 1 금속막이 형성된 기판을 열처리하여 상기 폴리실리콘막과 상기 티타늄막을 반응시켜 티타늄실리사이드막을 형성하는 단계;Heat treating the substrate on which the first metal film is formed to react the polysilicon film with the titanium film to form a titanium silicide film; 상기 티타늄질화막이 노출되도록 상기 제 1 금속막을 전면식각하여 플러그를 형성하는 단계;Forming a plug by etching the entire surface of the first metal film to expose the titanium nitride film; 상기 플러그가 형성된 기판 전면 상에 배선용 제 2 금속막을 형성하는 단계; 및Forming a second metal film for wiring on the entire surface of the substrate on which the plug is formed; And 상기 제 2 금속막, 티타늄질화막, 및 티타늄실리사이드막을 식각하여 금속배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.Forming a metal wire by etching the second metal film, the titanium nitride film, and the titanium silicide film. 제 4 항에 있어서,The method of claim 4, wherein 상기 폴리실리콘막은 530 내지 570℃의 온도에서 50 내지 200Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The polysilicon film is a metal wiring forming method of a semiconductor device, characterized in that formed at a thickness of 50 to 200Å at a temperature of 530 to 570 ℃. 제 4 항에 있어서,The method of claim 4, wherein 상기 열처리는 급속열처리 공정으로 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The heat treatment is a metal wiring forming method of a semiconductor device, characterized in that performed in a rapid heat treatment process. 제 6 항에 있어서,The method of claim 6, 상기 급속열처리 공정은 800 내지 1000℃의 온도에서 30 내지 200초 동안 수행하는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.The rapid heat treatment process is a metal wiring forming method of a semiconductor device, characterized in that performed for 30 to 200 seconds at a temperature of 800 to 1000 ℃. 제 4 항에 있어서,The method of claim 4, wherein 상기 제 1 금속막은 텅스텐막인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And the first metal film is a tungsten film. 제 4 항에 있어서,The method of claim 4, wherein 상기 제 2 금속막은 알루미늄막인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.And the second metal film is an aluminum film.
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