JPH0629294A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0629294A
JPH0629294A JP4203055A JP20305592A JPH0629294A JP H0629294 A JPH0629294 A JP H0629294A JP 4203055 A JP4203055 A JP 4203055A JP 20305592 A JP20305592 A JP 20305592A JP H0629294 A JPH0629294 A JP H0629294A
Authority
JP
Japan
Prior art keywords
film
contact hole
barrier
wiring
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4203055A
Other languages
Japanese (ja)
Other versions
JP3194793B2 (en
Inventor
Shigeya Mori
重哉 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20305592A priority Critical patent/JP3194793B2/en
Publication of JPH0629294A publication Critical patent/JPH0629294A/en
Application granted granted Critical
Publication of JP3194793B2 publication Critical patent/JP3194793B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To provide a method for manufacturing a highly adhesive and highly reliable wiring film by solving problems that a wiring layer formed between an Al wiring film and a barrier film (TiN, Ti layer) suffer from defective adhesion properties with a base insulation film and a pad is subjected to separation during wire bonding. CONSTITUTION:With regards to the prior art heat treatment for an enhanced Ti silicide after the film formation of barrier films 5 and 6, the reaction between a Ti film 5 in the lowest layer of the barrier film and a base insulation film 3 forms a fragile TiO2 film or the like and degrades the adhesion properties. In addition, a silicon film is deposited on a board 1 which includes a contact hole 13. The silicon film on the bottom of the contact hole is eliminated by sputtering etching while a silicon film 4a is adapted to remain on the insulation film at the same time. Then, after the barrier layers are deposited, heat treatment is carried out so as to form a Ti silicide layer at the contact portion. During the heat treatment, the residual silicon film 4a is interposed between the Ti film 5 and the insulation film 3, which protects the adhesion properties from being degraded.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関するもので、特にAl 系配線膜の密着性に係り、U
LSI等の配線膜の形成方法に使用されるものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to the adhesion of Al-based wiring films.
It is used in a method of forming a wiring film such as an LSI.

【0002】[0002]

【従来の技術】LSI等に使用される配線膜の従来例に
ついて、図6及び図7を参照して説明する。
2. Description of the Related Art A conventional example of a wiring film used in an LSI or the like will be described with reference to FIGS.

【0003】図6はコンタクト孔(コンタクトホールと
呼ばれる)を含む基板断面図である。半導体基板1上に
絶縁物のBPSG膜(硼素リンガラス)3が形成され、
このBPSG膜3には、基板1の表面に露出して形成さ
れた不純物拡散層(活性層)2と、電気的接触をとるた
めのコンタクト孔が開孔されている。このコンタクト孔
を含むBPSG膜3上に、Ti 膜5及びTi N膜6から
なるバリア膜が形成される。さらにその上にAl または
Al 合金(例えばAl −Si 、Al −Cu )からなるA
l 系配線膜8が形成される。
FIG. 6 is a sectional view of a substrate including a contact hole (called a contact hole). An insulating BPSG film (boron phosphorus glass) 3 is formed on the semiconductor substrate 1,
The BPSG film 3 has contact holes for making electrical contact with the impurity diffusion layer (active layer) 2 formed on the surface of the substrate 1 so as to be exposed. A barrier film composed of the Ti film 5 and the Ti N film 6 is formed on the BPSG film 3 including the contact holes. On top of that, an Al or Al alloy (for example, Al-Si, Al-Cu)
The l-based wiring film 8 is formed.

【0004】上記のバリア膜は、Al とSi が反応する
ことによって生じる、Al 系配線のコンタクト部の接合
突き抜けや、Si 析出によるコンタクト抵抗増大等を抑
制するために設けられるものである。
The above-mentioned barrier film is provided in order to suppress the contact penetration of the contact portion of the Al-based wiring and the increase in contact resistance due to the precipitation of Si, which are caused by the reaction between Al and Si.

【0005】なおTi 膜5及びTi N膜6からなるバリ
ア膜の形成直後には、コンタクト部において、Si 基板
表面の薄い酸化物のTi による還元、及びTi とSi と
のシリサイド化を促進して、コンタクト抵抗を低減する
ための熱処理が行われる。この熱処理によって、拡散層
2近傍のTi 膜は、Ti シリサイド層7になる。次に前
記Al 系配線膜8を形成した後に、パターニングを行な
い配線パターンを形成する。
Immediately after the formation of the barrier film composed of the Ti film 5 and the Ti N film 6, the reduction of the thin oxide on the surface of the Si substrate by Ti and the silicidation of Ti and Si are promoted at the contact portion. A heat treatment is performed to reduce the contact resistance. By this heat treatment, the Ti film in the vicinity of the diffusion layer 2 becomes the Ti silicide layer 7. Next, after the Al-based wiring film 8 is formed, patterning is performed to form a wiring pattern.

【0006】次に図7に示すように、その上に絶縁保護
膜9を堆積し、ボンディングパッド部10を開孔する。
なお図7は、ワイヤボンディング後のパッド部10を含
む基板断面図である。
Next, as shown in FIG. 7, an insulating protective film 9 is deposited thereon, and a bonding pad portion 10 is opened.
Note that FIG. 7 is a cross-sectional view of the substrate including the pad portion 10 after wire bonding.

【0007】このような半導体装置においては、ボンデ
ィングワイヤ11をパッド部10にボンディングすると
きと、パッド部10と下地絶縁膜3との界面近傍で剥離
(12)する、すなわち密着性不良が生じるという問題
点があった。
In such a semiconductor device, when the bonding wire 11 is bonded to the pad portion 10, and when the pad portion 10 and the base insulating film 3 are separated (12) near the interface, that is, poor adhesion occurs. There was a problem.

【0008】[0008]

【発明が解決しようとする課題】前記のように、高集積
化されたLSI等において、Al 系配線膜を使用するデ
バイスでは、拡散層とのコンタクト部において、Al ま
たはAl 合金とSi 基板との反応を防止するため、Ti
N及びTi からなるバリア膜が使用されている。Al ま
たはAl 合金とバリア膜との積層配線からなるボンディ
ングパッド部は、下地絶縁膜との密着性が悪く、ワイヤ
ボンディング時に、パッド部と下地絶縁膜とが剥離する
という問題がある。
As described above, in a highly integrated LSI or the like, in a device using an Al-based wiring film, the Al or Al alloy and the Si substrate are contacted with each other at the contact portion with the diffusion layer. Ti to prevent reaction
A barrier film consisting of N and Ti is used. The bonding pad portion formed of the laminated wiring of Al or Al alloy and the barrier film has poor adhesion with the underlying insulating film, and there is a problem that the pad portion and the underlying insulating film are separated during wire bonding.

【0009】本発明は、この問題点を考慮してなされた
ものであって、積層配線膜と下地絶縁膜との密着性に対
して高い信頼性を有する半導体装置の製造方法を提供す
ることを目的とする。
The present invention has been made in consideration of this problem, and provides a method of manufacturing a semiconductor device having high reliability with respect to the adhesion between a laminated wiring film and a base insulating film. To aim.

【0010】[0010]

【課題を解決するための手段】本発明は、(a)不純物
拡散層が表面に露出して形成された半導体基板上に絶縁
膜(例えばSi 酸化膜を含む絶縁膜)を形成する工程
と、(b)この絶縁膜に前記拡散層の露出面に達するコ
ンタクト孔を形成する工程と、(c)コンタクト孔を含
む前記半導体基板上にスパッタリングによりSi 膜を形
成する工程と、(d)スパッタエッチングによりコンタ
クト孔底に付着したSi 膜を除去すると共に前記絶縁膜
上にSi 膜を残した後、引き続いて大気にさらすことな
くTi 膜とTi N膜とをこの順に前記基板上に形成する
工程と、(e)前記コンタクト孔底にTi シリサイド層
を形成する熱処理工程と、(f)前記基板上にAl 系
(AlまたはAl 合金)配線膜を形成する工程とを含む
ことを特徴とする半導体装置の製造方法である。
The present invention comprises (a) a step of forming an insulating film (for example, an insulating film containing a Si oxide film) on a semiconductor substrate having an impurity diffusion layer exposed on the surface thereof, (B) a step of forming a contact hole reaching the exposed surface of the diffusion layer in the insulating film; (c) a step of forming a Si film on the semiconductor substrate including the contact hole by sputtering; and (d) sputter etching. By removing the Si film adhering to the bottom of the contact hole and leaving the Si film on the insulating film, and subsequently forming the Ti film and the TiN film in this order on the substrate without exposing to the atmosphere. , (E) a heat treatment step of forming a Ti silicide layer on the bottom of the contact hole, and (f) a step of forming an Al-based (Al or Al alloy) wiring film on the substrate. of It is a manufacturing method.

【0011】[0011]

【作用】Al 系配線膜及びバリア膜(Ti N,Ti )か
らなる積層配線膜と下地絶縁膜との密着性が良くない要
因について調査したところ、バリア膜形成直後に行なう
コンタクト抵抗低減のための熱処理工程において、積層
配線膜の最下層のTi 膜と下地絶縁膜とが反応して、脆
い層(Ti O2 やTi B)が生成されるためであり、ま
たこの密着性不良は、下地絶縁膜の構成成分にも影響さ
れ、特にB(硼素)の含有率が高い下地膜ほど発生しや
すいことを発見した。
The function of the poor adhesion between the laminated wiring film made of Al-based wiring film and the barrier film (Ti N, Ti) and the underlying insulating film was investigated, and it was found that the contact resistance reduction immediately after the formation of the barrier film was performed. This is because in the heat treatment step, the lowermost Ti film of the laminated wiring film reacts with the underlying insulating film to form a brittle layer (TiO 2 or Ti B). It has been found that the base film, which is influenced by the constituent components of the film and has a particularly high B (boron) content, is more likely to occur.

【0012】本発明はこの知見に基づいてなされたもの
である。すなわちコンタクト孔を形成し、コンタクト孔
底の拡散層の露出面を含む基板上に、通常のスパッタリ
ングによりSi 膜を形成すると、スパッタリングの成膜
特性上、前記コンタクト孔底に堆積されるSi 膜の厚さ
は、絶縁膜上に堆積されるSi 膜の厚さに比べ薄く、例
えば数分の 1程度である。次にスパッタエッチングによ
りSi 膜の除去を行なうとスパッタエッチングのエッチ
ング特性により、コンタクト孔底の薄いSi 膜を除去す
ると同時に絶縁膜上に堆積した厚いSi 膜を残すことが
できる。次に引き続いて大気にさらすことなく、すなわ
ちコンタクト孔に露出する拡散層面及び絶縁膜上の残留
Si 膜を清浄に保持した状態でその上にバリア膜を形成
する。次にコンタクト孔に露出する拡散層のSi とバリ
ア膜のTi とを反応させ、低抵抗のTi シリサイド層を
形成し、コンタクト抵抗を低減する熱処理工程を行なう
が、この際、本発明の製造方法によれば、絶縁膜とその
上に堆積されるバリア層との間に残留Si 膜が設けられ
ており、バリア膜形成後の前記熱処理において、このS
i 膜により、絶縁膜とバリア膜との反応が抑えられ、従
来技術に見られたTi O2 やTi B等の脆い層が形成さ
れず、密着性に対して高い信頼性のボンディングパッド
部を含む配線膜が得られ、ボンディング時にパッド部か
らの剥離もなくなった。
The present invention has been made based on this finding. That is, when the contact hole is formed and the Si film is formed on the substrate including the exposed surface of the diffusion layer at the bottom of the contact hole by the ordinary sputtering, the Si film deposited on the bottom of the contact hole is formed due to the film formation characteristics of the sputtering. The thickness is thinner than the thickness of the Si film deposited on the insulating film, and is, for example, about a fraction. Next, when the Si film is removed by sputter etching, the thin Si film at the bottom of the contact hole can be removed and at the same time the thick Si film deposited on the insulating film can be left due to the etching characteristics of sputter etching. Then, subsequently, without exposing to the atmosphere, that is, while the residual Si film on the diffusion layer surface and the insulating film exposed in the contact hole is kept clean, a barrier film is formed thereon. Next, Si of the diffusion layer exposed in the contact hole is reacted with Ti of the barrier film to form a Ti silicide layer of low resistance, and a heat treatment step of reducing the contact resistance is performed. At this time, the manufacturing method of the present invention is performed. According to the document, the residual Si film is provided between the insulating film and the barrier layer deposited on the insulating film.
The i film suppresses the reaction between the insulating film and the barrier film, does not form the brittle layer such as TiO 2 or Ti B found in the conventional technique, and provides a bonding pad portion with high reliability for adhesion. A wiring film containing the same was obtained, and peeling from the pad portion was eliminated during bonding.

【0013】[0013]

【実施例】以下、本発明の一実施例について図面を参照
して説明する。図1ないし図5は、本実施例による半導
体装置の製造方法を工程順に示す断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 5 are sectional views showing a method of manufacturing a semiconductor device according to this embodiment in the order of steps.

【0014】図1に示すように、P型シリコン半導体基
板1の主表面に燐イオン(P+ )や砒素イオン(A
+ )等の不純物イオンが注入され、基板1の主表面に
露出してN型不純物拡散層2が形成されている。そして
基板1の主表面全体に絶縁膜(BPSG膜)3が形成さ
れ、この絶縁膜3に対し、写真蝕刻法が用いられ、拡散
層2の前記露出面に達するコンタクト孔13が、例えば
RIE法により設けられる。なお図6及び図7と同じ符
号は同一部分または相当部分をあらわす。
As shown in FIG. 1, phosphorus ions (P + ) and arsenic ions (A) are formed on the main surface of the P-type silicon semiconductor substrate 1.
Impurity ions such as s + ) are implanted and exposed on the main surface of the substrate 1 to form the N-type impurity diffusion layer 2. Then, an insulating film (BPSG film) 3 is formed on the entire main surface of the substrate 1, and a photolithography method is used for the insulating film 3 so that the contact hole 13 reaching the exposed surface of the diffusion layer 2 is formed by, for example, the RIE method. Provided by. The same reference numerals as those in FIGS. 6 and 7 represent the same or corresponding portions.

【0015】次に図2に示すように、コンタクト孔13
を含む基板上、すなわち絶縁膜3の表面及びコンタクト
孔13に、通常のスパッタ装置(カソード側にSi ター
ゲットを、アノード側にウェーハを配し、Ar ガス使
用)により、Si のスパッタが行なわれ、膜厚10nmない
し50nmのSi 膜4が堆積される。このとき、スパッタリ
ングの成膜特性から、コンタクト孔13内に堆積される
Si 膜厚は、絶縁膜3上に堆積されるSi 膜厚に比し薄
い。例えばアスペクト比 0.5以上のコンタクト孔内のS
i 膜厚は、絶縁膜3上のSi 膜厚の 5分の 1以下であ
る。
Next, as shown in FIG. 2, the contact hole 13
Si is sputtered on the substrate including, that is, on the surface of the insulating film 3 and the contact hole 13 by an ordinary sputtering device (Si target is placed on the cathode side and a wafer is placed on the anode side and Ar gas is used). A Si film 4 having a film thickness of 10 nm to 50 nm is deposited. At this time, the Si film thickness deposited in the contact hole 13 is smaller than the Si film thickness deposited on the insulating film 3 due to the film forming characteristics of the sputtering. For example, S in a contact hole with an aspect ratio of 0.5 or more
The i film thickness is one fifth or less of the Si film thickness on the insulating film 3.

【0016】次に図3に示すように、再びスパッタ装置
に前記基板1を搬入し、スパッタエッチングにより、コ
ンタクト孔内に堆積したSi 膜4が無くなるまでエッチ
ングを行なう。この時、絶縁膜3上のSi 膜は、コンタ
クト孔13内のSi 膜厚よりかなり厚いので、膜厚の違
いにより十分な厚さのSi 膜4aが絶縁膜3上に残され
る。
Next, as shown in FIG. 3, the substrate 1 is again carried into the sputtering apparatus, and is sputter-etched until the Si film 4 deposited in the contact hole is removed. At this time, since the Si film on the insulating film 3 is considerably thicker than the Si film thickness in the contact hole 13, the Si film 4a having a sufficient thickness is left on the insulating film 3 due to the difference in film thickness.

【0017】その後、大気中にさらすことなく、引き続
いて真空中でスパッタリングによりTi 膜5を、次にT
i N膜6を、それぞれ堆積する。
Thereafter, the Ti film 5 is successively sputtered in vacuum without being exposed to the atmosphere, and then the Ti film 5 and then the T film 5 are deposited.
The iN films 6 are deposited respectively.

【0018】次に図4に示すように、 400℃ないし 800
℃の温度で熱処理を行ない、コンタクト孔底のTi と拡
散層2のSi とを反応させて、Ti シリサイド層7を形
成する。
Next, as shown in FIG.
A heat treatment is performed at a temperature of .degree. C. to react Ti at the bottom of the contact hole with Si at the diffusion layer 2 to form a Ti silicide layer 7.

【0019】次に図5に示すように、Ti N膜6の表面
全体に、Al 合金がスパッタリングにより堆積され、厚
さ 400nmないし 800nmのAl 系配線膜8が形成される。
次にAl 系配線膜8、Ti N膜6、Ti 膜5及びSi 膜
4aからなる積層膜に、通常の写真蝕刻法を用い、所望
のパターンの積層配線膜を形成する。
Next, as shown in FIG. 5, an Al alloy is deposited by sputtering on the entire surface of the TiN film 6 to form an Al-based wiring film 8 having a thickness of 400 nm to 800 nm.
Next, a laminated wiring film having a desired pattern is formed on the laminated film including the Al-based wiring film 8, the TiN film 6, the Ti film 5 and the Si film 4a by using a normal photolithography method.

【0020】次に図示してないが、その上に、絶縁保護
膜、例えばPSG膜(燐ガラス膜)を、約 1μm 程度の
厚さ堆積した後、ボンディングパッド部の開孔を行な
う。
Next, although not shown, an insulating protective film, for example, a PSG film (phosphorus glass film) is deposited thereon to a thickness of about 1 μm, and then the bonding pad portion is opened.

【0021】このように本実施例の製造方法により形成
された配線膜は、絶縁膜3上ではAl 系配線膜8、Ti
N膜6、Ti 膜5及びSi 膜4aの積層構造で構成され
ている。Si 膜4aがTi 膜5と絶縁膜3との間にある
ため、Ti N膜6を堆積した後に行なうコンタクト抵抗
低減化のための熱処理工程において、Ti 膜5と絶縁膜
3とは反応することがなく、したがってTi O2 やTi
B等の脆い層も形成されることがないため、ワイヤボン
ディング時にボンディングパッド部と下地の絶縁膜3と
の界面近傍で剥離することがなくなる。
As described above, the wiring film formed by the manufacturing method of the present embodiment has the Al-based wiring film 8 and Ti formed on the insulating film 3.
It has a laminated structure of an N film 6, a Ti film 5 and a Si film 4a. Since the Si film 4a is between the Ti film 5 and the insulating film 3, the Ti film 5 and the insulating film 3 should react with each other in the heat treatment step for reducing the contact resistance after the TiN film 6 is deposited. , Therefore there is no Ti O 2 or Ti
Since a brittle layer such as B is not formed, peeling does not occur near the interface between the bonding pad portion and the underlying insulating film 3 during wire bonding.

【0022】他方、コンタクト孔底の拡散層2の表面上
にはスパッタにより堆積されたSi膜は残っておらず、
Ti 膜は拡散層2のSi とシリサイド化され、低抵抗の
Tiシリサイド層7が形成されているため、拡散層2と
前記積層配線膜との間のコンタクト抵抗は、従来と同様
低減されている。
On the other hand, there is no Si film deposited by sputtering on the surface of the diffusion layer 2 at the bottom of the contact hole,
Since the Ti film is silicided with Si of the diffusion layer 2 and the Ti silicide layer 7 having a low resistance is formed, the contact resistance between the diffusion layer 2 and the laminated wiring film is reduced as in the conventional case. .

【0023】また上記積層配線膜は、Al 系配線膜8の
下部にTi N膜6、Ti 膜5及びSi 膜4aからなる積
層バリアメタル層が敷かれていることにより、エレクト
ロマイグレーション(E.M.)及びストレスマイグレ
ーション(S.M.)の発生が抑制される。
Further, in the above-mentioned laminated wiring film, a laminated barrier metal layer composed of the TiN film 6, the Ti film 5 and the Si film 4a is laid under the Al-based wiring film 8, so that electromigration (EM) is performed. .) And stress migration (S.M.) are suppressed.

【0024】上記実施例において、図2に示すスパッタ
リングによりSi 膜を形成する工程において、絶縁膜上
に堆積するSi 膜4の膜厚の望ましい実施態様は、10nm
ないし50nmである。Si 膜厚が10nm以下の場合には、後
工程における熱処理に際し、絶縁膜3とTi 膜5との反
応を抑制できないおそれがある。またコンタクト抵抗低
減のためには、コンタクト孔底の拡散層上に、スパッタ
により形成されたSi層4を残さないことが必要であ
り、このためSi 膜厚を50nm以上にすることは望ましく
ない。
In the above embodiment, in the step of forming the Si film by sputtering shown in FIG. 2, a preferable embodiment of the film thickness of the Si film 4 deposited on the insulating film is 10 nm.
To 50 nm. If the Si film thickness is 10 nm or less, the reaction between the insulating film 3 and the Ti film 5 may not be suppressed during the heat treatment in the subsequent step. Further, in order to reduce the contact resistance, it is necessary not to leave the Si layer 4 formed by sputtering on the diffusion layer at the bottom of the contact hole. Therefore, it is not desirable to set the Si film thickness to 50 nm or more.

【0025】上述した実施例は一例であり、本発明を限
定するものではない。例えば実施例では、Al 系配線膜
8はAl 合金から成っているが、純粋なAl で形成して
もよい。また実施例の拡散層2はN型であるがP型の拡
散層を形成する場合にも、同様に本発明を適用できる。
また絶縁膜にはBPSG膜を例にとったが、Si O
2膜、PSG膜等であっても差支えない。
The above-described embodiments are merely examples and do not limit the present invention. For example, in the embodiment, the Al type wiring film 8 is made of Al alloy, but it may be made of pure Al. Although the diffusion layer 2 of the embodiment is N-type, the present invention can be similarly applied to the case of forming a P-type diffusion layer.
The insulating film is a BPSG film as an example.
Two films, PSG film, etc. can be used.

【0026】[0026]

【発明の効果】これまで詳述したように、本発明の半導
体装置の製造方法によれば、Ti N及びTi から成るバ
リア膜と下地の絶縁膜との間にSi 膜を介在させること
により、Ti N膜成膜後の加熱処理時に、Ti 膜と絶縁
膜との反応を抑え、Ti O2 やTi B等の脆い層の形成
がないため、ワイヤボンディング時に剥離もなく、パッ
ド部と下地絶縁膜との密着性に対して、高い信頼性を有
する半導体装置の製造方法を提供することができた。
As described above in detail, according to the method of manufacturing a semiconductor device of the present invention, the Si film is interposed between the barrier film composed of Ti N and Ti and the underlying insulating film. During the heat treatment after forming the TiN film, the reaction between the Ti film and the insulating film is suppressed, and a brittle layer such as TiO 2 or TiB is not formed. It was possible to provide a method for manufacturing a semiconductor device having high reliability with respect to the adhesion to a film.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の製造方法の工程の一例を
示す断面図である。
FIG. 1 is a cross-sectional view showing an example of steps of a method for manufacturing a semiconductor device of the present invention.

【図2】図1に示す工程に引き続く製造工程を示す断面
図である。
FIG. 2 is a cross-sectional view showing a manufacturing process that follows the process shown in FIG.

【図3】図2に示す工程に引き続く製造工程を示す断面
図である。
FIG. 3 is a cross-sectional view showing a manufacturing process that follows the process shown in FIG.

【図4】図3に示す工程に引き続く製造工程を示す断面
図である。
FIG. 4 is a cross-sectional view showing a manufacturing process that follows the process shown in FIG.

【図5】図4に示す工程に引き続く製造工程を示す断面
図である。
FIG. 5 is a cross-sectional view showing a manufacturing process that follows the process shown in FIG.

【図6】従来の半導体装置の製造方法を説明するための
コンタクト孔を含む基板断面図である。
FIG. 6 is a cross-sectional view of a substrate including a contact hole for explaining a conventional method for manufacturing a semiconductor device.

【図7】従来の半導体装置の製造方法の問題点を説明す
るための基板断面図である。
FIG. 7 is a cross-sectional view of a substrate for explaining a problem of a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 シリコン半導体基板(P型) 2 不純物拡散層(N型) 3 絶縁膜(BPSG膜) 4 スパッタリングにより形成されたSi 膜 4a スパッタエッチング後に残されたSi 膜 5 Ti 膜 6 Ti N膜 7 Ti シリサイド膜 8 Al 系配線膜 9 絶縁保護膜 10 ボンディングパッド部 12 Ti 膜と下地絶縁膜との剥離 13 コンタクト孔 1 Silicon semiconductor substrate (P type) 2 Impurity diffusion layer (N type) 3 Insulating film (BPSG film) 4 Si film formed by sputtering 4a Si film left after sputter etching 5 Ti film 6 Ti N film 7 Ti silicide Film 8 Al wiring film 9 Insulation protection film 10 Bonding pad 12 Separation of Ti film and underlying insulating film 13 Contact hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】不純物拡散層が表面に露出して形成された
半導体基板上に絶縁膜を形成する工程と、この絶縁膜に
前記拡散層の露出面に達するコンタクト孔を形成する工
程と、コンタクト孔を含む前記半導体基板上にスパッタ
リングによりSi 膜を形成する工程と、スパッタエッチ
ングによりコンタクト孔底に付着したSi 膜を除去する
と共に前記絶縁膜上にSi 膜を残した後、引き続いて大
気にさらすことなくTi 膜とTi N膜とをこの順に前記
基板上に形成する工程と、前記コンタクト孔底にTi シ
リサイド層を形成する熱処理工程と、前記基板上にAl
系配線膜を形成する工程とを含むことを特徴とする半導
体装置の製造方法。
1. A step of forming an insulating film on a semiconductor substrate on which an impurity diffusion layer is exposed and a step of forming a contact hole reaching the exposed surface of the diffusion layer in the insulating film, and a contact. Forming a Si film on the semiconductor substrate including the holes by sputtering, and removing the Si film adhering to the bottom of the contact hole by sputter etching and leaving the Si film on the insulating film, and then exposing it to the atmosphere. Without forming a Ti film and a Ti N film in this order on the substrate, a heat treatment process of forming a Ti silicide layer on the bottom of the contact hole, and an Al film on the substrate.
And a step of forming a system wiring film.
JP20305592A 1992-07-07 1992-07-07 Method for manufacturing semiconductor device Expired - Fee Related JP3194793B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20305592A JP3194793B2 (en) 1992-07-07 1992-07-07 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20305592A JP3194793B2 (en) 1992-07-07 1992-07-07 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0629294A true JPH0629294A (en) 1994-02-04
JP3194793B2 JP3194793B2 (en) 2001-08-06

Family

ID=16467597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20305592A Expired - Fee Related JP3194793B2 (en) 1992-07-07 1992-07-07 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP3194793B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6417568B1 (en) 1999-03-12 2002-07-09 Nec Corporation Semiconductor device
KR20030050846A (en) * 2001-12-19 2003-06-25 주식회사 하이닉스반도체 Method for forming metal line of semiconductor
KR100480576B1 (en) * 1997-12-15 2005-05-16 삼성전자주식회사 Forming method of metal wiring in semiconductor device
JP2006351799A (en) * 2005-06-15 2006-12-28 Fuji Xerox Co Ltd Surface emitting semiconductor device array
KR101237633B1 (en) * 2005-12-27 2013-02-27 신에쓰 가가꾸 고교 가부시끼가이샤 Methods for Preparing Cellulose Ether

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480576B1 (en) * 1997-12-15 2005-05-16 삼성전자주식회사 Forming method of metal wiring in semiconductor device
US6417568B1 (en) 1999-03-12 2002-07-09 Nec Corporation Semiconductor device
KR20030050846A (en) * 2001-12-19 2003-06-25 주식회사 하이닉스반도체 Method for forming metal line of semiconductor
JP2006351799A (en) * 2005-06-15 2006-12-28 Fuji Xerox Co Ltd Surface emitting semiconductor device array
KR101237633B1 (en) * 2005-12-27 2013-02-27 신에쓰 가가꾸 고교 가부시끼가이샤 Methods for Preparing Cellulose Ether

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