JPH0574956A - Electrode structure for semiconductor device - Google Patents

Abstract

PURPOSE:To provide an electrode structure having high reliability by reducing a resistance value of an interlayer connecting hole in a semiconductor device having multilayer interconnections. CONSTITUTION:An interlayer connecting hole to be formed in a semiconductor device in which two more layers of interconnections 12, 18 made of Al or Al alloy are mounted is provided, the exposed interconnection 12 is covered with three layers 15, 16 and 17 made of Ti/TiN/Ti. Thus, a resistance value of substantially half that of prior art is provided for a high speed, and a circuit defect is prevented to provide an electrode structure having high reliability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention comprises a multi-layer wiring structure,
The present invention relates to an electrode structure of a semiconductor device that requires high reliability and high speed.

[0002]

2. Description of the Related Art In recent years, the number of output terminals of semiconductor elements, which have been increased in the degree of integration, has increased, so that the wiring cannot be made in a single layer.
At present, so-called multi-layer wiring is used, and the material of the wiring is not only Al but also Al-Si or Al-Si.
-Cu (hereinafter referred to as Al alloy layer) is also generally used.

By installing TiN / Ti below the second and subsequent wiring layers of such a multilayer wiring element, a second wiring layer is formed.
Layer wiring layer and a via hole (V
ia-Hall) is included to prevent stress migration and not to be used as an electrode.
TiN / Ti functions not as an electrode but as a wiring layer.

As a result, the resistance to the stress migration of the wiring layer is increased, but the Via resistance is increased.

Via holes (V
ia Hall) That is, in order to prevent a so-called punch-through phenomenon, a laminated metal layer made of Ti and Ti nitride, molybdenum silicide, or the like is formed in contact with the Al or Al alloy layer that forms the wiring layer. To achieve electrical continuity.

The process of forming such a wiring structure is as follows. That is, the semiconductor wafer transferred to a predetermined place in a dedicated sputtering apparatus is coated with Ti of about 200 Å by a sputtering process,
About 20 SCCM of nitrogen is introduced into the sputtering system to coat the Ti layer with about 700 Å thick TiN. Then, the semiconductor wafer is recovered and the multi-layer wiring process is performed.

FIG. 1 is a sectional view showing an electrode structure of a semiconductor device which has undergone such steps. That is, a semiconductor substrate 1 made of, for example, silicon is provided with an active element or a passive element by introducing and diffusing a predetermined impurity, and a so-called multi-layer wiring structure is prepared in preparation for an increase in the number of pins for this element. For this reason, an interlayer insulating layer 3 is formed between the first layer wiring 2 and the semiconductor substrate 1 to form a first wiring layer, and then a second insulating layer 4 covering the first layer wiring 2 is deposited. To do.

In order to further expose the first layer wiring 2, a second
An opening is provided in the insulator layer 4 by using a photolithography technique to form an exposed portion 5 of the first layer wiring 2.
After that, a method is adopted in which after the laminated structure of the Ti layer 7 / TiN layer 6 is installed, the second wiring layer 8 is covered to complete the electrode structure.

[0009]

As described above, Ti and Ti
It was found that the resistance of the interlayer connection hole and the resistance of the wiring layer are about 2 to 5 times higher than that of only Al when the multilayer wiring is formed using the interlayer connection hole of the N laminated structure. As a result, the circuit speed is lowered and a circuit failure occurs due to the difference between the design value and the manufactured device value.

The present invention has been made under such circumstances, and an object of the present invention is to provide a highly reliable electrode structure of a semiconductor element by providing a low resistance interlayer connection hole.

[0011]

A first interlayer insulating layer that covers a semiconductor substrate, a first wiring layer that is placed so as to overlap the interlayer insulating layer, and a first wiring layer that is disposed so as to cover the first wiring layer. Two
Interlayer insulating layer, a first wiring layer portion exposed by removing the second interlayer insulating layer, and Ti / TiN / Ti covering the first wiring layer portion and the second interlayer insulating layer. Layers,
The second wiring layer formed to cover the Ti / TiN / Ti layer is characterized by the electrode structure of the semiconductor device according to the present invention.

[0012]

In recent semiconductor device characteristics, not only the improvement of the degree of integration but also the speeding up has been a major goal, but the same applies to the device having a multilayer wiring structure. The present invention focuses on the resistance of the interlayer connection hole formed in the semiconductor element using the multi-layer wiring. When Ti / TiN / Ti is installed, Ti / Ti
It was completed based on the fact that it will be about 1/2 of N. Therefore, it is possible to prevent defects due to the speedup simulation of the circuit and the speed difference between the manufactured devices,
It is possible to prevent the electromigration of Al itself that constitutes the wiring layer by diffusion of Ti disposed immediately below the wiring layer.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described in detail with reference to FIGS. 2 to 4. FIG. 2 is a sectional view showing an electrode structure of a semiconductor device to which the present invention is applied. That is,
For example, a semiconductor substrate 1 made of silicon and showing the first conductivity type
In addition, an active element or a passive element is provided by introducing and diffusing impurities of the second conductivity type to form an electronic circuit. In order to form a so-called multilayer wiring structure corresponding to the number of terminals of this circuit, the first wiring layer 12 is formed so as to overlap the interlayer insulating layer 11 adhered to the surface of the semiconductor substrate 10. Al-Si-Cu is used as the material to prevent the punch-through phenomenon in the electrode described later. Of course, Al-Si or Al can be applied depending on the case.

After forming the first wiring layer 12, the entire surface is covered with the second insulating layer 13 functioning as an interlayer insulating layer,
The exposed portion 1 of the first wiring layer 12 is formed by providing an opening, that is, an interlayer connection hole by a known photolithography technique.
4 is formed.

Next, in the sputtering process using the sputtering apparatus shown in FIG. 3, the Ti layer 15 has a thickness of about 2
After forming about 00 Å / TiN layer 16 thickness of about 700 Å / Ti layer 17 thickness of about 200 Å, the second wiring layer 18 is covered.

As is apparent from FIG. 3, the sputtering apparatus for the sputtering process is naturally connected to a decompression apparatus to obtain a predetermined degree of vacuum, and of course a magnetic field apparatus (not shown) necessary for plasma formation. Alternatively, an inert gas necessary for sputtering, such as Ar, can be introduced. The semiconductor substrate 10 on which the exposed portion 14 of the first wiring layer 12 is formed is carried from the load chamber 20 to the sputtering region 19 in the sputtering device by the carrier device 21, and then the target 22 is sputtered under predetermined conditions. Ti layer 15 / TiN
Layer 16 / Ti layer 17 is coated.

After the first Ti layer 15 is deposited, an inert gas such as nitrogen is introduced into the sputtering region 19 in an amount of 20 SCCM, a predetermined process is performed, and then a TiN layer 16 is deposited. Then, nitrogen is similarly introduced in an amount of 20 SCCM. Then, the Ti layer 17 is deposited through the same operation.

In such a sputtering process, the target 22 is replaced to form a three-layer deposited film, and the target 22 is installed in another sputtering region (not shown) disposed adjacent to the sputtering region 19. A method of continuously using a target (not shown) made of a different material is also used.

It should be added that the sputtering apparatus shown in FIG. 3 is provided with the upper and lower deposition preventive plates 23 and the heater 24 and clarifies the minimum necessary parts.

As shown in FIG. 2, after the second wiring layer 18 is covered, a patterning process is performed by a known photolithography technique and the patterning process is performed to arrange the second wiring layer 18 at a necessary place.

[0021]

The resistance of the interlayer connection hole of the semiconductor element disclosed in the embodiment is the resistance (Ω) on the vertical axis of the logarithmic scale,
Although it is shown in FIG. 4 in which the dimension (μm) of the interlayer connection hole is taken on the horizontal axis of the decimal scale, Al—Si—Cu indicates the second wiring layer 18.

As is clear from this figure, the resistance value of the inter-layer connection hole according to the present invention is a very good value of about 1/2 as compared with the conventionally used TiN / Ti method.
Its effectiveness is clear.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an electrode structure of a conventional semiconductor device.

FIG. 2 is a sectional view showing an electrode structure of a semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing a main part of a sputtering apparatus applied to construct an electrode structure of a semiconductor device according to the present invention.

FIG. 4 is a characteristic diagram comparing the resistance of the electrode structure of the semiconductor device of the present invention with that of a conventional product.

[Explanation of symbols]

 1, 10: semiconductor substrate, 2, 12: first wiring layer, 3, 11: interlayer insulating layer, 13: second insulating layer, 6, 15, 16: Ti layer, 7, 16: TiN layer, 8 , 18: second wiring layer.

Claims (1)

[Claims] 1. A first interlayer insulating layer that covers a semiconductor substrate, a first wiring layer that covers the insulating layer, and a second interlayer insulating layer that is stacked on the first wiring layer. Layer, a first wiring layer exposed by removing the second interlayer insulating layer, and a Ti / TiN / Ti wiring layer covering the first wiring layer portion and the second interlayer insulating layer, Ti / Ti
Electrode structure of semiconductor element, comprising a second wiring layer formed so as to cover the N / Ti wiring layer