JP2817209B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of manufacturing a semiconductor device, particularly to a method of forming a silicon oxide-based insulating film which is directly laminated on a metal silicide pattern, and to an insulating method which does not exert a large tensile stress on the metal silicide layer. The purpose of the present invention is to provide a method for laminating a film and to prevent the metal silicide pattern from peeling off. When forming a metal silicide pattern in which a silicon oxide-based insulating film is directly laminated on the upper part, the silicon oxide-based insulating film is removed. The method includes forming a first silicon oxide-based insulating film formed by high-temperature chemical vapor deposition and a second silicon oxide-based insulating film formed by low-temperature chemical vapor deposition.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a silicon oxide-based insulating film directly laminated on a metal silicide pattern.

With the increase in the degree of integration of semiconductor devices, the width of the electrode wiring provided in the semiconductor device has been extremely reduced, and in such a state, the resistance of the electrode wiring has been reduced to reduce the operating speed. In order to prevent such a problem, for example, a silicide of a high melting point metal, that is, metal silicide, which can greatly reduce the resistance as compared with the conventional polysilicon, has been increasingly used for, for example, a gate electrode of a MOS transistor.

When this metal silicide is used for the gate electrode, a poly-Si layer is usually interposed under the metal silicide to prevent the refractory metal from diffusing into the gate oxide film from the metal silicide and causing threshold fluctuation and breakdown voltage deterioration. In the polycide structure, when the electrode width is reduced as described above, there is a problem that the silicide layer is peeled off from the poly-Si layer and the performance of the device is deteriorated. It is rare.

[Conventional technology]

Conventionally, MOS transistors having a polycide gate are:
It was formed by the method described below with reference to FIGS. 3 (a) to 3 (d).

FIG. 3A shows, for example, an element forming region 54 defined and defined by a field oxide film 52 and a p-type channel cut region 53 therebelow on a surface of a p ^- type silicon (Si) substrate 51, for example.
Is formed, a gate oxide film 55 is formed on the element formation region 54 by thermal oxidation or the like, and then a poly-Si layer (n) having a thickness of about 2000 mm is formed on the substrate by a chemical vapor deposition (CVD) method.
⁺ -Type) 56 after forming, the poly-Si layer having a thickness of about 1000Å by sputtering on 56 for example tungsten silicide (WSi ₂₎ layer 57 is formed, then on the WSi ₂ layer 57, for example, dichlorosilane (SiH ₂ Cl ₂ ) and 1 oxygenated 2 nitrogen (N ₂ O)
Is used as a growth gas to form a first impurity-blocking silicon dioxide (SiO ₂ ) film 58 having a thickness of about 1000 ° by low pressure chemical vapor deposition at a high temperature of about 750 to 850 ° C. The reason why the SiO ₂ film 58 grown at a high temperature is used is to enhance the adhesion to the WSi ₂ layer 57.

Then, referring to FIG. 3B, the first impurity block is formed by dry lithography using a resist pattern (not shown) as a mask and using, for example, methane trifluoride CHF ₃ as an etching gas.
The SiO ₂ film 58 is patterned, followed by carbon tetrafluoride (CF ₄ )
A WSi ₂ layer 57 with a gas mixture of oxygen and oxygen (O ₂ ) followed by 6
The poly-Si layer 56 is patterned by sulfur fluoride (SF ₆ ) or the like, and a poly-Si layer 56 and a WSi ₂ layer 57 are laminated, and a first impurity blocking SiO ₂ film 58 is laminated on the upper layer. A polycide gate electrode PG extending from over the gate oxide film 55 onto the field oxide film 52 is formed.

Here, due to the tensile stress exerted by the first impurity block SiO ₂ film 58 formed on the upper surface, WS
a i ₂ layer 57 warped WS to be peeled from the poly-Si layer 56
peeling failure of i ₂ layer 57 is sometimes frequently.

Next, as shown in FIG. 3 (c), a first impurity block on the gate electrode PG is formed.
Using the SiO ₂ film 58 as a mask, arsenic (A
s ⁺ ) is ion-implanted and activated to form an n ⁺ -type source region 59 and an n ⁺ -type drain region 60. Note that the activation process is often performed simultaneously with reflow of the interlayer insulating film in a later step.

Next, after removing the exposed gate oxide film 55, a thickness of 1000 .ANG. Is formed on the exposed surfaces of silicon and silicide by thermal oxidation.
A second SiO ₂ film 61 for impurity blocking is formed on the substrate, and then an interlayer insulating film 62 of about 3000 to 6000 mm thick made of phosphosilicate glass (PSG) is formed on this substrate by a CVD method. A contact window 63 that exposes the source and drain regions 59 and 60 is formed by lithography means, and the side surface of the contact window 63 is formed gently by reflow treatment of the interlayer insulating film 62. Then, an Al alloy or the like is formed on the substrate. A wiring material layer, and pattern the wiring material layer by ordinary photolithography to form a source wiring.
64 and the drain wiring 65 are formed.

Incidentally, the heat history at the time of forming the interlayer insulating film 62 also causes the WSi ₂ layer 57 in the gate electrode PG to be peeled off, which causes another problem that cracks occur in the interlayer insulating film 62. Was.

[Problems to be solved by the invention]

According to the conventional method as described above, in a semiconductor device having a polycide gate, a phenomenon in which the refractory metal layer constituting the polycide gate, for example, the WSi ₂ layer 57 is separated from the poly-Si layer occasionally frequently occurs, There is a problem that the performance is deteriorated, and the manufacturing yield and reliability of the semiconductor device are significantly reduced. Also, when the WSi ₂ layer is used for a lower wiring extending over the insulating film, peeling may occur due to tensile stress of the impurity blocking insulating film formed on the upper surface in the same manner as described above.

Accordingly, an object of the present invention is to provide a method for laminating an insulating film on a metal silicide layer that does not exert a large tensile stress on the metal silicide layer, and to prevent the metal silicide pattern from peeling off.

[Means for solving the problem]

The object is to form a silicon layer on a silicon substrate, form a metal silicide layer on the silicon layer, and form a first silicon oxide-based insulating film on the metal silicide layer by chemical vapor deposition. Forming a second silicon oxide-based insulating film on the first silicon oxide-based insulating film at a temperature lower than the growth temperature of the first silicon oxide-based insulating film by chemical vapor deposition. And then sequentially patterning the second and first silicon oxide-based insulating films, the metal silicide layer, and the polysilicon layer.

(Operation)

That is, in the method of the present invention, the silicon oxide-based insulating film directly laminated on the metal silicide pattern is formed into a two-layer structure, and dense film quality is ensured and high-temperature air having an excellent impurity blocking effect is obtained. It consists of a combination of a silicon oxide-based insulating film formed by phase growth and a silicon oxide-based insulating film formed by low-temperature vapor-phase growth that is slightly thicker because the blocking effect is slightly inferior. Prevents peeling from a substrate such as a layer or an insulating film.

It is considered that this is because the stress of the low-temperature vapor-growth insulating film acts in a direction to cancel the stress of the high-temperature vapor-growth insulating film, and the tensile stress exerted on the metal silicide film as a whole insulating film decreases.

〔Example〕

Hereinafter, the method of the present invention will be specifically described with reference to the drawings for an embodiment of a MOS transistor.

1 (a) to 1 (e) are sectional views showing the steps of an embodiment of the method of the present invention, and FIGS. 2 (a) to 2 (c) are the same as FIGS.
It is process sectional drawing of a 90-degree different direction.

 The same objects are denoted by the same reference symbols throughout the drawings.

When a MOS transistor having a polycide gate using, for example, WSi ₂ as an electrode material is formed by the method of the present invention, a field oxide film is formed on a p ^- type silicon (Si) 1 in the same manner as in the prior art. 2 and an element forming region 4 defined by a p-type channel cut region 3 thereunder. First, a gate oxide film 5 having a thickness of about 300.degree. To form

Referring to FIG. 1 (b), a normal chemical vapor deposition (CV) process is performed on the substrate to be processed.
D) For example, a poly-Si layer (n
After forming the ( ⁺ type) 6, a WSi ₂ layer 7 having a thickness of about 1000 ° is formed on the poly-Si layer 6 by sputtering, and then a mixed gas of, for example, SiH ₂ Cl ₂ and N ₂ O is used as a growth gas. The WSi ₂ layer 7 is formed on the WSi ₂ layer 7 by a low pressure chemical vapor deposition method of SiO ₂ performed at a high temperature of about 750 to 850 ° C. under a reduced pressure of 0.1 Torr or less.
高温 High-density Si with high density and excellent impurity blocking effect
The O ₂ film 8A is formed, and then the reduced pressure chemical reaction of SiO ₂ is performed at a low temperature of about 350 to 450 ° C. under a reduced pressure of about 1 to ₂ Torr using a mixed gas of monosilane (SiH ₄ ) and oxygen (O ₂ ) as a growth gas. On the above-mentioned high-temperature-grown SiO ₂ film 8A by vapor phase growth means,
A low-temperature-grown SiO ₂ film 8B that exerts a negative stress on the high-temperature-grown SiO ₂ film 8A of about 1000 ° is formed.

Both the high-temperature grown SiO ₂ film 8A and the low-temperature grown SiO ₂ film 8B function as the first impurity blocking SiO ₂ film 8. The low-temperature-grown SiO ₂ film 8B has a slightly lower impurity blocking effect than the high-temperature-grown SiO ₂ film 8A, but the total film pressure is increased to maintain the blocking effect more than before.

1 (c) and 2 (a) Next, a resist mask pattern (not shown) is formed on the low-temperature-grown SiO ₂ film 8B by a normal photo process, and reactive ion etching (RIE) is performed using this resist pattern as a mask. Low temperature grown SiO ₂ film 8B and high temperature grown S by processing
The iO ₂ film 8A, the WSi ₂ layer 7 and the poly-Si layer 6 are sequentially patterned to form a first low-temperature grown SiO ₂ film 8B and a high-temperature grown SiO ₂ film 8A.
WSi _{2 with} SiO ₂ film 8 for impurity blocking deposited on the upper surface
A polycide gate electrode PG composed of the layer 7 and the poly-Si layer 6 thereunder is formed. The etching gas used in the RIE process is, for example, CHF ₃ or WSi ₂ layer 7 for the SiO ₂ film 8.
[CF ₄ + O ₂ ] and SF ₆ for the poly-Si layer ₆ , respectively.

As in this embodiment, a first impurity-blocking SiO ₂ film 8 deposited on the WSi ₂ layer 7 is formed by a low-temperature-grown SiO ₂ film 8B and a high-temperature-grown SiO ₂ film 8B.
O ₂ when the two-layer structure consisting of the film 8A, a first impurity-block SiO ₂ film by patterning as above 8
When the polycide gate electrode PG is formed on the upper surface, the tensile stress exerted on the WSi ₂ layer 7 by the high-temperature grown SiO ₂ film 8A is weakened by the low-temperature grown SiO ₂ film 8B. _The tensile stress exerted on the WSi ₂ layer 7 as a whole of the _two films 8 is reduced, and the WSi ₂ layer 7 constituting the polycide gate electrode PG hardly peels off from the lower poly Si layer 6. This effect is due to the low temperature growth SiO ₂ film and the high temperature growth.
The same applies to the case where the stacking order of the SiO ₂ film is reversed. However, when the adhesion between the first impurity blocking SiO ₂ film 8 and the WSi ₂ layer 7 is taken into consideration, the stacking as in the above embodiment is performed. Order is preferred.

1 (d) and 2 (b) Next, arsenic (As ⁺ ) is ion-concentrated at a high concentration on the surface of the element forming region 4 through the gate oxide film 5 using the SiO ₂ film 8 for the first impurity block as a mask. The n ⁺ -type source region 9 and the n ⁺ -type drain region 10 are formed by performing implantation and performing a predetermined activation process. Note that the above activation may be performed at the same time as a heat treatment at the time of reflow treatment of the interlayer insulating film in a later step.

1 (e) and 2 (c) Next, after the exposed gate oxide film 5 is washed out with hydrofluoric acid or the like, the exposed surface of Si and WSi ₂ is exposed to thermal oxidation at a temperature of about 900 ° C., for example. A second SiO ₂ film 11 for impurity blocks having a thickness of about 1000 ° is formed, and then a normal 350-4
An interlayer insulating film 12 made of, for example, PSG and having a thickness of about 3000 to 5000 ° is formed on the substrate by a CVD process at 00 ° C., and the source region 9, the drain region 10, and the WSi ₂ layer 7 of the gate electrode PG are formed by ordinary photolithography. Form contact windows 13A, 13B, 13C that expose the surface, and for example, Al
Forming a wiring material layer made of an alloy, performing patterning by a usual method, forming a source wiring 14, a drain wiring 15 and a gate wiring 16 derived from the respective contact windows, and thereafter forming a covering insulating film (not shown). MOS having a polycide gate formed by the method of the present invention
The transistor is completed.

The thermal history of forming the second impurity-blocking SiO ₂ film 11, forming the interlayer insulating film 12, and forming a coating insulating film (not shown) also causes the polycide gate electrode PG There was no peeling of the WSi ₂ layer 7.

In the above embodiment, the present invention is applied to a metal silicide.
Although the polycide gate using WSi ₂ has been described, the present invention has the same effect when other metal silicide such as MoSi ₂ or TiSi ₂ is used.

Also, the present invention relates to WSi ₂ , MoS
It is also applied when forming a metal silicide wiring of i ₂ , TiSi ₂ or the like, and has an effect of increasing the peel strength from the insulating film.

〔The invention's effect〕

As described above, according to the present invention, the electrode wiring made of metal silicide is prevented from being peeled off from the lower poly-Si layer, the insulating film, or the like due to thermal history.

Therefore, the present invention is effective in improving the production yield and reliability of a semiconductor device using metal silicide for an electrode and a wiring.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (e) are sectional views showing steps of an embodiment of the method of the present invention, and FIGS. 2 (a) to 2 (c) show steps in different directions of the embodiment. Sectional views, FIGS. 3 (a) to 3 (d) are process sectional views of a conventional method. In the figure, 1 is a p ^- type Si substrate, 2 is a field oxide film, 3 is a p-type channel cut region, 4 is an element formation region, 5 is a gate oxide film, 6 is a poly Si layer, 7 is a WSi ₂ layer, 8 Is a SiO ₂ film for the first impurity block, 8A is a SiO ₂ film grown at a high temperature, 8B is a SiO ₂ film grown at a low temperature, 9 is an n ⁺ type source region, 10 is an n ⁺ type drain region, and 11 is a second impurity block. use SiO ₂ film, 12 denotes an interlayer insulating film, 13A, 13B, @ 13 C the contact window, 14 the source wiring, 15 denotes a drain wiring, 16 denotes a gate wiring.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/78 H01L 21/336 H01L 21/28 H01L 21/768

Claims (1)

(57) [Claims] A step of forming a silicon layer on a silicon substrate; a step of forming a metal silicide layer on the silicon layer; and forming a first silicon oxide-based insulating film on the metal silicide layer by chemical vapor deposition. Forming a second silicon oxide-based insulating film on the first silicon oxide-based insulating film at a temperature lower than the growth temperature of the first silicon oxide-based insulating film by chemical vapor deposition; A method of manufacturing a semiconductor device, comprising: a step of growing by growing; and a step of sequentially patterning the second and first silicon oxide-based insulating films, the metal silicide layer, and the polysilicon layer.