JPH0730103A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a manufacturing method for a semiconductor device which relaxes stress generating on the periphery of side wall edges and in the periphery of field oxide film edges and suppresses the generation of joint leaks when a side wall is formed on the sides of a gate electrode. CONSTITUTION:After a gate electrode 4 is formed by way of a gate oxide film 3 on a semiconductor substrate 1, a silicon oxide film 7 is deposited over the entire surface. Then, the silicon oxide film is subjected to etchback to form a side wall 8 within a range in which the shaving depth of the semiconductor substrate 1 is under 200Angstrom .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a MOS (Metal Oxide Semiconductor).
) A method for manufacturing a semiconductor device having a transistor structure.

[0002]

2. Description of the Related Art Conventionally, the gate length of a semiconductor device has become shorter with the miniaturization and higher integration of the semiconductor device. When the gate length becomes short, the electric field of the gate at the time of writing becomes extremely high even with the same writing voltage, carriers passing therethrough obtain high energy, and collision ionization occurs. This is called the hot carrier phenomenon, and M
The characteristic deterioration of the OS transistor was caused.

Therefore, in recent years, MOS type transistors having an LDD structure for suppressing the hot carrier phenomenon by weakening the electric field in the depletion layer at the ends of the source region and the drain region have been adopted. A MOS transistor having this LDD structure is generally formed by the following method.

After forming a gate electrode on a semiconductor substrate (silicon substrate) via a gate oxide film, a low concentration impurity is ion-implanted into the silicon substrate using the gate electrode as a mask to form source and drain gate electrodes. A low-concentration impurity diffusion layer is formed on the side edge. Next, a silicon oxide film is deposited on the entire surface by CVD as a sidewall forming material.
After the deposition by the method, the silicon oxide film is etched back until the portions corresponding to the source region and the drain region of the semiconductor substrate are exposed, and sidewalls are formed on the side surfaces of the gate electrode.

Next, oxidation is performed in an oxygen atmosphere or a water vapor atmosphere at about 800 to 900 ° C., and a thermal oxide film is formed on the entire surface as a silicon oxide film for ion implantation for forming a high concentration impurity diffusion layer. Next, this thermal oxide film is
A high-concentration impurity ion implantation is performed to form a source and a drain. A high-concentration impurity is ion-implanted into a silicon substrate using a gate electrode and a sidewall as a mask. Form. By this ion implantation, the portions corresponding to the source region and the drain region of the semiconductor substrate are made amorphous.

Next, after forming an interlayer insulating film on the entire surface, a heat treatment is performed to flatten the interlayer insulating film and activate the crystal recovery of the source region and the drain region. Next, a contact hole is opened at a desired position in the interlayer insulating film, a wiring material film is sputtered to fill the contact hole, and a metal wiring film is formed. Then, after patterning the metal wiring film, a final protective film is formed on the entire surface to complete a MOS type semiconductor device having an LDD structure.

A semiconductor device having a MOS transistor having this LDD structure has a structure in which a low-concentration impurity diffusion layer is formed at the end of the source region and the end of the drain region. The low-concentration impurity diffusion layer has the advantage that the electric field in this portion is weakened, hot carrier injection is suppressed, and the device life is improved.

[0008]

However, the above-mentioned L
In a method of manufacturing a semiconductor device including a MOS transistor having a DD structure, a portion corresponding to a source region and a drain region of a semiconductor substrate is over-etched during etch back performed when forming a sidewall on a side surface of a gate electrode. It is etched and greatly scraped. For this reason, a relatively large stress is generated around the edge of the sidewall and around the edge of the field oxide film (element isolation oxide film). Therefore, crystal defects are generated in the amorphous layer formed when the high-concentration impurity is ion-implanted in the source region and the drain region of the semiconductor substrate. Therefore, there is a problem that a junction leak occurs.

An object of the present invention is to solve such a conventional problem, and when forming a sidewall on a side surface of a gate electrode, a sidewall edge portion and a field oxide film edge portion are formed. An object of the present invention is to provide a method for manufacturing a semiconductor device in which stress generated around the semiconductor device is relaxed and the occurrence of junction leak is suppressed.

[0010]

In order to achieve this object, the present invention is to form a gate electrode on a semiconductor substrate through a gate oxide film and then deposit a sidewall forming material over the entire surface of the semiconductor substrate. In the method for manufacturing a semiconductor device, in which a sidewall is formed on the side surface of the gate electrode by etching back until exposed, the etching back is performed within a range in which the exposed semiconductor substrate has a shaving depth of 200 Å or less. The present invention provides a method for manufacturing a semiconductor device, which is characterized in that it is performed.

[0011]

According to the present invention, the etching back for forming the sidewall on the side surface of the gate electrode is performed within the range in which the shaving depth of the semiconductor substrate is 200 Å or less. The stress generated around the periphery and the edge of the field oxide film is relaxed. Therefore, it is possible to suppress occurrence of crystal defects in the amorphous layer formed when the high concentration impurities are ion-implanted into the source region and the drain region of the semiconductor substrate.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment according to the present invention will be described with reference to the drawings. 1 to 5 are partial cross-sectional views showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention. In the step shown in FIG. 1, the semiconductor substrate 1 is selectively oxidized to form a field oxide film 2 in the element isolation region. Next, a gate oxide film 3 having a film thickness of about 150 Å is formed on the entire surface. Then, on the gate oxide film 3, 3500
After depositing a polycrystalline silicon film with a film thickness of about Å, this is patterned to form the gate electrode 4.

Next, using the gate electrode 4 as a mask, an acceleration voltage = 50 KeV and an implantation amount = 2 × 10 3 are applied to the semiconductor substrate 1.
Phosphorus (P) is ion-implanted at ¹³ cm ^-2 to form low-concentration impurity regions 5 and 6. Next, in the step shown in FIG. 2, a mixed gas of monosilane (SiH ₄ ) and nitrous oxide (N ₂ O) is used as a source gas, and the temperature is 82.
CVD (Chemical Vap) under the conditions of 5 ° C. and pressure = 100 Pa
or Deposition) method, and a film thickness of 220 is formed on the surface of the gate oxide film 3 and the surface of the gate electrode 4 obtained in the step shown in FIG.
A silicon oxide film 7 of about 0Å is deposited.

Next, in the step shown in FIG. 3, the silicon oxide film 7 obtained in the step shown in FIG. 2 is etched back (reactive ion) until the portions corresponding to the source region and the drain region of the semiconductor substrate 1 are exposed. Etching) is performed to form sidewalls 8 made of the silicon oxide film 7 on the side surfaces of the gate electrode 4. At this time, in the etch back, as shown in FIG. 6, the end point was controlled so that the cut depth d of the exposed semiconductor substrate 1 was 200 Å or less.

The etch back is performed by carbon tetrafluoride (CF ₄ ) = 10 sccm, trifluoromethane (CH 3).
F ₃ ) = 30 sccm, Argon (Ar) = 1000 s
It was performed under the conditions of ccm, pressure = 2 Torr, and RF power = 300 W. At this time, the etching rate for the silicon oxide film 7 = 3000 Å / min, the etching rate for the semiconductor substrate (silicon) 1 = 300 Å / min
Met. Then, the end point control of the etch back is performed by monitoring the emission wavelength (4825Å) of carbon monoxide (CO) generated during the etch back of the silicon oxide film 7 and determining the emission intensity decrease start time by the over etching of the semiconductor substrate 1. As the time (scraping time), the scraping depth d of the semiconductor substrate 1 was obtained from the etching rate for the semiconductor substrate 1.

Next, in the step shown in FIG. 4, the semiconductor substrate 1 obtained in the step shown in FIG. 3 is oxidized in an oxygen (O ₂ ) gas atmosphere at 900 ° C. to expose the exposed source and drain regions. A silicon oxide film 13 having a film thickness of about 100Å is formed on the gate electrode 4. Next, using the gate electrode 4 and the sidewall 8 as a mask, the semiconductor substrate 1 is
Acceleration voltage = 40 KeV, injection amount = 3 × 10 ¹³ cm ⁻² ,
Arsenic (As) is ion-implanted to form high concentration impurity regions 9 and 11. In this way, the low concentration impurity region 5
A source 10 made of the high concentration impurity region 9 and a drain 12 made of the low concentration impurity region 6 and the high concentration impurity region 11 were formed.

Next, in the step shown in FIG. 5, an interlayer insulating film 14 is formed on the entire surface of the semiconductor substrate 1 obtained in the step shown in FIG. Next, a heat treatment is performed at 800 ° C. for 15 minutes, which also serves to planarize the interlayer insulating film 14 and activate the source 10 and the drain 12. After that, desired steps such as opening of contact holes and formation of metal wiring are performed to form an MO having an LDD structure.
A semiconductor device having an S transistor is completed.

Next, in the process shown in FIG. 3 of the first embodiment, the etching depth d of the semiconductor substrate 1 exposed during the etching back for forming the sidewall 8 becomes the value shown in Table 1. Except for the above control, seven types of semiconductor devices were manufactured according to the manufacturing process shown in the first embodiment. However, gate length =
The width was 0.8 μm and the gate width was 16 μm. Next, for each semiconductor device, the occurrence rate of defective junction leak was evaluated by the method described below.

A voltage of 7 V is applied (reverse bias is applied) to the drain 12 of each semiconductor device, and the leak current (junction leak current) between the drain 12 and the semiconductor substrate 1 is measured. The leak current value exceeds 15 pA. The thing was judged to be defective.
The results are shown in Table 1.

[0020]

[Table 1]

From Table 1, the abrasion depth d of the semiconductor substrate 1 is
The semiconductor device having a thickness of 200 Å or less had no junction leakage defect and good results were obtained. This is because the formation of the sidewalls 8 relaxed the stress generated around the edges of the sidewalls 8 and around the edges of the field oxide film 2. Therefore, high-concentration impurities were ion-implanted into the source 10 and the drain 12. This is because the occurrence of crystal defects in the amorphous layer formed at this time was suppressed.

On the other hand, the abrasion depth d of the semiconductor substrate 1 is 20
It was confirmed that a junction leak defect occurred in the semiconductor device having a thickness of more than 0 Å. This is because when the semiconductor substrate 1 is over-etched beyond a certain depth (200 Å), a large stress is generated around the edges of the sidewalls 8 and around the edges of the field oxide film 2, causing the source 10 and the drain to drain. 1
Secondly, this is because crystal defects are generated in the amorphous layer formed when the high-concentration impurities are ion-implanted.

Although P and As are ion-implanted when the source 10 and the drain 12 are formed in this embodiment, the present invention is not limited to this, and other n-type impurities may be ion-implanted. Moreover, the implantation amount and the acceleration voltage at the time of ion implantation may be determined as desired. Further, in this embodiment, n
Although the case of manufacturing the semiconductor device including the MOS transistor of the channel LDD structure has been described, the present invention can be applied to the case of manufacturing the semiconductor device including the MOS transistor of the p channel LDD structure. Is.

[0024]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the etching back performed when the sidewall is formed on the side surface of the gate electrode is performed by the etching depth of the semiconductor substrate. Since it is performed within the range of 200 Å or less, the stress generated around the sidewall edge portion and the field oxide film edge portion can be relaxed. Therefore, it is possible to suppress the occurrence of crystal defects in the amorphous layer formed when the high concentration impurities are ion-implanted into the source region and the drain region of the semiconductor substrate.
As a result, it is possible to prevent the occurrence of defective junction leakage and to manufacture a semiconductor device having high performance and excellent reliability.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing a part of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a partial sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 6 is a partial enlarged cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 low concentration impurity region 6 low concentration impurity region 7 silicon oxide film 8 sidewall 9 high concentration impurity region 10 source 11 high concentration impurity region 12 drain 13 silicon oxide film 14 Interlayer insulation film

Claims (1)

[Claims] 1. A gate electrode is formed on a semiconductor substrate via a gate oxide film, and then a sidewall forming material deposited on the entire surface is etched back until the semiconductor substrate is exposed to form a side surface on the side surface of the gate electrode. In the method of manufacturing a semiconductor device in which a wall is formed, the etch back is performed within a range in which a depth of abrasion of the exposed semiconductor substrate is 200 Å or less.