JP3099813B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a low dielectric constant insulating film is formed between fine wirings.

[0002]

2. Description of the Related Art The operating speed of a semiconductor device is determined by a product RC (time constant) of a wiring resistance (R) and a parasitic capacitance (C) between wirings.
And the parasitic capacitance (C) between the wirings increases in inverse proportion to the wiring interval. Therefore, in order to improve the operation speed of a semiconductor device, it is important to reduce a parasitic capacitance between wirings. From such a viewpoint, spin-on-glass (Spi) having a low dielectric constant between fine wirings
A technique for forming an nOn Glass (SOG) film is widely used.

FIGS. 16 to 19 are process sectional views showing a conventional method of manufacturing a semiconductor device including a SOG film forming process.

First, as shown in FIG. 16, after a predetermined semiconductor element (not shown) is formed on the surface of a silicon substrate 1, Si
A base insulating film 2 made of O ₂ is deposited. Next, a film thickness of 40 n
A titanium film 3 having a thickness of m, an aluminum-copper alloy film 4 having a thickness of 500 nm, and a titanium nitride film 5 having a thickness of 30 nm are sequentially laminated by a sputtering method to form a laminated metal film having a thickness of 570 nm. Next, metal wiring is formed by patterning by a known method. Minimum space between metal wiring is about 0.3μ
m.

Next, as shown in FIG. 17, an SOG film 10 is applied on the patterned metal wiring. A silicon oxide film of about 30 nm may be formed between the titanium nitride film 5 and the SOG film 10 as an adhesion layer. However, it is necessary to reduce the film thickness because it serves as an adhesion layer, and is usually 50 nm or less.

[0006] Subsequently, as shown in FIG.
An interlayer insulating film 6 made of O ₂ is formed.

Thereafter, as shown in FIG. 19, via holes 11a to 11c are formed by using a photolithography technique and a dry etching technique, and oxygen ashing is performed.

Thereafter, after forming a barrier metal layer on the entire surface, a tungsten film is buried, and an upper layer wiring (not shown) is further formed thereon to complete a semiconductor device having a multilayer wiring structure.

[0009]

However, in the above prior art, as shown in the right side encircled portion of FIG. 19, the SOG film remains at the bottom of the via hole formed on the large-area metal wiring,
In some cases, conduction failure occurred.

This is for the following reason. When a coating material such as an SOG film is used, the coating thickness differs between a metal wiring portion having a fine metal film and a metal wiring portion having a large area. The large area portion is thicker than the fine portion. Therefore, when a via hole is formed by reactive ion etching, the SOG film remains at the bottom of the via hole formed on the large-area aluminum-copper alloy film 4 as shown in FIG. In particular, when a fine hole having a size of 0.3 μm or less is formed, the etching rate of the SOG film becomes extremely slow in a miniaturized metal wiring portion due to a microloading effect.

On the other hand, if overetching is performed to prevent such an SOG film from remaining, the SOG film on the side wall of the metal part immediately below the hole is etched in the part where misalignment between the via hole and the metal part occurs. A slit is formed at this location (surrounded portion on the left side in FIG. 19). When such a slit occurs, the hole filling property becomes poor due to the generation of gas from the SOG film or the like, and the reliability of the element decreases. Recently, so-called borderless wiring, in which the hole diameter and the metal wiring width are equal to each other, has been increasing for the purpose of miniaturization of the element. In such a case, the above-mentioned problem becomes particularly remarkable.

In the above prior art, a thick portion of the SOG film may be formed on the upper portion or near the side surface of the large-area wiring portion, and the internal stress (tensile stress) increases at this portion to cause cracks. There was something.

The present invention solves the above-mentioned problems of the prior art, which prevents the SOG film from remaining at the bottom of the via hole, prevents the occurrence of slits on the side surfaces of the metal wiring, and provides good burying property and good conductivity. It is an object of the present invention to provide a method for forming a via hole. It is another object of the present invention to provide a method for forming a via hole in a self-aligned manner.

[0014]

According to the present invention for solving the above problems, (A) a step of forming a metal film and a first interlayer insulating film on a semiconductor substrate in this order; Patterning a first interlayer insulating film and the metal film by etching to form a metal wiring made of the metal film; and (C) forming an SOG film and a second interlayer insulating film on the entire surface in this order. (D) removing at least the SOG film formed on the first interlayer insulating film and a part of the second interlayer insulating film; and (E) removing the first interlayer insulating film. And forming a plurality of via holes reaching the metal wiring.

According to the invention, (A) a step of forming a metal film and a first film in this order on a semiconductor substrate;
(B) a step of patterning the first film and the metal film by etching to form a metal wiring made of the metal film; and (C) forming an SOG film and a second film on the entire surface in this order. (D) removing at least the SOG film formed on the first film and a part of the second film; and (E) etching the first film, Forming a plurality of via holes reaching the metal wiring.

The configuration and operation of the present invention will be described below with reference to the drawings.

As described above, in the conventional manufacturing method,
After patterning the wiring by etching the metal film, the SOG film has been formed directly or, if desired, via an adhesion layer (thin silicon oxide film). Therefore, the SOG film remains after the formation of the via hole due to the unevenness of the thickness of the SOG film on the metal wiring (FIG. 19). On the other hand, in the manufacturing method of the present invention, first, a metal film and a first film or a first interlayer insulating film are formed in this order on the entire surface of a semiconductor substrate, and then these are etched to A metal wiring made of a metal film is formed. Thereafter, an SOG film is applied. Therefore, the layer structure above the metal wiring has a structure in which the first interlayer insulating film 6 is interposed between the metal wiring (aluminum-copper alloy film 4) and the SOG film 10, as shown in FIG. Since the SOG film 10 on the metal wiring is removed in the later flattening step (D), at the stage immediately before forming a via hole,
There is no longer SO on the metal wiring (aluminum-copper alloy film 4)
The G film 10 does not exist (FIG. 8). For this reason, the SOG film, which is a problem in the related art, does not remain.

In the prior art, the SOG film is exposed on the inner wall of the via hole on the large-area metal wiring (FIG. 1).
9, via holes 11c) and the generation of gas from the SOG film generate "spots", which causes a problem that the filling property is deteriorated. In this regard, according to the manufacturing method of the present invention, as described above, the SOG film 10 on the metal wiring has already been removed immediately before the via hole is formed. Therefore,
SOG on the inner wall of via hole on the formed large area metal wiring
The film is not exposed (via hole 11c in FIG. 9). Therefore, the problem of deterioration of the embedding property is solved.

[0019]

(First Embodiment) A first embodiment of the present invention.
Will be described with reference to FIGS.

First, as shown in FIGS. 1 and 2, a metal film and a first interlayer insulating film 6 are formed in this order on a semiconductor substrate (silicon substrate 1). Here, a titanium film 3 as a metal film,
Although a laminated film including the aluminum-copper alloy film 4 and the titanium nitride film 5 is used, the present invention is not limited to this. Here, the thickness of the first interlayer insulating film needs to be equal to or greater than the thickness of the interlayer insulating film to be finally obtained. This is because it is removed in the subsequent flattening step, and the film thickness may be reduced. For example, 5 to 100 times more than the finally obtained interlayer insulating film.
Thicken about nm. On the other hand, there is no particular upper limit to the film thickness, but there is no particular advantage even if the film thickness is too large. Since the final thickness of the interlayer insulating film is usually 250 nm or more, the thickness of the first interlayer insulating film is preferably 250 nm or more, more preferably 300 to 3000 nm.

Next, the first interlayer insulating film 6 and the metal film are patterned by etching to form a metal wiring made of the metal film (FIG. 5).

Subsequently, an SOG film 10 is formed on the entire surface (FIG. 6). The type of the SOG film is not particularly limited.
G film, organic SOG film, HSQ (Hydrogen Silisesquioxa)
ne) A film or the like can be used. Considering the balance of performance such as dielectric constant and gas generation, HSQ film, organic SO
A G film is preferably used.

Here, the HSQ film has a structure represented by the following formula (1). The relative permittivity is 3.0.

[0024]

Embedded image

On the other hand, the organic SOG film has a structure in which a methyl group (CH ₃ —) or the like is bonded to silicon oxide. The relative dielectric constant of the organic SOG film decreases as the organic component content increases, and a dielectric constant of about 2.7 can be obtained.

Next, a second interlayer insulating film 8 is formed on the entire surface so as to bury the metal wiring and the SOG film 10 (FIG. 7).

Thereafter, at least the SOG film 10 formed on the first interlayer insulating film and a part of the second interlayer insulating film are removed (FIG. 8). Through this step, the semiconductor layer on the substrate is planarized. The removal method is a chemical mechanical polishing (Chemical Mechanical Polish).
(shing, CMP), dry etching, or the like. In this step, a part of the first interlayer insulating film 6 may be removed.

The thickness of the first interlayer insulating film 6 in the state of FIG. 8 is the thickness of the interlayer insulating film of the finally obtained semiconductor device. For this reason, the film thickness when the first interlayer insulating film 6 is first formed (the step of FIG. 2) needs to be equal to or greater than the thickness of the interlayer insulating film of the finally obtained semiconductor device.

Subsequently, after the formation of the photoresist 9, the first interlayer insulating film 6 is etched to form a plurality of via holes 11a to 11c reaching the metal wiring (FIG. 9). In this step, a part of the second interlayer insulating film other than the first interlayer insulating film may be etched. After removing the photoresist (FIG. 10A), a barrier metal layer (not shown) is formed, and the tungsten film 12 is embedded in the via hole. Further, after a metal film made of an aluminum-copper alloy film or the like is formed thereon, the upper wiring 13 is formed using photolithography and dry etching techniques, thereby completing a semiconductor device having a multilayer wiring structure (FIG. 10).
(B)).

In this embodiment, the first interlayer insulating film and the second interlayer insulating film may be the same or different. For example, both the first interlayer insulating film and the second interlayer insulating film can be a silicon oxide film or a silicon nitride film.

One of the first interlayer insulating film and the second interlayer insulating film may be a silicon oxynitride film, and the other may be a silicon oxide film. By doing so, a high etching selectivity can be obtained between the constituent material of the hole forming region and the constituent material of the other region,
As a result, via holes can be formed in a self-aligned manner. In this case, the etching for forming the via hole is preferably performed by wet etching with phosphoric acid, for example. This is because the etching selectivity can be increased.

(Second Embodiment) A second embodiment of the present invention will be described with reference to the drawings.

In this embodiment, the first interlayer insulating film 6 in the first embodiment is a first film 6 ', and the second interlayer insulating film 8 is a second film 8'. It is preferable that the first film 6 'and the second film 8' be a combination having greatly different etching rates. For example, one of the first film and the second film is a polycrystalline silicon film, and the other is a silicon oxide film or a silicon nitride film.

First, in the same manner as in the first embodiment, a metal wiring is formed, a first film 6 ', an SOG film 10 and a second film 8' are formed, and then the surface is flattened (FIG. 11).

Subsequently, after the formation of the photoresist 9, the first film 6 'is etched to form a plurality of via holes 11a to 11c reaching the metal wiring (FIG. 12). As the etching gas, a mixed gas containing HBr, Cl ₂ , and O ₂ can be preferably used. Polycrystalline silicon first film 6 '
Since the etching rates of the second film 8 'and the second film 8' are significantly different, the first film 6 'is selectively etched when the via hole is formed, and the second film 8' is hardly etched. Therefore, via holes are formed in a self-aligned manner. FIG. 13A illustrates this. As shown in the figure, even when the opening of the photoresist 9 is formed at a position slightly shifted from the formation region of the via hole 11, substantially only the first film 6 'is etched due to the difference in the etching rate, and the via hole is removed. It is formed in a self-aligned manner. Therefore, even if the opening of the photoresist 9 is made larger than the diameter of the via hole 11, a hole having a desired diameter can be obtained, and as shown in FIG. It may be opened.

In the case where one of the first film 6 'and the second film 8' is made of a material other than an insulating film, for example, polycrystalline silicon or the like, the polycrystalline silicon is formed by means such as heat treatment after forming a via hole. Process to convert the
It functions as an interlayer insulating film.

Thereafter, the photoresist is peeled off (FIG. 1).
4), a barrier metal layer is formed, and a tungsten film is buried in the via hole (not shown). After forming a metal film such as an aluminum-copper alloy film on the upper layer,
An upper layer wiring (not shown) is formed by using photolithography technology and dry etching technology to complete a semiconductor device having a multilayer wiring structure.

In the present invention, when an HSQ film is used as the SOG film, it is preferable to perform a heat treatment after forming the HSQ film in an atmosphere from which oxygen and water have been removed. By performing such a heat treatment, the SO at the time of forming a via hole later can be formed.
It is possible to reduce the etching rate of the G film and prevent the occurrence of a slit on the side surface of the metal wiring. At this time, the temperature of the heat treatment is preferably set to 350 to 500 ° C. If the temperature exceeds 500 ° C., the chemical bond between Si and H is broken, and the dielectric constant of the HSQ film may increase. 350 ° C
If it is less than 1, cracks may occur in the insulating film formed on the SOG film. Note that "under an atmosphere from which oxygen and water have been removed" means that oxygen and water contained in the atmosphere are substantially completely removed by an operation such as once evacuating the processing atmosphere. For example, such a state can be realized by applying a high vacuum of about 10 ⁻⁸ or more. After that, a heat treatment may be performed after introducing an inert gas to a predetermined pressure.

The method of manufacturing a semiconductor device according to the present invention is particularly suitable when at least a part of the plurality of via holes has a diameter substantially equal to the width of a metal wiring connected to the via hole, that is, when a borderless wiring is included. It is valid. This is because the problems of the SOG film remaining at the bottom of the via hole and the occurrence of slits on the side surfaces of the metal wiring, which are problems to be solved by the present invention, are particularly significant when borderless wiring is formed. Note that borderless wiring is applied
This is the case where the minimum distance between the lower wirings is 0.3 μm or less.

[0040]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1 to 10 are process cross-sectional views of a method of manufacturing a semiconductor device according to this embodiment.

As shown in FIG. 1, first, a silicon substrate 1
After forming a predetermined semiconductor element on the surface (not shown), B
A base insulating film 2 made of PSG (Boro Phospho Silicate Glass) was formed by a plasma CVD method. Next, a titanium film 3 having a thickness of 40 nm, an aluminum-copper alloy film 4 having a thickness of 500 nm, and a titanium nitride film 5 having a thickness of 30 nm were sequentially laminated by a sputtering method to form a laminated metal film having a thickness of 570 nm.

Next, as shown in FIG. 2, a first interlayer insulating film 6 made of BPSG was formed on the titanium nitride film 5 by a plasma CVD method. The thickness was 800 nm.

Subsequently, as shown in FIG. 3, after forming a photoresist 7 on the first interlayer insulating film 6, the first interlayer insulating film 6 was dry-etched using this as a mask. For the etching, a mixed gas containing C ₄ F ₈ , Ar, O ₂ and CO was used.

After the photoresist 7 is stripped (FIG. 4), the laminated metal film composed of the titanium film 3, the aluminum-copper alloy film 4, and the titanium nitride film 5 is etched using the first interlayer insulating film 6 as a mask to form a metal wiring. (FIG. 5). For the etching, a mixed gas containing Cl ₂ and CF ₄ was used.
The wiring interval of the fine wiring section (the wiring interval on the left in the figure) is about 0.3
μm. In addition, the width of the large-area wiring portion (the right wiring width in the figure) was set to about 500 μm.

Subsequently, as shown in FIG.
The G film 10 was applied to about 500 nm. This coating thickness is a value of the maximum thickness part. HSQ was used as the material of the SOG film 10. The SOG film 10 is formed with a small thickness on the first interlayer insulating film 6 of the fine wiring on the left in the figure, and has a large film thickness on the first interlayer insulating film 6 in the large area on the right in the figure. Is formed.

After coating the HSQ film, 15 hours on a hot plate
Heat treatment was sequentially performed at 0 ° C., 250 ° C., and 350 ° C. The heat treatment time was 1 minute in each case. Thereafter, the following heat treatment was further performed. Once the processing atmosphere is 10 ^-8
After applying a high vacuum to about 3mT, 3mT
orr pressure. Heat treatment was performed at 480 ° C. for 5 minutes in this vacuum atmosphere. Here, the reason why the high vacuum is once set to about 10 ⁻⁸ is that oxygen and water contained in the atmosphere are substantially completely removed. By performing such heat treatment, the etching rate of the HSQ film at the time of forming a via hole later is reduced, and the etching rate is equal to that of the first interlayer insulating film 6 and the second interlayer insulating film 8 made of a silicon oxide film. can do. Thereby, it is possible to prevent the occurrence of a slit or the like on the side surface of the metal wiring.

Next, as shown in FIG.
A second interlayer insulating film 8 made of BPSG was formed by the method. The film thickness was 1400 nm.

Thereafter, the second interlayer insulating film 8, the SOG film 10, and the first interlayer insulating film 6 are formed by using a chemical mechanical polishing method.
Was polished to flatten the surface (FIG. 8). At this time, the polishing was performed so that the SOG film 10 on the first interlayer insulating film 6 was completely removed and a part of the upper portion of the first interlayer insulating film 6 was further removed. Thereby, the thickness of the interlayer insulating film 6 is set to 600 n
m. In this state, the SOG film on the aluminum-copper alloy film 4 constituting the metal wiring is substantially completely removed.

Subsequently, as shown in FIG. 9, after a photoresist 9 was formed on the first interlayer insulating film 6, dry etching was performed using the photoresist 9 as a mask to form a via hole 11. For the etching, a mixed gas containing C ₄ F ₈ , Ar, and O ₂ was used. FIG. 9 shows a state in which misalignment of the photoresist 9 slightly occurs. The titanium nitride film 5 at the bottom of the via hole was completely removed by etching, and the surface of the aluminum-copper alloy film 4 was exposed. FIG. 10 (a)
FIG. 4 is a view showing a state where a photoresist is removed.

Thereafter, a barrier metal layer (not shown) is formed on the entire surface.
After the formation, the tungsten film 12 is deposited and etched back so that the tungsten film 12 is formed only in the via hole.
Was embedded. Further, after forming a metal film made of an aluminum-copper alloy film or the like on the upper layer, the upper layer wiring 13 is formed using photolithography technology and dry etching technology, thereby completing a semiconductor device having a two-layer wiring structure ( FIG. 10 (b)). Via conduction of the manufactured semiconductor device was good on both large-area metal wirings and fine-area metal wirings, and no cracks were observed.

(Embodiment 2) In the first embodiment, both the first interlayer insulating film 6 and the second interlayer insulating film 8 are made of silicon oxide films. To a first film 6 'made of a polycrystalline silicon film and a second interlayer insulating film 8
Was used as a second film 8 ′ made of a silicon oxide film. As a result, a via hole was formed in a self-aligned manner above the metal wiring.

First, a base insulating film 2 made of BPSG and a film thickness of 40 nm were formed on the surface of the silicon substrate 1 in the same manner as in the first embodiment.
Titanium film 3, aluminum-copper alloy film 4 having a thickness of 500 nm,
A titanium nitride film 5 having a thickness of 30 nm was formed in this order. Next, a non-doped polycrystalline silicon film was formed thereon as a first film 6 ′ by using a plasma CVD method. The thickness was 800 nm.

After forming the photoresist, HBr, Cl ₂ ,
The first film 6 ′ is etched using a mixed gas containing O ₂ , and furthermore, Cl ₂ , CF ₄
The titanium film 3, the aluminum-copper alloy film 4, and the titanium nitride film 5 were etched using a mixed gas containing, and a metal wiring was patterned (not shown). The wiring interval of the miniaturized wiring part was about 0.3 μm, and the width of the large area wiring part (the wiring width on the right in the figure) was about 500 μm.

Thereafter, in the same manner as in Example 1, application and heat treatment of an HSG film, formation of a second film 8 'made of BPSG, and planarization by CMP were performed. This state is shown in FIG.

After the formation of the photoresist 9,
Dry etching was performed to form a via hole 11 (FIG. 12). For the etching, a mixed gas containing HBr, Cl ₂ , and O ₂ was used. Here, the state immediately before the formation of the via hole is as shown in FIG. A first film 6 'made of polycrystalline silicon is formed on the aluminum-copper alloy film 4 constituting the metal wiring, and a second film 8' made of BPSG is formed on the SOG film 10. I have. That is, the fine wiring portion (borderless wiring portion) on the left side in the drawing has a form in which polycrystalline silicon is buried only in a portion where a via hole is formed. When the above-mentioned etching gas is used, the etching rate of polycrystalline silicon is much higher than that of BPSG. Therefore, even if misalignment of the photoresist 9 occurs in FIG. 12, the via hole of the fine wiring portion can be formed in a self-aligned manner.

Since the via holes in the fine wiring portion can be formed in a self-aligned manner, the following effects can be obtained.
When the interlayer insulating film is formed of a single material, a slit may be generated on the side surface of the fine metal wiring due to misalignment of the photoresist. For example, in the prior art shown in FIG. 19, when overetching is performed to remove the via hole bottom SOG film 10 in the large-area wiring portion located on the right in the drawing, a slit is generated on the side surface of the fine metal wiring on the left in the drawing. . Further, in the manufacturing method of the first embodiment, since the SOG film 10 does not remain at the bottom of the via hole, the over-etching time can be shortened, and such a problem does not occur so much. Depending on the case, a shallow slit may occur (Fig. 1
5). In this regard, according to the method of the present embodiment, the second film 8 ′
Since the silicon oxide film of the constituent material of (1) has a lower etching rate and a higher selectivity than the polycrystalline silicon film of the constituent material of the first film 6 ', the second film 8 in the via hole as shown in FIG. 'Remains almost unetched. Thus, the progress of etching of the SOG film 10 on the side surface of the fine metal wiring (aluminum-copper alloy film 4) at the time of over-etching can be prevented. In the figure, the SOG film 10 is applied thicker than the aluminum-copper alloy film 4 between the wirings. Further, in this case, the exposed portion of the SOG film 10 on the side surface of the via hole can be further reduced, gas generation can be suppressed, and defective filling of the hole can be more effectively prevented.

Thereafter, a heat treatment was performed in an oxygen-containing atmosphere to convert the polycrystalline silicon into a silicon oxide film. Next, after forming a barrier metal layer on the entire surface, a tungsten film is deposited, and etched back to bury the tungsten film only in the via hole (not shown).
Further, after a metal film made of an aluminum-copper alloy film or the like is formed thereon, an upper layer wiring (not shown) is formed by using a photolithography technique and a dry etching technique. completed. Via conduction of the manufactured semiconductor device was good on both large-area metal wirings and fine-area metal wirings, and no cracks were observed.

(Example 3) A two-layer wiring structure was formed in the same manner as in Example 1 except that the first interlayer insulating film 6 was a silicon oxide film and the second interlayer insulating film 8 was a silicon oxynitride film. Having completed the semiconductor device. When forming a borderless wiring, a via hole could be formed in a self-aligned manner above the metal wiring due to a difference in etching rate between the silicon oxide film and the silicon oxynitride film. Via conduction of the manufactured semiconductor device was good on both large-area metal wirings and fine-area metal wirings, and no cracks were observed.

Example 4 A semiconductor device having a two-layer wiring structure was completed by substantially the same steps as in Example 1. 3 in that the first interlayer insulating film 6 is a silicon oxynitride film and the second interlayer insulating film 8 is a silicon oxide film, and that the first interlayer insulating film 6 in the process of FIG. Are different from each other in that the etching gas used in the etching is changed, and the via holes are formed by wet etching. The etching gas for the first interlayer insulating film 6 was a mixed gas containing CHF ₃ O ₂ . The via holes were formed by wet etching using phosphoric acid. At this time, the temperature was about 120 ° C.

According to the method of this embodiment, a via hole can be formed in a self-aligned manner above a metal wiring when forming a borderless wiring. This is because the etching rates of the silicon oxide film and the silicon oxynitride film are greatly different in the etching for forming the via hole. Via conduction of the manufactured semiconductor device was good on both large-area metal wirings and fine-area metal wirings, and no cracks were observed.

In each of the above embodiments, only an example of a two-layer structure is shown, but it is needless to say that the present invention can be applied to a multilayer structure of three or more layers.

[0063]

As described above, according to the present invention, since the SOG film is applied after forming the first interlayer insulating film on the metal wiring, the following effects can be obtained.

The first effect is that S at the bottom of the via hole
The purpose is to prevent the OG film from remaining and obtain a good conductive via hole. This is because the SOG film on the metal wiring has already been removed immediately before the formation of the via hole.

The second effect is that the occurrence of slits on the side surfaces of the metal wiring can be prevented, and the occurrence of poisoned vias can be effectively prevented. This is because the SOG film on the metal wiring has already been removed immediately before the formation of the via hole, so that the over-etching time can be shortened. Also, the exposed area of the SOG film on the inner wall of the via hole is small.

The third effect is that the occurrence of cracks in the SOG film can be prevented. This is because according to the manufacturing method of the present invention, it is not necessary to form the thick film portion of the SOG film.

Further, by appropriately selecting the materials of the first interlayer insulating film and the second interlayer insulating film, a fourth effect that via holes can be formed in a self-aligned manner can be obtained. This is because a high etching selectivity can be obtained between the constituent material of the hole forming region and the constituent material of the other region by appropriately selecting the above materials. This effect is particularly remarkable when a so-called borderless wiring having the same hole diameter and metal wiring width is formed.

[Brief description of the drawings]

FIG. 1 is a process sectional view for illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a process sectional view for illustrating the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a process sectional view for illustrating the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the present invention;

FIG. 5 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 6 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 7 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the semiconductor device of the present invention.

FIG. 9 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 10 is a process sectional view illustrating the method for manufacturing the semiconductor device of the present invention.

FIG. 11 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 12 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 13 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 14 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 15 is a process sectional view for illustrating the method for manufacturing the semiconductor device according to the present invention.

FIG. 16 is a process sectional view for illustrating the conventional method of manufacturing a semiconductor device.

FIG. 17 is a process cross-sectional view for describing the conventional method for manufacturing a semiconductor device.

FIG. 18 is a process sectional view for illustrating the conventional method of manufacturing a semiconductor device.

FIG. 19 is a process sectional view for illustrating the conventional method of manufacturing a semiconductor device.

[Description of Signs] 1 silicon substrate 2 base insulating film 3 titanium film 4 aluminum-copper alloy film 5 titanium nitride film 6 first interlayer insulating film 6 ′ first film 7 photoresist 8 second interlayer insulating film 8 ′ Second film 9 Photoresist 10 SOG film 11 Via hole 12 Tungsten film 13 Upper wiring

Claims (18)

(57) [Claims] (A) forming a metal film and a first interlayer insulating film on a semiconductor substrate in this order; and (B) patterning the first interlayer insulating film and the metal film by etching. Forming a metal wiring made of the metal film; (C) forming an SOG film and a second interlayer insulating film on the entire surface in this order; and (D) forming at least a first interlayer insulating film on the first interlayer insulating film. Removing the formed SOG film and a part of the second interlayer insulating film; and (E) etching the first interlayer insulating film to form a plurality of via holes reaching the metal wiring. And a method of manufacturing a semiconductor device. 2. In the step (D), at least the SOG film formed on the first interlayer insulating film and the second interlayer insulating film are removed by chemical mechanical polishing. The method for manufacturing a semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein each of the first interlayer insulating film and the second interlayer insulating film is a silicon oxide film or a silicon nitride film. Manufacturing method. 4. The method according to claim 1, wherein one of the first interlayer insulating film and the second interlayer insulating film is a silicon oxynitride film and the other is a silicon oxide film. The manufacturing method of the semiconductor device described in the above. 5. The method according to claim 1, wherein the SOG film is an HSQ film. 6. In the step (C), after forming the HSQ film,
6. The method according to claim 5, wherein the heat treatment is performed in an atmosphere from which oxygen and water have been removed, and then the second interlayer insulating film is formed. 7. The method according to claim 6, wherein the temperature of the heat treatment is 350 to 500 ° C. 8. The method of manufacturing a semiconductor device according to claim 1, wherein said SOG film is an organic SOG film. 9. The semiconductor device according to claim 1, wherein at least a part of the plurality of via holes has a diameter substantially equal to a width of the metal wiring connected to the via holes. Production method. 10. A method comprising: (A) forming a metal film and a first film on a semiconductor substrate in this order; and (B) patterning the first film and the metal film by etching to form the metal film. Forming a metal wiring made of a film;
(C) a step of forming an SOG film and a second film on the entire surface in this order; and (D) removing at least the SOG film formed on the first film and a part of the second film. And (E) etching the first film to form a plurality of via holes reaching the metal wiring. 11. The semiconductor device according to claim 10, wherein one of the first film and the second film is a polycrystalline silicon film, and the other is a silicon oxide film or a silicon nitride film. Of manufacturing a semiconductor device. 12. The method according to claim 11, further comprising, after the step (E), converting the polycrystalline silicon film into a silicon oxide film. 13. The method according to claim 11, further comprising, after the step (E), converting the polycrystalline silicon film into a silicon oxide film by thermal oxidation. 14. The method of manufacturing a semiconductor device according to claim 10, wherein said SOG film is an HSQ film. 15. The method according to claim 14, wherein in the step (C), after forming the HSQ film, a heat treatment is performed in an atmosphere from which oxygen and water have been removed, and then the second film is formed. 13. The method for manufacturing a semiconductor device according to item 5. 16. The temperature of the heat treatment is 350 to 500 ° C.
The method of manufacturing a semiconductor device according to claim 15, wherein: 17. The method for manufacturing a semiconductor device according to claim 10, wherein said SOG film is an organic SOG film. 18. The semiconductor device according to claim 10, wherein at least a part of the plurality of via holes has a diameter substantially equal to a width of the metal wiring connected to the via holes. Production method.