JP2003338539A - Method for forming metal wiring in semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form metal wiring in a semiconductor device by a dual damascene process. <P>SOLUTION: This method for forming metal wiring in a semiconductor layer comprises: a step for forming a stopper film 704a, an interlayer dielectric film 706, and a hard mask layer 708b on a conductive layer 702 on a semiconductor substrate 700; a step for etching the hard mask layer and the interlayer dielectric film to form in the conductive layer a via hole 712 through which the surface of the stopper film is exposed; a step for filling the via hole with an intermediary material layer; a step for etching a portion of the hard mask layer to form a hard mask pattern that defines a wiring region overlapping at least a portion of the via hole; a step for removing the intermediay material layer from the via hole, then forming the wiring region 718 by etching a portion of the interlayer dielectric film using the hard mask pattern as an etching mask, and removing the stopper layer remaining in the via hole; and a step for filling the via hole and the wiring region with a conductive material. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming metal wiring of a semiconductor device by a dual damascene process.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor devices has increased, metal wiring layers having a multilayer wiring structure have been required, and the distance between metal wirings in semiconductor devices has gradually become narrower. As a result, the influence of parasitic resistance R and capacitance C components existing between metal wiring layers adjacent to each other or vertically adjacent wiring layers on the same layer has become the most important problem.

Parasitic resistance and capacitance components in metal wiring systems degrade the electrical performance of the device due to RC-induced delays. In addition, the parasitic resistance and capacitance components existing between the wiring layers increase the total power consumption of the chip and increase the amount of signal leakage.

Therefore, it is a very important problem to develop a multi-layer wiring technique having a small RC in the ultra-high integration semiconductor device.

In order to form a high-performance multi-layer wiring structure having a small RC, it is necessary to form a wiring layer using a metal having a low specific resistance or use an insulating film having a low dielectric constant.

In order to reduce the resistance in the metal wiring layer,
Currently, research using a metal having a low specific resistance, for example, copper as a metal material for forming a metal wiring layer is actively under way.

It is difficult to obtain a copper wiring by directly patterning it by a photo etching technique. Therefore,
The dual damascene process is mainly used to form copper wiring.

1 to 5 are sectional views showing a method of forming a metal wiring of a semiconductor device according to a conventional example in a process order.

Referring to FIG. 1, a stopper film 104 is formed on a semiconductor substrate 100 on which a predetermined conductive layer 102 is formed.

Then, an interlayer insulating film 106 is formed on the stopper film 104.

Next, a first photoresist pattern 108 having a first width W1 and a first opening H1 partially exposing the upper surface of the interlayer insulating film 106 is formed on the interlayer insulating film 106. That is, after applying a photoresist on the interlayer insulating film 106, the photoresist is exposed and developed to form a first photoresist pattern 108.

Referring to FIG. 2, the interlayer insulating film 10 is formed using the first photoresist pattern 108 as an etching mask.
Etch 6. The etching is a stopper film 1
Perform until 04 is exposed. A via hole 110 having a first width W1 is formed in the interlayer insulating film 106a by the etching.

Next, the first photoresist pattern 108.
To remove. The first photoresist pattern 108 can be removed using a normal method, for example, an ashing process.

Referring to FIG. 3, a second opening having a second width W2 larger than the first width W1 and partially exposing the interlayer insulating film 106a is formed on the interlayer insulating film 106a in which the via hole 110 is formed. A second photoresist pattern 112 having H2 is formed. The position of the second opening H2 is formed so as to correspond to the position of the via hole 110.

Referring to FIG. 4, the interlayer insulating film 106a is dry-etched using the second photoresist pattern 112 as an etching mask. By the etching, the wiring region 114 having the second width W2 is formed in the interlayer insulating film 106b, and the first width W1 for connecting the conductive layer 102 and the wiring region 114 is formed under the wiring region 114. A via hole 110a having a hole is formed.
However, the stopper layer 104 exposed through the via hole (110; see FIG. 3) during the etching may be etched together to expose the conductive layer 102 to the outside. A material having a large etching selection ratio with respect to the stopper film 104a is used for the interlayer insulating film 106b, but a via hole (110;
The stopper film 104 exposed through (see FIG. 3)
Is also etched at a predetermined rate. Therefore, after the etching of the interlayer insulating film 106b is completed, the exposed stopper film 104 may be completely etched to expose the conductive layer 102 to the etching atmosphere. When the conductive layer 102, for example, the copper wiring layer is exposed to the etching atmosphere, a hard polymer (not shown) is formed along the sidewall, but the hard polymer is not easily removed. In such development, the interlayer insulating film 106a which must be etched
Of the stopper film 104a with respect to the interlayer insulating film 106b.
The smaller the etching selection ratio is, the more serious.

Referring to FIG. 5, the second photoresist pattern 112 is removed using an ashing process.
Oxygen-based plasma is used in the ashing process. Therefore, the conductive layer 102 exposed during the second photoresist pattern 112 removing process, that is, during the ashing process is combined with oxygen to form the metal oxide layer 116. When the metal oxide layer 116 is formed, the electric resistance is rapidly increased, and even if a conductive material is embedded in the wiring region 114 and the via hole 110a, the metal wiring (not shown) and the conductive layer 102 are formed. There is also a case where a floating phenomenon occurs, that is, a lifting phenomenon without being electrically connected. In addition, the wiring region 114 and the via hole 110
Since the ashing process using oxygen-based plasma proceeds after forming a, the surface of the interlayer insulating film 106b is damaged by the ashing process. That is, H ₂ O, OH, CO ₂ , H _{2 and the} like are induced by the ashing process and adhered to the surface of the interlayer insulating film 106b, which rapidly increases the dielectric constant of the interlayer insulating film 106b. Act as a factor.

6 to 9 are cross-sectional views showing a method of forming a metal wiring of a semiconductor device according to another conventional example in the order of steps.

Referring to FIG. 6, a stopper film 204 is formed on the semiconductor substrate 200 on which a predetermined conductive layer 202 is formed.

Then, an interlayer insulating film 206 is formed on the stopper film 204.

Next, a first photoresist pattern 208 having a first width H1 and a first opening H1 partially exposing the upper surface of the interlayer insulating film 206 is formed on the interlayer insulating film 206. That is, after coating a photoresist on the interlayer insulating film 206, the photoresist is exposed and developed to form a first photoresist pattern 208.

Referring to FIG. 7, a part of the interlayer insulating film 206 is etched using the first photoresist pattern 208 as an etching mask. In the etching, only a part of the interlayer insulating film 206 is etched and the interlayer insulating film 206 having a predetermined thickness is left without being etched. By the etching, the partial via hole 210 having the first width W1 is formed in the interlayer insulating film 206a.

Next, the first photoresist pattern 208.
To remove. The first photoresist pattern 108 can be removed using a normal method, for example, an ashing process.

Referring to FIG. 8A, the interlayer insulating film 2 having a second width W2 larger than the first width W1 is formed on the interlayer insulating film 206a having the partial via hole 210 formed therein.
A second photoresist pattern 212 having a second opening H2 that partially exposes 06a is formed. Second opening H
The position 2 is formed so as to correspond to the position of the partial via hole 210. However, when the second photoresist pattern 212 is formed on the interlayer insulating film 206a, the photoresist 212 may remain on the bottom of the partial via hole 210. The photoresist 212 remaining on the bottom of the partial via hole 212 may serve as a barrier for the subsequent etching of the interlayer insulating film 206a, and an unopened via hole may be formed when the remaining interlayer insulating film 206a is etched. A detailed description of this will be given later.

On the other hand, FIG. 8B illustrates an example of the misaligned second photoresist pattern.
Although not shown, the photoresist may remain at the bottom of the partial via hole 210 in this case as described with reference to FIG. 8A.

Referring to FIG. 9A, the interlayer insulating film 2 is formed using the second photoresist pattern 212 as an etching mask.
06a is dry-etched. By the etching, the wiring region 214 having the second width W2 is formed in the interlayer insulating film 206b, and the first width W1 for connecting the conductive layer 202 and the wiring region 214 is formed under the wiring region 214. A via hole 210a having a is formed.
However, the photoresist 212 remaining on the bottom of the partial via hole (210; see FIG. 8A) during the etching acts as a barrier against the etching. Therefore, the partial via hole (210; FIG. 8)
The interlayer insulating film 206b existing under (see A) is not further etched, and eventually an unopened via hole 210a is formed.

On the other hand, in FIG. 9B, when the misaligned second photoresist pattern 212 is formed, the interlayer insulating film 206a is etched using the misaligned second photoresist pattern 212 as an etching mask to form the wiring region 214 and the via hole. It shows the state in which 210a is formed. As shown in FIG. 9B,
When misalignment occurs, the width of the via hole 210a becomes narrower than the first width W1 and the profile of the via hole 210a becomes defective. In addition, as described with reference to FIG. 9A, a via hole (not shown) may be formed that is not opened when the photoresist remains at the bottom of the partial via hole (210; see FIG. 8B).

FIG. 10A shows an example of a metal wiring layer having an unopened via hole. 9A and 10A
Referring to FIG.
Are removed using an ashing process. The photoresist 212 remaining in the via hole (210a; see FIG. 9A) during the ashing process is also removed. However, as described above, the via hole 21 that is not opened.
0a is formed so that the wiring region 214 and the conductive layer 202 are not connected. In addition, after forming the wiring region 214 and the via hole 210a, in order to proceed with the ashing process using oxygen-based plasma, the interlayer insulating film 206b is formed.
The surface of the substrate is damaged by the ashing process. That is, H ₂ O, OH, CO ₂ ,
H ₂ or the like is induced and adhered to the surface of the interlayer insulating film 206b, and this acts as a factor for rapidly increasing the dielectric constant of the interlayer insulating film 206b.

On the other hand, FIG. 10B illustrates a state after the second photoresist pattern 212 is removed when the misalignment of the second photoresist pattern 212 occurs. As shown in FIG. 10B, the via hole 210a having a width smaller than the first width W1 is formed, and the profile of the via hole 210a becomes defective. Also,
As described above, the partial via hole (210; FIG. 8).
When the photoresist remains at the bottom of the wiring region 214 (see B), an unopened via hole (not shown) may be formed and the wiring region 214 and the conductive layer 202 may not be connected.

[0029]

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problems in the prior art. The technical problem to be achieved by the present invention is to etch an interlayer insulating film to form a wiring region and a via hole. The problem that the metal oxide layer is formed on the conductive layer in the second photoresist pattern removing process due to the stopper film being etched and the conductive layer being exposed to the outside can be prevented, and the damage due to the ashing process can be prevented. It is also possible to solve the problem that the photoresist does not remain in the partial via hole when the second photoresist pattern is formed and the via hole is not opened. Even if misalignment of the second photoresist pattern occurs, the via hole Method for forming metal wiring of semiconductor device that can prevent profile failure It is to provide a.

[0030]

The metal wiring forming method for a semiconductor device according to the first and second embodiments for achieving the above-mentioned technical object is to form a stopper film on a conductive layer formed on a semiconductor substrate. Forming, forming an interlayer insulating film on the stopper film, forming a hard mask layer on the interlayer insulating film, and limiting a via hole corresponding to the conductive layer on the hard mask layer. Forming a first photoresist pattern, and a via hole exposing the surface of the stopper film formed on the conductive layer by etching the hard mask layer and the interlayer insulating film using the first photoresist pattern as an etching mask. Forming, a step of removing the first photoresist pattern, a step of embedding the via hole as an intermediate material layer, Etching a portion of the hard mask layer to form a hard mask pattern that defines a wiring region overlapping at least a portion of the via hole; removing the mediator layer from the via hole; Using the mask pattern as an etching mask, a part of the interlayer insulating film is etched to form a wiring region, the stopper layer remaining in the via hole is removed, and a conductive material is embedded in the via hole and the wiring region. And stages.

The interlayer insulating film is formed by laminating a first interlayer insulating film, a second stopper film and a second interlayer insulating film on the stopper film. At this time, in the step of forming the wiring region, The second interlayer insulating film may be formed by etching using the second stopper film as an etching stopper layer.

The hard mask layer is at least one of a silicon oxide film, a silicon nitride film, a silicon carbide film, polysilicon, a metal oxide, a metal nitride or a metal having a high etching selection ratio with respect to the interlayer insulating film. It is preferable that the intermediary material layer comprises a carbon-based organic material B having an etch selectivity and the interlayer insulating layer.
The SOG film is made of an ARC film or an SOG film, and the SOG film is made of an inorganic material H having an etching selection ratio with the interlayer insulating film.
It can be an SQ film, an MSQ film or a porous SiO ₂ film.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following examples are provided so that those skilled in the art can understand the present invention sufficiently, and can be modified into various other forms. Are not limited to the embodiments described below. When the following description describes a layer as being on top of another layer, it may be directly on top of the other layer with a third layer interposed therebetween. In addition, the thickness and size of each layer are exaggerated in the drawings for convenience of description and clarity. In the drawings, the same reference numerals refer to the same elements.

<First Embodiment> FIGS. 11 to 17 are sectional views showing a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.

Referring to FIG. 11, a predetermined conductive layer 702.
A stopper film 704 is formed on the semiconductor substrate 700 having the film formed thereon.
To form. The conductive layer 702 may be an impurity-doped region formed on the semiconductor substrate 700, a Cu wiring layer, or another metal wiring layer. The stopper film 704 is preferably made of a material having a high etching selection ratio with the interlayer insulating film 706 formed thereon, for example, Si ₃ N ₄ or SiC.

Next, an interlayer insulating film 706 is formed on the stopper film 704. The interlayer insulating film 706 is, for example, Si.
OC film, porous SiO ₂ film, PSG (phosphor)
ous silicate glass), BPSG
(Boron phosphorous silicat
e-glass) film, USG (undoped sili)
Cate glass) film, FSG (fluorine)
doped silicate glass), HDP
(High density plasma) film, PE-
TEOS (plasma enhanced-tetr
It is desirable to use a material film having a low dielectric constant, such as an aetherthosilicate film or an SOG (spin on glass) film. The interlayer insulating film 706 is made of a material film having a high etching selection ratio with respect to the stopper film 704.

Then, a hard mask layer 708 is formed on the interlayer insulating film 706. The hard mask layer 708 is a material having a high etching selection ratio with respect to the interlayer insulating film 706, such as a silicon nitride film, a silicon oxide film, a silicon carbide film, polysilicon, a metal oxide such as aluminum oxide, or a metal nitride such as TiN. It is desirable that the object be made of metal such as aluminum or titanium.

Next, a first opening H1 is formed on the hard mask layer 708, which has a first width W1 and partially exposes an upper surface of the hard mask layer 708 which defines a via hole (described later) corresponding to the conductive layer 702. A photoresist pattern 710 is formed. That is, the hard mask layer 70
8 is coated with a photoresist, and then the photoresist is exposed and developed to form a first photoresist pattern 71.
Form 0.

Referring to FIG. 12, the hard mask layer 708 and the interlayer insulating layer 706 are etched using the first photoresist pattern 710 as an etching mask to form a via hole 712 exposing the stopper layer 704.

Next, the first photoresist pattern 71
Remove 0. The first photoresist pattern 710 may be removed using a conventional method, for example, an ashing process.

Referring to FIG. 13, an intermediate material layer 714 is formed on the semiconductor substrate 700 in which the via hole 712 is formed.
Is applied to fill the via hole 712. The mediator layer 714 may be formed only in the via hole 712, or may be thinly formed on the hard mask layer 708a by a predetermined height. The mediator layer 714 is a carbon-based organic material BARC (Bottom Anti-).
It may be formed of a Reflection Coating film. The BARC film may be formed by a spin coating method. At this time, the rotation speed of the spin coater is 100.
It is desirable to be about 0 to 5000 rpm. 100 after applying the organic material film by the spin coating method.
Baking is performed at a temperature of about ℃ to 150 ℃.

Meanwhile, the mediator layer 714 may include an SOG layer. The SOG film is, for example, an inorganic HSQ.
(Hydro silsesquioxane) membrane, M
It is preferably an SQ film or a porous SiO ₂ film.

Referring to FIG. 14, a second width W2, which is larger than the first width W1, is formed on the semiconductor substrate 700 on which the mediator layer 714 is formed. A second photoresist pattern 716 having an opening H2 is formed. The position of the second opening H2 is formed so as to correspond to the position of the via hole 712, and the second opening H2 is positioned above the via hole 712 so as to overlap with at least a part of the via hole 712.

Referring to FIG. 15, the interlayer insulating film 7 is formed using the second photoresist pattern 716 as an etching mask.
06 Mediator layer 714 and hard mask layer 708
dry etch a. When the mediator layer 714 is a BARC film, which is an organic material film, the etching uses a gas containing O ₂ or a gas containing N ₂ and H ₂ . Alternatively, C _x F _y based gas or C _x H _y F
An etching gas containing a z-based gas, an inert gas such as Ar, and CO or O ₂ gas may be used. On this occasion,
The mediator layer 714 in the via hole 712 is also recessed to some extent during the etching.

On the other hand, when the mediator layer 714 is an SOG film, the dry etching may include a CxFy-based gas or a CxHyFz-based gas, an inert gas such as Ar, and CO, CO ₂ or O ₂ gas. Use gas. The dry etching is preferably performed at a pressure of 5 to 50 mTorr and a power of about 1000 to 5000 W for 1 to 2 minutes.

Referring to FIG. 16, the second photoresist pattern 716 is removed. The second photoresist pattern 716 may be removed using a conventional method, for example, an ashing process. At this time, when the mediator layer 714 is an organic material, the organic material film is also removed. That is, the intermediate material layer 714 made of an organic material film, which is present in the upper portion of the hard mask layer 708a and the via hole 712, is also removed in the step of removing the second photoresist pattern 716, for example, the ashing step. Second photoresist pattern 7
16 and the mediator layer 714 are removed, the second width W2
The hard mask layer 708b having an opening having a is exposed.

When the mediator layer 714 is an SOG film,
The SOG film formed on the hard mask layer 708b and in the via hole 712 is removed by wet etching.
It is preferable to use an etching solution, such as an HF solution, which has a high etching rate of the SOG film with respect to the interlayer insulating film 706 and can selectively remove only the SOG film. HSQ
The SOG film as described above has an extremely high etching rate in the HF solution, while the interlayer insulating film 706, for example, the SiOC film is hardly etched in the HF solution.

Referring to FIG. 17, a hard mask layer 70
The interlayer insulating film 706 is dry-etched by using 8b as an etching mask to form the wiring region 718 and the via hole 712a.
Are formed at the same time. That is, the wiring region 718 having the second width W2 is formed in the interlayer insulating film 706, and the wiring region 7 is formed.
A via hole 712a having a first width smaller than the second width W2 is formed in the lower part of 18. On the other hand, since the hard mask layer 708b is used as an etching mask, the hard mask layer 708b must have a sufficient thickness to withstand while the interlayer insulating film 706 is etched.

Next, the stopper film 704 exposed through the via hole 712a is etched and removed.
At this time, the hard mask layer 708b may be etched and removed together, or the hard mask layer 708b may be left as it is and the subsequent process may be performed.

Next, a barrier layer (not shown) is formed along the step on the semiconductor substrate 700 from which the stopper film 704 has been removed.
And after forming a conductive layer (not shown), it is planarized to complete the formation of the metal wiring of the dual damascene structure.

<Second Embodiment> FIGS. 18 to 24 are sectional views showing, in the order of steps, a method for forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention. Compared with the first embodiment, the first embodiment is the same as the first embodiment except that a first interlayer insulation film 805, a second stopper film 806 and a second interlayer insulation film 807 are used instead of the interlayer insulation film 706. .

Referring to FIG. 18, a predetermined conductive layer 802 is formed.
The first stopper film 8 is formed on the semiconductor substrate 800 on which the
To form 04. Then, a first interlayer insulating film 805, a second stopper film 806, and a second interlayer insulating film 807 are sequentially formed on the first stopper film 804.

Next, a hard mask layer 808 is formed on the second interlayer insulating film 807. The hard mask layer 808 is a material having a high etching selection ratio with respect to the interlayer insulating film 706, such as a silicon nitride film, a silicon oxide film, a silicon carbide film, polysilicon, a metal oxide such as aluminum oxide, or a metal nitride such as TiN. It is desirable that the object be made of metal such as aluminum or titanium.

Next, a first opening H1 is formed on the hard mask layer 808, which has a first width W1 and partially exposes an upper surface of the hard mask layer 808 which defines a via hole (described later) corresponding to the conductive layer 802. A photoresist pattern 810 is formed.

Referring to FIG. 19, the hard mask layer 808, the second interlayer insulating film 807a, the second stopper film 806 and the first interlayer insulating film 806 are sequentially etched using the first photoresist pattern 810 as an etching mask. Etching while changing the stopper layer 804
A via hole 812 that exposes is formed. Then, the first photoresist pattern 810 is removed.

Referring to FIG. 20, the via hole 812 is filled with a medium material layer 814. The mediator layer 814 may be formed only in the via hole 812, or may be thinly formed on the hard mask layer 808a by a predetermined height.
The mediator layer 814 is a carbon-based organic BARC (Bottom) as an organic material layer as in the first embodiment.
The anti-reflection coating film or the SOG film may be used.

Referring to FIG. 21, a second width W2, which is larger than the first width W1, is formed on the semiconductor substrate 800 on which the mediator layer 814 is formed. A second photoresist pattern 816 having an opening H2 is formed. The second opening H2 is formed so as to correspond to the position of the via hole 812, and the second opening H is formed on the upper portion of the via hole 812 so as to overlap with at least a part of the via hole 812 to form a dual damascene structure.
Position 2.

Referring to FIG. 22, the medium material layer 8 using the second photoresist pattern 816 as an etching mask.
14 and hard mask layer 808b are dry etched. At this time, the mediator layer 814 in the via hole 812 is also recessed to some extent during the etching.

Referring to FIG. 23, the second photoresist pattern 816 is removed. The second photoresist pattern 816 may be removed using a normal method, for example, an ashing process. Then, as in the first embodiment, the via hole 8 is formed.
The mediator layer 814 remaining in 12 is removed.

Referring to FIG. 24, the hard mask layer 80
Second interlayer insulating film 807b using 8b as an etching mask
Is dry-etched until the second stopper film 806 is exposed to form a wiring region 818. Then, the first stopper film 804 exposed through the via hole 812a.
Are removed by etching. At this time, the hard mask layer 8
08b may be removed by etching together, or the hard mask layer 808b may be left as it is and the subsequent process may be performed.

Then, a barrier layer (not shown) and a conductive layer (not shown) are formed along the steps on the semiconductor substrate 800 from which the first stopper film 804 has been removed, as in the first embodiment. Planarization is completed to complete the formation of the dual damascene metal wiring.

Although the preferred embodiments of the present invention have been described above in detail, the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention. is there.

[0063]

According to the method for forming a metal wiring of a semiconductor device according to the present invention, a stopper film is formed when a wiring region and a via hole are formed by etching an interlayer insulating film (or a second interlayer insulating film and a first interlayer insulating film). Alternatively, there is no concern that the conductive layer is exposed to the outside due to the etching of the first stopper film). Therefore, the conventional problem that the metal oxide layer is formed on the conductive layer in the second photoresist pattern removing step is not a problem. Does not occur.

In addition, according to the present invention, since the partial via hole is filled with an organic material or an inorganic material after the partial via hole is formed and before the second photoresist pattern is formed, the bottom of the partial via hole is formed when the second photoresist pattern is formed. The conventional problem that the photoresist remains and the via hole is not opened does not occur.

Further, according to the present invention, since the partial via hole is filled with an organic material or an inorganic material after the partial via hole is formed and before the second photoresist pattern is formed, even if the misalignment of the second photoresist pattern occurs, the conventional method is used. The profile defect of such a via hole does not occur.

Further, according to the present invention, after the second photoresist pattern is removed, the hard mask layer is used as an etching mask to form a wiring region and a via hole, so that damage caused by the ashing process that appears on the surface of the interlayer insulating film as in the prior art is prevented. I do not receive it. In addition, as in the first and second embodiments of the present invention, a full via hole may be applied using an intermediate material layer.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a conventional example in order of steps.

FIG. 2 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a conventional example in order of process steps.

FIG. 3 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a conventional example in a process order.

FIG. 4 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a conventional example, in the order of steps.

FIG. 5 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a conventional example in order of steps.

FIG. 6 is a cross-sectional view showing, in the order of steps, a method for forming a metal wiring of a semiconductor device according to another conventional example.

FIG. 7 is a cross-sectional view showing, in the order of steps, a method for forming a metal wiring of a semiconductor device according to another conventional example.

FIG. 8 is a cross-sectional view showing, in the order of steps, a method for forming a metal wiring of a semiconductor device according to another conventional example.

FIG. 9 is a cross-sectional view showing, in the order of steps, a method for forming a metal wiring of a semiconductor device according to another conventional example.

FIG. 10 is a cross-sectional view showing, in the order of steps, a method for forming a metal wiring of a semiconductor device according to another conventional example.

FIG. 11 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.

FIG. 12 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to the first preferred embodiment of the present invention in the order of steps.

FIG. 13 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to the first preferred embodiment of the present invention in the order of steps.

FIG. 14 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.

FIG. 15 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to the first preferred embodiment of the present invention in the order of steps.

FIG. 16 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to the first preferred embodiment of the present invention in the order of steps.

FIG. 17 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to the first preferred embodiment of the present invention in the order of steps.

FIG. 18 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.

FIG. 19 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.

FIG. 20 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.

FIG. 21 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.

FIG. 22 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.

FIG. 23 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.

FIG. 24 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.

[Explanation of symbols]

104,204,704 Stopper film 804 First stopper film 806 Second stopper film 106, 206, 706 Interlayer insulation film 805 First interlayer insulating film 807 Second interlayer insulating film 110, 210 partial beer holes 110a, 210a, 712, 812 via holes 114, 214, 718, 818 Wiring area

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Kim, Tsuru             62-5 Bunjeong-dong, Songpa-gu, Seoul, South Korea             Address Hyundai Apartment No. 1207 (72) Inventor Lee Morone             Buksan, Wokpo-dong, Bat-gu, Suwon-si, Gyeonggi-do, Republic of Korea             Apartment 117 Building 1602 F term (reference) 5F033 KK01 KK11 MM02 QQ11 QQ25                       QQ27 QQ28 QQ37 RR01 RR03                       RR04 RR06 RR09 RR11 RR14                       RR15 RR29 SS04 SS15 TT01                       XX15

Claims (10)

[Claims] 1. A step of forming a stopper film on a conductive layer formed on a semiconductor substrate, a step of forming an interlayer insulating film on the stopper film, and a step of forming a hard mask layer on the interlayer insulating film. Forming a first photoresist pattern on the hard mask layer to define a via hole corresponding to the conductive layer; and using the first photoresist pattern as an etching mask to form the hard mask layer and the interlayer insulating film. Etching to form a via hole exposing the surface of the stopper layer formed on the conductive layer, removing the first photoresist pattern, filling the via hole as an intermediate material layer, Etching a part of the hard mask layer to limit a wiring region overlapping with at least a part of the via hole Forming a hard mask pattern, removing the intermediary material layer from the via hole, and forming a wiring region by etching a part of the interlayer insulating film using the hard mask pattern as an etching mask, A method of forming a metal wiring of a semiconductor device, comprising: removing the stopper layer remaining in the via hole; and burying a conductive material in the via hole and the wiring region. 2. The interlayer insulating film is formed by laminating a first interlayer insulating film, a second stopper film and a second interlayer insulating film on the stopper film. Method for forming metal wiring of semiconductor device. 3. The semiconductor device according to claim 2, wherein the forming of the wiring region is performed by etching the second interlayer insulating film using the second stopper film as an etching stopper layer. Metal wiring forming method. 4. The semiconductor device according to claim 1, wherein the stopper film and the second stopper film are formed of a silicon nitride film or a silicon carbide film having an etching selection ratio with the interlayer insulating film. Metal wiring forming method. 5. The interlayer insulating film is a SiOC film, a porous SiO ₂ film, a PSG film, a BPSG film, a USG film, an FSG.
3. The method for forming metal wiring of a semiconductor element according to claim 1, comprising a film, an HDP film, a PE-TEOS film or an SOG film. 6. The hard mask layer comprises a silicon oxide film, a silicon nitride film, a silicon carbide film, polysilicon, which has a high etching selection ratio with respect to the interlayer insulating film.
At least one of metal oxide, metal nitride or metal
The method for forming metal wiring of a semiconductor device according to claim 1, wherein the method comprises: 7. The method of claim 1, wherein the mediator layer comprises a BARC film or a SOG film of a carbon-based organic material having an etching selection ratio with the interlayer insulating film. . 8. The SOG film is an inorganic HSQ film, an MSQ film or a porous SiO ₂ film having an etching selection ratio with the interlayer insulating film.
A method for forming a metal wiring of a semiconductor device according to 1. 9. The method of claim 1, wherein the medium material layer is formed on the hard mask layer to a predetermined height while filling the via hole. 10. The step of forming the hard mask pattern, the step of forming a second photoresist pattern corresponding to the hard mask pattern on the semiconductor substrate having the mediator layer formed thereon, and the second photoresist. The method may include etching the mediator layer and the hard mask layer using the pattern as an etching mask, and removing the mediator layer on the second photoresist pattern and the hard mask layer. 9. The method for forming metal wiring of a semiconductor device according to item 9.