CN113363201A - Semiconductor device and super through hole forming method - Google Patents
Semiconductor device and super through hole forming method Download PDFInfo
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- CN113363201A CN113363201A CN202010146183.3A CN202010146183A CN113363201A CN 113363201 A CN113363201 A CN 113363201A CN 202010146183 A CN202010146183 A CN 202010146183A CN 113363201 A CN113363201 A CN 113363201A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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Abstract
The embodiment of the invention provides a semiconductor device and a forming method of a super through hole, wherein the forming method of the super through hole comprises the following steps: providing a semiconductor device, wherein the semiconductor device comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially positioned on the surface of a semiconductor substrate, a first metal interconnection structure is arranged in the first dielectric layer, and a second metal interconnection structure is arranged in the second dielectric layer; forming a first through hole and a second through hole penetrating through the third dielectric layer, wherein the second through hole exposes the second metal interconnection structure; selectively growing an interconnection structure barrier layer, wherein the interconnection structure barrier layer is grown only on the surface of the exposed second metal interconnection structure; and forming a third through hole penetrating through the second dielectric layer, wherein the third through hole is communicated with the first through hole, and the first metal interconnection structure is exposed out of the third through hole. The method simplifies the process and reduces the process cost.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a method for forming a super through hole.
Background
The through holes serve as channels for interconnection of the multiple metal layers and connection between the active region of the semiconductor device and an external circuit, and play a crucial role in the structure of the semiconductor device. In the via technology, one or more metal wiring structures in an insulating layer can be connected with a metal wiring structure under the insulating layer by forming a super via in a multi-layered insulating layer, which not only provides improved resistance characteristics but also minimizes capacitance.
However, many challenges still exist in using super vias, for example, super vias need to be landed on lower-level metal wiring structures, and conventional vias need to be landed on higher-level metal wiring structures, so how to form super vias at the same time as conventional vias with lower process cost is one of the problems to be solved by those skilled in the art.
Disclosure of Invention
The embodiment of the invention provides a super through hole, a forming method thereof and a semiconductor device, and aims to form the super through hole while forming a conventional through hole by adopting lower process cost.
The invention provides a method for forming a semiconductor structure, which comprises the following steps:
providing a semiconductor device, wherein the semiconductor device comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially positioned on the surface of a semiconductor substrate, a first metal interconnection structure is arranged in the first dielectric layer, and a second metal interconnection structure is arranged in the second dielectric layer;
forming a first through hole and a second through hole penetrating through the third dielectric layer, wherein the second through hole exposes the second metal interconnection structure;
selectively growing an interconnection structure barrier layer, wherein the interconnection structure barrier layer is grown only on the surface of the exposed second metal interconnection structure;
and forming a third through hole penetrating through the second dielectric layer, wherein the third through hole is communicated with the first through hole, and the first metal interconnection structure is exposed out of the third through hole.
An embodiment of the present invention further provides a semiconductor device, including:
the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially positioned on the surface of the semiconductor substrate;
the first dielectric layer is internally provided with a first metal interconnection structure, and the second dielectric layer is internally provided with a second metal interconnection structure;
the bottom of the second through hole is communicated to the second metal interconnection structure, and an interconnection structure barrier layer covering the second metal interconnection structure is formed in the second through hole;
and a third through hole penetrating through the first dielectric layer and exposing the first metal interconnection structure, wherein the third through hole is communicated with the first through hole.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method of the super through hole, when the second through hole exposing the second metal interconnection structure is formed, the formed interconnection structure barrier layer is only located on the surface of the exposed second metal interconnection structure through a selective growth process, structures at other positions cannot be influenced, and further the second metal interconnection structure can be protected from being influenced by a corresponding process in the process of forming the third through hole.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 4 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the conventional process has a high cost for forming a super via while forming a conventional via, and the reason for the high cost is analyzed in conjunction with a method for forming a semiconductor device.
Specifically, the super via is formed while the conventional via is formed, multiple etching steps are required for etching the dielectric layer, and different etching steps correspond to different etching regions and etching positions. Because the conventional through hole is located on the metal wiring structure of the higher layer, the process of forming the conventional through hole is usually combined in the process of forming the super through hole, and the conventional through hole formed prematurely exposes the corresponding metal wiring structure, in order to avoid the exposed metal wiring structure from being damaged by the subsequent process for forming the super through hole, a barrier layer corresponding to the metal wiring structure needs to be formed, and the barrier layer needs to expose other positions of the metal wiring structure, so that the influence of the subsequent process on the metal wiring structure is avoided, and meanwhile, the influence of the mask on other structures is avoided.
However, the formation process of the barrier layer is excessively complicated. Specifically, referring to fig. 1, a conventional via 1 exposes a metal wiring structure 2, and an initial via 3 for forming a super via is further formed in other regions of the device, wherein, when forming a barrier layer, referring to fig. 2, a barrier material layer 4 covering the conventional via 1 and the initial via 3 needs to be formed, and further the barrier material layer in the initial via 3 is removed through a process of photolithography and etching, and the surface barrier material layer is removed through a grinding process, so that only the barrier material layer in the conventional via 1 is retained as a barrier layer 5 (refer to fig. 3), and the barrier material layer in other portions is removed.
Obviously, the process for forming the barrier layer is complex and the process cost is high.
Based on this, an embodiment of the present invention provides a method for forming a super via, where when a second via exposing a second metal interconnection structure is formed, a selective growth process is performed to make a formed interconnection structure barrier layer only on the surface of the exposed second metal interconnection structure without affecting structures at other positions, so that in a process of forming a third via, the second metal interconnection structure can be protected from being affected by a corresponding process.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 4, a semiconductor device is provided.
The semiconductor device comprises a first dielectric layer 101, a second dielectric layer 102 and a third dielectric layer 103 which are sequentially located on the surface of a semiconductor substrate 100, wherein a first metal interconnection structure 110 is arranged in the first dielectric layer 101, and a second metal interconnection structure 120 is arranged in the second dielectric layer 102.
The semiconductor device is used for providing a process foundation for forming conventional through holes and super through holes.
Specifically, the semiconductor substrate 100 may be a silicon substrate, a silicon germanium substrate, or other semiconductor substrates known in the art, and a transistor, an interconnection line, a plug, or other semiconductor devices may be formed in the semiconductor substrate 100, and those skilled in the art may set the semiconductor substrate according to actual needs.
Specifically, a first dielectric layer 101, a second dielectric layer 102 and a third dielectric layer 103 are sequentially formed on the semiconductor substrate 100. The first dielectric layer 101, the second dielectric layer 102, and the third dielectric layer 103 are made of low-k materials, and specifically, the low-k materials may be SiO2SiOF, SiCOH, SiO, SiCO, or SiCON.
The first dielectric layer 101, the second dielectric layer 102, and the third dielectric layer 103 may be formed by a deposition process.
In this embodiment, a first etching stop layer 104 is further formed between the first dielectric layer 101 and the second dielectric layer 102, and a second etching stop layer 105 is further formed between the second dielectric layer 102 and the third dielectric layer 103. The first etching barrier layer 104 and the second etching barrier layer 105 are used as stop layers in the process of forming through holes by etching, so that the semiconductor substrate is prevented from being damaged by an etching process.
The material of the first etch stop layer 104 and the second etch stop layer 105 may be silicon nitride (SiN), and in other embodiments of the present invention, the first etch stop layer and the second etch stop layer may also be one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride.
The first etch stopper 104 and the second etch stopper 105 may be formed by a deposition process.
In addition, in order to facilitate the patterning of the dielectric layer and protect the third dielectric layer 103, a hard mask layer 106 is further formed on the surface of the third dielectric layer 103.
The hard mask layer 106 may include a dielectric hard mask layer and a metal hard mask layer (not shown in the figure), the material of the dielectric hard mask layer may be one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide and silicon nitride containing carbon, and the material of the metal hard mask layer may be titanium nitride, copper nitride or aluminum nitride.
The dielectric hard mask layer is used for improving the adhesion between the third dielectric layer 103 and a metal hard mask layer formed later, and is used as a protective layer of the third dielectric layer 103 to prevent metal atoms in the metal hard mask layer from diffusing into the third dielectric layer 103, so that the influence on the k value of the third dielectric layer 103 is avoided, and electric leakage is prevented.
Specifically, the dielectric hard mask layer and the metal hard mask layer may be formed by a chemical vapor deposition process.
In this embodiment, the first metal interconnection structure 110 in the first dielectric layer 101 may be understood as a metal wiring structure at a lower layer, and a corresponding connection needs to be made through a super via, and the second metal interconnection structure 120 in the second dielectric layer 102 may be understood as a metal wiring structure at a higher layer, and a corresponding connection needs to be made through a conventional via.
The material of the first metal interconnection structure 110 and the second metal interconnection structure 120 may be one or more of W, Al, Ag, Cr, Co, Ni, Pt, Ti, Ta, Ru, or Cu, which is not particularly limited in the present invention. Specifically, in the present embodiment, the material of the first metal interconnection structure 110 and the second metal interconnection structure 120 may be copper.
Referring to fig. 5 to 6, a first via 111 and a second via 121 penetrating through the third dielectric layer 103 are formed, and the second via 121 exposes the second metal interconnection structure 120.
Here, the first via 111 may be understood as an initial via in a process of forming a super via, and the second via 121 may be understood as a conventional via for exposing the second metal interconnection structure located at a higher level. And the first through hole 111 and the second through hole 121 are formed at the same time, and are used for combining the technological processes of the conventional through hole and the super through hole, so that the technological process is simplified, and the technological cost is reduced.
Specifically, the first via 111 and the second via 121 may be formed by photolithography and etching. Specifically, forming the first via 111 and the second via 121 penetrating through the third dielectric layer 103 may include:
referring to fig. 5, a patterned first mask layer 107 is formed on the hard mask layer 106.
The first mask layer 107 exposes regions for forming the first and second via holes, and covers other regions of the hard mask layer 106.
Specifically, the first mask layer 107 may be a photoresist layer, and the photoresist in the region for forming the first through hole and the second through hole is removed by photolithography and development, and the photoresist in the other region of the hard mask layer is retained.
Referring to fig. 6, with the first mask layer 107 as a mask, the hard mask layer 106, the third dielectric layer 103 and the second etching stop layer 105 exposed by the first mask layer 107 are removed by etching, so as to form the first through hole 111 in a region corresponding to the first through hole, and form the second through hole 121 in a region corresponding to the second through hole.
Specifically, the hard mask layer 106, the third dielectric layer 103, and the second etching stop layer 105 may be etched by dry etching, wet etching, or a combination of the two methods. For different layer materials, different etching parameters or etching solutions can be adopted to realize corresponding processes, and the invention is not described herein again.
In this embodiment, after the first via hole 111 and the second via hole 121 are formed, the first mask layer 107 is removed. Specifically, the first mask layer 107 may be removed by an ashing process or a stripping process.
Referring to fig. 7, an interconnect structure barrier layer 130 is selectively grown, and the interconnect structure barrier layer 130 is grown only on the exposed surface of the second metal interconnect structure 120.
The selective growth process is used to form the interconnect structure barrier layer 130 only on the exposed surface of the second metal interconnect structure 120, so that the second metal interconnect structure 120 is protected from the corresponding process during the formation of the third via.
The selective growth process is a process for growing a material of a growth substrate, and the process can realize that a specific growth material grows on a material surface layer of the specific growth substrate, or the specific growth material grows on the material surface layer of the growth substrate having a specific lattice matching relationship with the specific growth material, so that the material of the growth substrate grows. In the embodiment of the invention, the material of the interconnect structure barrier layer is a material which can only grow on the metal surface layer, so that the interconnect structure barrier layer in the embodiment of the invention only grows on the exposed second metal interconnect structure.
The selective growth process is not formed at other positions, so that the embodiment of the invention does not need to carry out a complex patterning process, and compared with the existing process, the process is simplified, and the process cost is reduced.
In this embodiment, the selective etching ratio of the interconnect structure barrier layer 130 to the second dielectric layer 102 is greater than or equal to 5, so as to better protect the second metal interconnect structure under the interconnect structure barrier layer from being affected by the subsequent etching of the second dielectric layer.
Specifically, the material of the barrier layer 130 of the interconnect structure is AlN, TiN, RuO2、TiO2、HfN、ZfO2、Al2O3W, Ru or a metal alloy material. Correspondingly, the interconnect structure barrier layer may be formed using a Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD) process.
Wherein the material of the interconnect structure barrier layer 130 is different from the material of the second metal interconnect structure.
The thickness of the interconnect structure barrier layer 130 should not be too large, nor too small. If the thickness of the barrier layer is too large, the barrier layer of the interconnection structure is not easy to remove, and if the thickness of the barrier layer of the interconnection structure is too small, the barrier layer of the interconnection structure cannot play a corresponding protection role, so that the second metal interconnection structure below the barrier layer of the interconnection structure is possibly damaged in the etching process. Therefore, in the present embodiment, the thickness of the interconnect structure barrier layer 130 is set to
Referring to fig. 8 to 10, a third via 113 is formed through the second dielectric layer 102.
The third via 113 is connected to the first via 111, and the first metal interconnection structure 110 is exposed from the third via 113. And the first metal interconnection structure is exposed to realize the connection of the first metal interconnection structure and the metal plug formed in the subsequent step.
In the present embodiment, since the second metal interconnection structure is already covered by the interconnection structure barrier layer, the second metal interconnection structure 120 located at a higher level is not damaged while the third via 113 is formed in the present step.
Specifically, the process of forming the third via penetrating through the second dielectric layer may include:
referring to fig. 8, the hard mask layer 106 is used as a mask to etch and remove a portion of the second dielectric layer 102 in the first through hole 111.
Based on that the hard mask layer 106 has been etched in the foregoing step, and this step is only to further deepen the first through hole, in this embodiment, the hard mask layer 106 may be used as a mask, the opening of the first through hole 111 is used as a cut-in, and a portion of the second dielectric layer 102 in the first through hole 111 is etched and removed.
A portion of the second dielectric layer 102 is etched for integration of the process flow to simultaneously form the third via, the first interconnect trench, and the second interconnect trench in a subsequent etch.
In the step, the etching process in the step may be implemented by wet etching, dry etching or a combination of the two methods.
Referring to fig. 9, a patterned second mask layer 108 is formed on the hard mask layer 106, where the second mask layer 108 exposes the first through hole 111 and the second through hole 121, and a peripheral area of the first through hole 111 and a peripheral area of the second through hole 121, and covers other areas of the hard mask layer 106;
the peripheral area of the first via 111 exposed by the second mask layer 108 is used to define the location of the first interconnect trench, and the peripheral area of the second via 121 exposed by the second mask layer 108 is used to define the location of the second interconnect trench. The first interconnection trench is used for penetrating through the first via 111, the second interconnection trench is used for penetrating through the second via 121, in the subsequent step of forming the metal plug, the interconnection trench is used for forming an interconnection line structure of the metal plug, and the via is used for forming a plug structure of the metal plug.
The second mask layer 108 may be a photoresist layer, which may be a positive photoresist or a negative photoresist, and through photolithography and development processes, the photoresist layer exposing the first through hole 111, the second through hole 121, and the peripheral areas of the first through hole 111 and the second through hole 121 and covering the other areas of the hard mask layer may be formed.
Referring to fig. 10, with the second mask layer as a mask, the second dielectric layer 102 and the first etch stop layer 104 remaining in the first through hole 111, and the hard mask layer 106 and a portion of the third dielectric layer 103 located in the peripheral area of the first through hole 111 and the peripheral area of the second through hole 111 are removed by etching.
A through hole penetrating the second dielectric layer 102 and the first through hole 111 is taken as a third through hole 113, a portion of the third dielectric layer 103 in the peripheral area of the first through hole 111 is taken as a first interconnection trench 112, and a portion of the third dielectric layer 103 in the peripheral area of the second through hole 121 is taken as a second interconnection trench 122.
The second dielectric layer 102 and the first etching stop layer 104, and the hard mask layer 106 and the third dielectric layer 103 may be etched by dry etching, wet etching, or a combination of the two methods.
After the etching step is completed, the second mask layer is further removed in the embodiment of the invention.
Referring to fig. 11, the interconnect structure barrier layer is removed.
And removing the interconnection structure barrier layer to expose the second metal interconnection structure, so as to realize the connection of the second metal interconnection structure and the metal plug formed subsequently.
Specifically, a specific removal process and corresponding process parameters may be determined according to the material of the barrier layer of the interconnect structure.
In this embodiment, a wet etching process may be used to remove the barrier layer of the interconnect structure. Specifically, in the wet etching process, the etching solution is a DHF solution or an EKC solution. The DHF solution is a hydrofluoric acid solution, and specifically, a dilute hydrofluoric acid solution may be used in the embodiment of the present invention, for example, the volume ratio is less than or equal to 20%, for example, 10%, 5%, or 2%; the EKC solution is an etching solution containing Hydroxylamine (HDA), 2- (2-aminoethoxy) ethanol (DGA), and Catechol (Catechol) as main components.
In an alternative example, if the material of the barrier layer of the interconnect structure is RuO2RuO can also be caused by reduction2And reduction to metal Ru can simultaneously realize elimination of the barrier layer of the interconnection structure and generation of metal at the bottom of the second through hole.
Referring to fig. 12 to 13, a first metal plug connected to the first metal interconnection structure and a second metal plug connected to the second metal interconnection structure are formed in the first via, the second via, and the third via, respectively.
Specifically, the first metal interconnection structure and the second metal interconnection structure are led out by forming corresponding metal plug structures.
Wherein, the materials of the first metal plug and the second metal plug are the same as the materials of the first metal interconnection structure and the second metal interconnection structure, so that the corresponding structures are lattice matched and tightly connected.
In this embodiment, the process of forming the first metal plug connected to the first metal interconnection structure and the second metal plug connected to the second metal interconnection structure respectively may include:
referring to fig. 12, a metal material layer 109 is deposited, wherein the metal material layer 109 completely covers the first via, the second via, the third via, and the first interconnection trench located in the peripheral area of the first via and the second interconnection trench located in the peripheral area of the second via.
The metal material layer 109 covers the corresponding via and interconnect trench to connect with the first metal interconnect structure 110 and the second metal interconnect structure 120, and forms a corresponding metal plug in a subsequent step.
The material of the metal material layer 109 is the same material as the first metal interconnection structure 110 and the second metal interconnection structure 120, so as to achieve better electrical characteristics and lattice matching.
Wherein the metallic material layer 109 may be deposited using a CVD process.
Referring to fig. 13, the metal material layer is polished to have the metal material layer remaining in the third via, the first via, and the first interconnection trench as a first metal plug 115, and to have the metal material layer remaining in the second via and the second interconnection trench as a second metal plug 125.
In this step, the metal material layer outside the first interconnection trench and the second interconnection trench is removed by polishing, so as to obtain the first metal plug 115 located in the third via, the first via, and the first interconnection trench, and the second metal plug 125 located in the second via and the second interconnection trench.
Wherein, the plug part of the first metal plug 115 is located in the third via hole and the first via hole, the interconnect structure of the first metal plug 115 is located in the first interconnect trench, the corresponding plug part of the second metal plug 125 is located in the second via hole, and the interconnect structure of the second metal plug 125 is located in the second interconnect trench,
in this embodiment, the hard mask layer 106 is simultaneously removed by grinding in this step, so that it is not necessary to perform other processes to remove the hard mask layer 106.
Specifically, the polishing process may be a mechanical chemical polishing process, and the invention is not limited herein.
It can be seen that in the method for forming a super via according to the embodiment of the present invention, when the second via exposing the second metal interconnection structure is formed, the formed barrier layer of the interconnection structure is only located on the surface of the exposed second metal interconnection structure through the selective growth process, and the structures at other positions are not affected, so that the second metal interconnection structure can be protected from the influence of the corresponding process in the process of forming the third via.
Referring to fig. 10, an embodiment of the present invention still further provides a semiconductor device, including:
a first dielectric layer 101, a second dielectric layer 102 and a third dielectric layer 103 which are sequentially positioned on the surface of the semiconductor substrate 100; a first metal interconnection structure 110 is arranged in the first dielectric layer 101, and a second metal interconnection structure 120 is arranged in the second dielectric layer 102; a first via 111 and a second via 121 penetrating through the third dielectric layer 103, wherein the bottom of the second via 121 is connected to the second metal interconnection structure 120, and an interconnection structure barrier layer 130 covering the second metal interconnection structure 120 is formed in the second via 121; a third via 113 penetrating through the first dielectric layer 101 and exposing the first metal interconnection structure 110, wherein the third via 113 is communicated with the first via 111.
Specifically, the semiconductor substrate 100 may be a silicon substrate, a silicon germanium substrate, or other semiconductor substrates known in the art, and a transistor, an interconnection line, a plug, or other semiconductor devices may be formed in the semiconductor substrate 100, and those skilled in the art may set the semiconductor substrate according to actual needs.
The first dielectric layer 101, the second dielectric layer 102, and the third dielectric layer 103 are made of low-k materials, and specifically, the low-k materials may be SiO2SiOF, SiCOH, SiO, SiCO, or SiCON.
A first etching barrier layer 104 is further disposed between the first dielectric layer 101 and the second dielectric layer 102, a second etching barrier layer 105 is further disposed between the second dielectric layer 102 and the third dielectric layer 103, and a hard mask layer 106 is further disposed on the surface of the third dielectric layer 103.
The material of the first etch stop layer 104 and the second etch stop layer 105 may be silicon nitride (SiN), and in other embodiments of the present invention, the first etch stop layer and the second etch stop layer may also be one or more of amorphous germanium, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, or silicon oxycarbonitride.
The hard mask layer 106 may include a dielectric hard mask layer and a metal hard mask layer (not shown in the figure), the material of the dielectric hard mask layer may be one or a combination of several of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide and silicon nitride containing carbon, and the material of the metal hard mask layer may be titanium nitride, copper nitride or aluminum nitride.
The dielectric hard mask layer is used for improving the adhesion between the third dielectric layer 103 and the metal hard mask layer, and is used as a protective layer of the third dielectric layer 103 to prevent metal atoms in the metal hard mask layer from diffusing into the third dielectric layer 103, so that the influence on the k value of the third dielectric layer 103 is avoided, and electric leakage is prevented.
In this embodiment, the first metal interconnection structure 110 in the first dielectric layer 101 may be understood as a metal wiring structure at a lower layer, and a corresponding connection needs to be made through a super via, and the second metal interconnection structure 120 in the second dielectric layer 102 may be understood as a metal wiring structure at a higher layer, and a corresponding connection needs to be made through a conventional via.
The material of the first metal interconnection structure 110 and the second metal interconnection structure 120 may be one or more of W, Al, Ag, Cr, Co, Ni, Pt, Ti, Ta, Ru, or Cu, which is not particularly limited in the present invention. Specifically, in the present embodiment, the material of the first metal interconnection structure 110 and the second metal interconnection structure 120 may be copper.
Here, the first via 111 may be understood as an initial via in a process of forming a super via, and the second via 121 may be understood as a conventional via for exposing the second metal interconnection structure located at a higher level.
And the selective etching ratio of the interconnection structure barrier layer to the second dielectric layer is greater than or equal to 5.
Specifically, the material of the barrier layer of the interconnection structure is AlN, TiN, RuO2、TiO2、HfN、ZfO2、Al2O3W, Ru or a metal alloy material.
The thickness of the barrier layer of the interconnection structure is not too large or too small. If the thickness of the barrier layer is too large, the barrier layer of the interconnection structure is not easy to remove, and if the thickness of the barrier layer of the interconnection structure is too small, the barrier layer of the interconnection structure cannot play a corresponding protection role, so that the second metal interconnection structure below the barrier layer of the interconnection structure is possibly damaged in the etching process. Therefore, in the present embodiment, the thickness of the barrier layer of the interconnect structure is set to
The third via 113 is connected to the first via 111, and the first metal interconnection structure 110 is exposed from the third via 113.
In this embodiment, a portion of the third dielectric layer 103 in the peripheral region of the first via 111 further includes a first interconnection trench 112, and a portion of the third dielectric layer in the peripheral region of the second via further includes a second interconnection trench 122.
The first interconnection trench 112 is through the first via 111, the second interconnection trench 122 is through the second via 121, and when a metal plug is formed subsequently, the interconnection trench is used for forming an interconnection line structure of the metal plug, and the via is used for forming a plug structure of the metal plug.
The semiconductor device may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a specific description of the semiconductor device in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (18)
1. A method for forming a super via, comprising:
providing a semiconductor device, wherein the semiconductor device comprises a first dielectric layer, a second dielectric layer and a third dielectric layer which are sequentially positioned on the surface of a semiconductor substrate, a first metal interconnection structure is arranged in the first dielectric layer, and a second metal interconnection structure is arranged in the second dielectric layer;
forming a first through hole and a second through hole penetrating through the third dielectric layer, wherein the second through hole exposes the second metal interconnection structure;
selectively growing an interconnection structure barrier layer, wherein the interconnection structure barrier layer is grown only on the surface of the exposed second metal interconnection structure;
and forming a third through hole penetrating through the second dielectric layer, wherein the third through hole is communicated with the first through hole, and the first metal interconnection structure is exposed out of the third through hole.
2. The method of forming a hyper via of claim 1, further comprising:
removing the interconnection structure barrier layer;
and forming a first metal plug connected with the first metal interconnection structure and a second metal plug connected with the second metal interconnection structure in the first through hole, the second through hole and the third through hole.
3. The method of claim 1, wherein the selective etch ratio of the barrier layer of the interconnect structure to the second dielectric layer is greater than or equal to 5.
4. The method of claim 1, wherein the interconnect structure barrier layer is made of AlN, TiN, RuO2、TiO2、HfN、ZfO2、Al2O3Or a metal alloy material.
5. The method of forming the super via of claim 1, wherein the thickness of the barrier layer of the interconnect structure is
6. The method of forming a hyper via of claim 2, wherein the first metal interconnect structure, the second metal interconnect structure, the first metal plug, and the second metal plug are of the same material.
7. The method of forming the super via of claim 2, wherein the interconnect structure barrier layer is removed using a wet etch process.
8. The method for forming the super via according to claim 7, wherein in the wet etching process, the etching solution is DHF solution or EKC solution.
9. The method for forming the super via according to claim 2, wherein a first etching barrier layer is further formed between the first dielectric layer and the second dielectric layer, a second etching barrier layer is further formed between the second dielectric layer and the third dielectric layer, and a hard mask layer is further formed on the surface of the third dielectric layer.
10. The method of forming the super via of claim 9, wherein the forming the first via and the second via through the third dielectric layer comprises:
forming a first patterned mask layer on the hard mask layer, wherein the first mask layer exposes regions for forming a first through hole and a second through hole and covers other regions of the hard mask layer;
and etching and removing the hard mask layer, the third dielectric layer and the second etching barrier layer exposed by the first mask layer by taking the first mask layer as a mask, forming the first through hole in the area corresponding to the first through hole, and forming the second through hole in the area corresponding to the second through hole.
11. The method of forming the super via of claim 10, wherein the forming a third via through the second dielectric layer comprises:
etching and removing part of the second dielectric layer in the first through hole by taking the hard mask layer as a mask;
forming a graphical second mask layer on the hard mask layer, wherein the second mask layer exposes the first through hole, the second through hole, a peripheral area of the first through hole and a peripheral area of the second through hole, and covers other areas of the hard mask layer;
and etching and removing the second dielectric layer and the first etching barrier layer which are left in the first through hole, and the hard mask layer and a part of third dielectric layer which are positioned in the peripheral area of the first through hole and the peripheral area of the second through hole, wherein the through hole which is positioned in the second dielectric layer and is communicated with the first through hole is used as a third through hole, the part which is positioned in the peripheral area of the first through hole in the third dielectric layer is used as a first interconnection groove, and the part which is positioned in the peripheral area of the second through hole in the third dielectric layer is used as a second interconnection groove.
12. The method of claim 11, wherein the step of forming a first metal plug connected to the first metal interconnect structure and a second metal plug connected to the second metal interconnect structure in the first via, the second via, and the third via, respectively, comprises:
depositing a metal material layer, wherein the metal material layer completely covers the first through hole, the second through hole, the third through hole, a first interconnection groove located in the peripheral area of the first through hole and a second interconnection groove located in the peripheral area of the second through hole;
and grinding the metal material layer, wherein the metal material layer left in the third through hole, the first through hole and the first interconnection groove is taken as a first metal plug, and the metal material layer left in the second through hole and the second interconnection groove is taken as a second metal plug.
13. A semiconductor device, comprising:
the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially positioned on the surface of the semiconductor substrate;
the first dielectric layer is internally provided with a first metal interconnection structure, and the second dielectric layer is internally provided with a second metal interconnection structure;
the bottom of the second through hole is communicated to the second metal interconnection structure, and an interconnection structure barrier layer covering the second metal interconnection structure is formed in the second through hole;
and a third through hole penetrating through the first dielectric layer and exposing the first metal interconnection structure, wherein the third through hole is communicated with the first through hole.
14. The semiconductor device of claim 13, wherein a selective etch ratio of the interconnect structure barrier layer to the second dielectric layer is greater than or equal to 5.
15. The semiconductor device of claim 13, wherein the interconnect structure barrier layer is of a material selected from the group consisting of AlN, TiN, RuO2、TiO2、HfN、ZfO2、Al2O3W, Ru or a metal alloy material.
16. The semiconductor device of claim 13, wherein the interconnect structure barrier layer has a thickness of
17. The semiconductor device according to claim 13, wherein a first etching barrier layer is further disposed between the first dielectric layer and the second dielectric layer, a second etching barrier layer is further disposed between the second dielectric layer and the third dielectric layer, and a hard mask layer is further disposed on a surface of the third dielectric layer.
18. The semiconductor device of claim 13, wherein a portion of the third dielectric layer in the peripheral region of the first via further comprises a first interconnect trench, and a portion of the third dielectric layer in the peripheral region of the second via further comprises a second interconnect trench.
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