JP2013084662A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need to form a groove for embedding a conductor in a part located at a via layer insulating film of a seal ring in a step of forming a via hole in the via layer insulating film.SOLUTION: A seal groove 121 is formed in a via layer insulating film 40 and a second wiring layer insulating film 50. A plurality of holes 31 are formed in an etching stopper layer 30. A second seal conductor pattern 120 is embedded in the plurality of holes 31 and the seal groove 121. In the etching stopper layer 30, a part located at a bottom of the seal groove 121 serves as a thin film part 32 and is thinner than a part in which the seal groove 121 is not formed.

Description

  The present invention relates to a semiconductor device having a seal ring and a method for manufacturing the semiconductor device.

  The semiconductor device is provided with a seal ring for protecting the internal circuit from moisture and the like. For example, Patent Document 1 describes that in a multilayer wiring layer having a damascene structure, grooves are formed in each of the wiring layer and the via layer, and copper is embedded in these grooves to form a seal ring.

JP 2004-297022 A

  When the opening is formed in the film by etching, the optimum etching condition varies depending on the shape of the opening. For this reason, when a plurality of types of openings having different shapes are formed in the same film, it is very difficult to optimally process each other's shape.

  The seal ring generally uses a groove shape. On the other hand, an internal circuit is formed inside the seal ring. In the internal circuit, a plurality of hole-shaped vias are formed in the via layer insulating film. For this reason, when a portion of the seal ring located in the via layer insulating film is formed into a groove shape, it is necessary to form a hole-shaped via and a groove-shaped seal ring in the same etching process. If the via shape cannot be optimally processed for the reason described above, the yield of the semiconductor device may be reduced. For this reason, it is preferable not to process a groove shape such as a seal ring at the same time in the step of forming a via hole in the via layer insulating film.

According to the present invention, a first wiring layer;
A first seal conductor pattern embedded in the first wiring layer;
An etching stopper layer formed on the first wiring layer;
A via layer insulating film formed on the etching stopper layer;
A wiring layer insulating film formed on the via layer insulating film;
A seal groove penetrating the wiring layer insulating film and the via layer insulating film;
A plurality of holes that are spaced apart from each other in the etching stopper layer and connect the seal groove and the first seal conductor pattern;
A second seal conductor pattern embedded in the seal groove and the plurality of holes;
With
The etching stopper layer located at the bottom of the seal groove is thinner than the etching stopper layer located in a region where the seal groove is not formed,
A semiconductor device in which at least a part of a seal ring is formed by the first seal conductor pattern and the second seal conductor pattern is provided.

Forming a first wiring layer embedded with a first seal conductor pattern;
Forming an etching stopper film and a via layer insulating film in this order on the first wiring layer, and further forming a wiring layer insulating film directly on the via layer insulating film;
Forming a plurality of holes located on the first seal conductor pattern on the wiring layer insulating film and the via layer insulating film;
By selectively removing the wiring layer insulating film, a sealing groove whose bottom surface is connected to the plurality of holes is formed in the wiring layer insulating film, and the via layer insulating film located at the bottom of the sealing groove is formed. Thinning process,
Etching the etching stopper film using the via layer insulating film located at the bottom of the seal groove as a mask allows the plurality of holes to penetrate the etching stopper film and the via located at the bottom of the seal groove. Removing the layer insulating film, and thinning or removing the etching stopper film located at the bottom of the seal groove; and
Forming a second conductor pattern by embedding a conductor in the plurality of holes and the seal groove;
With
A method of manufacturing a semiconductor device in which at least a part of a seal ring is formed by the first conductor pattern and the second conductor pattern is provided.

  According to the present invention, the etching stopper layer located at the bottom of the seal groove is thinner than the etching stopper layer located in a region where the seal groove is not formed. For this reason, the lower surface of the seal groove is located between the upper surface and the bottom surface of the etching stopper layer located in the region where the seal groove is not formed. The etching stopper layer is less likely to pass moisture than the via layer insulating film. For this reason, even if a hole is formed in the etching stopper layer instead of a groove, the function of the seal ring can be maintained. In addition, since it is not necessary to form a groove in the etching stopper layer, a plurality of holes are formed instead of the groove in the portion of the via layer insulating film that becomes the seal ring in the process of forming the via hole in the via layer insulating film. can do. And by narrowing the space | interval of this hole, at the time of the etching process in a post process, these several holes can be connected and it can be set as a groove | channel. Therefore, in the step of forming a via hole in the via layer insulating film, it is not necessary to form a groove in a portion of the seal ring located in the via layer insulating film.

  According to the present invention, in the step of forming a via hole in the via layer insulating film, it is not necessary to form a groove for embedding a conductor in a portion of the seal ring located in the via layer insulating film.

1 is a plan view showing a configuration of a semiconductor device 10 according to a first embodiment. It is a figure which shows the one part layer of the AA'-A "cross section of FIG. It is a figure which shows the one part layer of the BB 'cross section of FIG. It is a top view which shows the shape of an etching stopper layer. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIGS. It is sectional drawing which shows the manufacturing method of the semiconductor device shown in FIGS. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the semiconductor device which concerns on 3rd Embodiment. FIG. 10 is a plan view showing a layout of an etching stopper layer 30 in FIG. 9.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

(First embodiment)
FIG. 1 is a plan view showing the configuration of the semiconductor device 10 according to the first embodiment. The semiconductor device 10 includes an internal circuit 12 and a seal ring 100. The seal ring 100 is formed along the entire edge of the semiconductor device 10 and surrounds the entire circumference of the internal circuit 12. The seal ring 100 prevents moisture and the like from entering the internal circuit 12. The internal circuit 12 includes a logic circuit, but may include at least one of a memory circuit and an analog circuit in addition to the logic circuit.

  2 shows a part of the layer in the section AA′-A ″ in FIG. 1, and FIG. 3 shows a part of the layer in the section BB ′ in FIG. 1. 2 and 3 show the same layers. The semiconductor device 10 has a multilayer wiring layer. 2 and 3, the multilayer wiring layer has a structure in which a first wiring layer insulating film 20, an etching stopper layer 30, a via layer insulating film 40, and a second wiring layer insulating film 50 are stacked in this order. Have. In the present embodiment, the second wiring layer insulating film 50 is formed directly on the via layer insulating film 40. That is, no etching stopper layer is formed between the via layer insulating film 40 and the second wiring layer insulating film 50.

  The first wiring layer insulating film 20, the via layer insulating film 40, and the second wiring layer insulating film 50 are formed of a low dielectric constant film having a dielectric constant lower than that of silicon oxide, for example. This low dielectric constant film is, for example, SiOC or a porous film thereof. Among these, the thickness of the via layer insulating film 40 is, for example, not less than 100 nm and not more than 300 nm, and the thickness of the second wiring layer insulating film 50 is, for example, not less than 100 nm and not more than 300 nm. In the case where the via layer insulating film 40 and the second wiring layer insulating film 50 are formed of a low dielectric constant film, moisture is supplied to the internal circuit 12 through the altered layer formed on the surface layer of the low dielectric constant film. Is easy to penetrate. Therefore, the seal ring 100 is preferably formed in the via layer insulating film 40 and the second wiring layer insulating film 50 without a gap.

  The etching stopper layer 30 is made of, for example, SiN or SiCN. The thickness of the etching stopper layer 30 is, for example, not less than 10 nm and not more than 50 nm.

  A first seal conductor pattern 110 is embedded in the first wiring layer insulating film 20. A second seal conductor pattern 120 is embedded in the etching stopper layer 30, the via layer insulating film 40, and the second wiring layer insulating film 50.

  Specifically, a seal groove 121 is formed in the via layer insulating film 40 and the second wiring layer insulating film 50. In addition, a plurality of holes 31 are formed in the etching stopper layer 30. The hole 31 connects the bottom surface of the seal groove 121 and the top surface of the first seal conductor pattern 110. The second seal conductor pattern 120 is embedded in the plurality of holes 31 and the seal groove 121. In the etching stopper layer 30, the portion located on the bottom surface of the seal groove 121 is a thin film portion 32, and is thinner than the portion where the seal groove 121 is not formed. Therefore, as shown in FIG. 3, when viewed in the stacking direction of the multilayer wiring layer, the bottom surface of the seal groove 121 enters the etching stopper layer 30, and the seal groove 121 is formed in the etching stopper layer 30. It is located between the top and bottom of the part that is not.

  As shown in FIG. 2, the first wiring 200 and the second wiring 220 are formed in the internal circuit 12. The first wiring 200 is embedded in the first wiring layer insulating film 20, and the second wiring 220 is embedded in the second wiring layer insulating film 50. However, if the second wiring layer 220 does not reach the etching stopper layer 30, a part of the second wiring layer 220 may enter the via layer insulating film 40. In this figure, the via layer insulating film 40 and the second wiring layer insulating film 50 are different layers, but these two layers may be one insulating layer. The second wiring 220 and the first wiring 200 are connected to each other through the via 210. That is, the second wiring 220 is connected to the upper end of the via 210, and the first wiring 200 is connected to the lower end of the via 210. The via 210 is formed integrally with the second wiring 220. That is, the via 210 is formed in the same process as the first seal conductor pattern 110, and the second wiring 220 and the via 210 are formed in the same process as the seal groove 121. The diameter of the hole 31 is not less than 0.7 times and not more than 1.5 times the diameter of the via 210, for example. Preferably, the width of the via 210 is equal to the width of the hole 31.

  2 and 3 show a part of the multilayer wiring layer of the semiconductor device 10. That is, in the multilayer wiring layer of the semiconductor device 10, the etching stopper layer 30, the via layer insulating film 40, and the second wiring layer insulating film 50 are repeatedly formed until the required number of layers is reached. However, the plurality of via layer insulating films 40 do not need to have the same thickness, and the plurality of second wiring layer insulating films 50 do not need to have the same thickness. Further, the plurality of etching stopper layers 30 need not have the same thickness.

FIG. 4 is a plan view showing the shape of the etching stopper layer 30. A portion of the etching stopper layer 30 that overlaps with the seal groove 121 is a thin film portion 32. A plurality of holes 31 are formed in the etching stopper layer 30. When viewed in the width direction of the seal groove 121, the plurality of holes 31 are arranged in a line along the direction in which the seal groove 121 extends. The center distance _{L 1} between adjacent holes 31, the width of the hole 31 in the direction in which the seal groove 121 is extended (the diameter of the hole 31) W 2 times or less, preferably not more than 3/2. The center distance _{L 1} between adjacent holes 31 is, for example, 100nm or 200nm or less.

  Each of FIGS. 5 and 6 is a cross-sectional view illustrating a method of manufacturing the semiconductor device shown in FIGS. First, as shown in FIG. 5A, a first wiring layer insulating film 20 is formed. The first wiring layer insulating film 20 is formed on, for example, a semiconductor substrate (not shown). Elements such as transistors are formed on the semiconductor substrate. Further, at least one wiring layer may be formed between the first wiring layer insulating film 20 and the semiconductor substrate plate.

  Next, a groove for embedding the first seal conductor pattern 110 and a groove for embedding the first wiring 200 are formed in the first wiring layer insulating film 20. Next, a metal film such as a copper film is formed in these trenches and on the first wiring layer insulating film 20. Next, the metal film located on the first wiring layer insulating film 20 is removed using the CMP method. Thereby, the first seal conductor pattern 110 and the first wiring 200 are formed.

  Next, the etching stopper layer 30, the via layer insulating film 40, and the second wiring layer insulating film 50 are formed in this order on the first seal conductor pattern 110, the first wiring 200, and the first wiring layer insulating film 20. To do. The etching stopper layer 30, the via layer insulating film 40, and the second wiring layer insulating film 50 are formed by, for example, a CVD method.

  Next, as shown in FIG. 5B, a resist pattern 60 is formed on the second wiring layer insulating film 50, and the second wiring layer insulating film 50 and the via layer insulating film 40 are etched using the resist pattern 60 as a mask. . At this time, the etching stopper layer 30 functions as an etching stopper. Thereby, a plurality of holes 52 and holes 42 are formed in the second wiring layer insulating film 50 and the via layer insulating film 40. The hole 52 is a hole for forming the hole 31 in the etching stopper layer 30 and is located in a region where the seal ring 100 is formed. The distance between the centers of the adjacent holes 52 is not more than twice the width of the hole 52 (the diameter of the hole 52) in the direction in which the seal groove 121 extends. Alternatively, the distance between the centers of adjacent holes 52 is, for example, not less than 100 nm and not more than 200 nm. The hole 42 is a hole for forming the via 210 and is located on the first wiring 200. Thereafter, the resist pattern 60 is removed.

  Next, as shown in FIG. 6A, a resist pattern 62 is formed on the second wiring layer insulating film 50. The resist pattern 62 has an opening in each of the region where the second wiring 220 is embedded and the region where the seal groove 121 is formed in the second wiring layer insulating film 50. Next, the second wiring layer insulating film 50 is etched using the resist pattern 62 as a mask. As a result, the groove 54 and the seal groove 121 are formed in the second wiring layer insulating film 50. The groove 54 is a groove for embedding the second wiring 220 and overlaps the hole 42 in plan view.

  As described above, the center-to-center distance is not more than twice the width of the hole 52 (the diameter of the hole 52) in the direction in which the seal groove 121 extends. Alternatively, the distance between the centers of adjacent holes 52 is, for example, not less than 100 nm and not more than 200 nm. For this reason, when the seal groove 121 is formed, a portion of the via layer insulating film 40 located between the holes 52 is etched and thinned. In this step, the thickness of the portion located between the holes 52 in the via layer insulating film 40 is, for example, 50 nm or less.

  Thereafter, the resist pattern 62 is removed.

  Next, as shown in FIG. 6B, the etching stopper layer 30 is etched using the second wiring layer insulating film 50 and the via layer insulating film 40 as a mask. Thereby, the etching stopper layer 30 located at the bottom of the hole 42 is removed, and the first wiring 200 is exposed at the bottom of the hole 42. Further, the etching stopper layer 30 located at the bottom of the hole 52 is also removed, and the hole 31 is formed.

  Further, by this etching process, the via layer insulating film 40 and the portion located between the holes 52 are also removed. As a result, the portion located between the holes 31 in the etching stopper layer 30 is also etched, and the thin film portion 32 is formed.

  Thereafter, a conductive film, for example, a copper film is formed in each of the hole 31, the seal groove 121, the hole 42, and the groove 54 and on the second wiring layer insulating film 50. Next, the conductive film located on the second wiring layer insulating film 50 is removed using a CMP method. Thus, the second seal conductor pattern 120, the via 210, and the second wiring 220 are formed (see FIG. 2).

  Next, the operation and effect of this embodiment will be described. According to the present embodiment, the portion of the etching stopper layer 30 located at the bottom of the seal groove 121 is thinner than the portion of the etching stopper layer 30 located in the region where the seal groove 121 is not formed, and the thin film portion 32. It has become. For this reason, the lower surface of the seal groove 121 enters the etching stopper layer 30. The etching stopper layer 30 is less likely to infiltrate moisture than the via layer insulating film 40. Therefore, even if the part located in the etching stopper layer 30 in the seal ring 100 is not in a groove shape and is in a dot shape, the sealing function of the seal ring 100 is maintained.

  In the step of forming the via hole 42 in the via layer insulating film 40, a plurality of holes 52 are formed in the portion of the via layer insulating film 40 that becomes the seal ring 100 instead of the groove. The plurality of holes 52 are finally connected to form a groove. Therefore, in the step of forming the via hole 42 in the via layer insulating film 40, it is not necessary to form a groove for embedding the conductor in the portion of the via layer insulating film 40 that becomes the seal ring 100. For this reason, the hole 42 and the hole 52 can be formed with a high yield.

  For example, when a groove is formed in a portion of the via layer insulating film 40 that becomes the seal ring 100, the groove is less likely to be formed than the hole 42. For this reason, the condition for sufficiently forming the groove is an over-etching condition for the hole 42. In this case, when the hole 42 is formed, the hole 42 penetrates the etching stopper layer 30, so that the metal (for example, copper) constituting the first wiring 200 can be sputtered and adhere to the side wall of the hole 42. Sex comes out. In this case, a poor embedding of the via 210 occurs.

  Further, when the etching time is long, many deposits are generated. Since this deposit obstructs etching, the etching time becomes longer.

  Further, as the etching time becomes longer, it becomes necessary to increase the resist pattern in order to withstand this. However, the resolution when forming the resist pattern decreases as the thickness of the resist pattern increases. For this reason, in order to advance miniaturization, the etching time cannot be lengthened.

  In this embodiment, it can suppress that such a problem arises.

(Second Embodiment)
7 and 8 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. In this semiconductor device manufacturing method, as shown in FIG. 7A, the steps up to the step of forming the hole 42 and the hole 52 (FIG. 5B in the first embodiment) are the same as those in the first embodiment. It is.

  After the holes 42 and 52 are formed, a resist pattern 62 is formed on the second wiring layer insulating film 50 as shown in FIG. The resist pattern 62 is the same as that in the first embodiment. Next, the second wiring layer insulating film 50 is etched using the resist pattern 62 as a mask. As a result, the groove 54 and the seal groove 121 are formed in the second wiring layer insulating film 50. Further, when the seal groove 121 is formed, the entire portion of the via layer insulating film 40 located between the holes 52 is etched and removed. Thereafter, the resist pattern 62 is removed.

  Next, as shown in FIG. 8A, the etching stopper layer 30 is etched using the second wiring layer insulating film 50 and the via layer insulating film 40 as a mask. As a result, the etching stopper layer 30 located at the bottom of the hole 42 is removed, and the first wiring 200 is exposed on the entire surface of the bottom of the hole 42. Further, the etching stopper layer 30 located at the bottom of the seal groove 121 is also removed. Therefore, the first seal conductor pattern 110 is exposed over the entire bottom surface of the seal groove 121.

  Next, as shown in FIG. 8B, the second seal conductor pattern 120 is embedded in the seal groove 121, and the via 210 and the second wiring 220 are embedded in the hole 42 and the groove 54. This step is the same as in the first embodiment.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. In addition, since the seal groove 121 does not have the etching stopper layer 30, it is possible to further suppress moisture from entering from the interface between the first seal conductor pattern 110 and the second seal conductor pattern 120.

(Third embodiment)
FIG. 9 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment. FIG. 10 is a plan view showing a layout of the etching stopper layer 30 in the semiconductor device shown in FIG. 9, and corresponds to FIG. 4 in the first embodiment. FIG. 9 shows a CC ′ cross section of FIG. 10 and corresponds to FIG. 3 in the first embodiment.

  The semiconductor device according to the present embodiment has the same configuration as that of the semiconductor device according to the first embodiment except for the layout of the holes 31. In the present embodiment, the holes 31 form a plurality of rows (two rows in the example shown in the drawing) extending along the direction in which the seal groove 121 extends (the left-right direction in FIG. 10). The holes 31 belonging to rows adjacent to each other are alternately arranged when viewed in the direction in which the seal groove 121 extends.

Further, when viewed in the width direction of the sealing groove 121 (vertical direction in FIG. 10), the distance L ₂ of the center of adjacent rows is no more than two times the width of the hole 31 (the diameter of the hole 31), preferably 3 / 2 times or less, for example, 100 nm or more and 200 nm or less.

  Also according to this embodiment, the same effect as that of the first embodiment can be obtained. Further, the width of the seal groove 121, that is, the width of the seal ring 100 can be increased. Further, in the seal groove 121, the holes 31, that is, the regions where the etching stopper layer 30 is not provided are arranged in a staggered manner. For this reason, it can further suppress that a water | moisture content permeates from the interface of the 1st seal conductor pattern 110 and the 2nd seal conductor pattern 120. FIG.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Internal circuit 20 1st wiring layer insulating film 30 Etching stopper layer 31 Hole 32 Thin film part 40 Via layer insulating film 42 Hole 50 2nd wiring layer insulating film 52 Hole 54 Groove 60 Resist pattern 62 Resist pattern 100 Seal ring 110 First seal conductor pattern 120 Second seal conductor pattern 121 Seal groove 200 First wiring 210 Via 220 Second wiring

Claims (11)

A first wiring layer;
A first seal conductor pattern embedded in the first wiring layer;
An etching stopper layer formed on the first wiring layer;
A via layer insulating film formed on the etching stopper layer;
A wiring layer insulating film formed on the via layer insulating film;
A seal groove penetrating the wiring layer insulating film and the via layer insulating film;
A plurality of holes that are spaced apart from each other in the etching stopper layer and connect the seal groove and the first seal conductor pattern;
A second seal conductor pattern embedded in the seal groove and the plurality of holes;
With
The etching stopper layer located at the bottom of the seal groove is thinner than the etching stopper layer located in a region where the seal groove is not formed,
A semiconductor device in which at least a part of a seal ring is formed by the first seal conductor pattern and the second seal conductor pattern. The semiconductor device according to claim 1,
The wiring layer insulating film is a semiconductor device formed directly on the via layer insulating film. The semiconductor device according to claim 1 or 2,
Located inside the seal ring, comprising a via formed in the via layer insulating film,
A semiconductor device in which a size of the via is the same as a size of the hole in a plan view. The semiconductor device according to claim 3.
A first wiring formed in the first wiring layer and connected to a lower end of the via;
A second wiring embedded in the wiring layer insulating film and connected to an upper end of the via;
With
A semiconductor device in which the via and the second wiring are integrally formed. In the semiconductor device according to any one of claims 1 to 4,
In plan view, the distance between the centers of adjacent holes is not more than twice the width of the holes in the direction in which the seal groove extends. In the semiconductor device according to any one of claims 1 to 5,
In plan view, the distance between the centers of adjacent holes is 3/2 times or less the diameter of the holes. In the semiconductor device according to any one of claims 1 to 6,
The semiconductor device, wherein the etching stopper layer is a SiN layer or a SiCN layer. Forming a first wiring layer embedded with a first seal conductor pattern;
Forming an etching stopper film and a via layer insulating film in this order on the first wiring layer, and further forming a wiring layer insulating film directly on the via layer insulating film;
Forming a plurality of holes located on the first seal conductor pattern on the wiring layer insulating film and the via layer insulating film;
By selectively removing the wiring layer insulating film, a sealing groove whose bottom surface is connected to the plurality of holes is formed in the wiring layer insulating film, and the via layer insulating film located at the bottom of the sealing groove is formed. Thinning process,
Etching the etching stopper film using the via layer insulating film located at the bottom of the seal groove as a mask allows the plurality of holes to penetrate the etching stopper film and the via located at the bottom of the seal groove. Removing the layer insulating film, and thinning or removing the etching stopper film located at the bottom of the seal groove; and
Forming a second conductor pattern by embedding a conductor in the plurality of holes and the seal groove;
With
A method of manufacturing a semiconductor device, wherein at least a part of a seal ring is formed by the first conductor pattern and the second conductor pattern. In the manufacturing method of the semiconductor device according to claim 8,
In plan view, the distance between the centers of adjacent holes is not more than twice the width of the holes in the direction in which the seal groove extends. In the manufacturing method of the semiconductor device according to claim 8 or 9,
A method of manufacturing a semiconductor device, wherein a distance between centers of adjacent holes is 3/2 times or less a diameter of the holes in a plan view. In the manufacturing method of the semiconductor device according to any one of claims 8 to 10,
The method for manufacturing a semiconductor device, wherein the etching stopper layer is a SiN layer or a SiCN layer.

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