JP2010171291A - Semiconductor device and method of manufacturing the semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which suppresses the increase of capacitance between wirings, and to provide a method of manufacturing the same. <P>SOLUTION: A semiconductor device 10 in this embodiment includes a semiconductor substrate 100, an interlayer insulating film 110 (a first interlayer insulating film) formed on the semiconductor substrate 100; an interlayer insulating film 120 (a second interlayer insulating film) which is formed on the interlayer insulating film 110 and which has a lower dielectric constant than that of the interlayer insulating film 110; and a Cu wiring 141, which penetrates the interlayer insulating film 120 and the bottom of which enters the interlayer insulating film 110. The Cu wiring 141 has a shape, in which its width becomes narrower to the lower side. The inclination of the side surface of the Cu wiring 141 in the interlayer insulating film 110 is larger than the inclination of the side surface of the Cu wiring 141 in the interlayer insulating film 120. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  A Cu multilayer wiring of a semiconductor device is usually formed by a damascene method. The damascene method includes a dual damascene method in which a via hole and a wiring groove are simultaneously formed, and a single damascene method in which a via hole and a wiring groove are separately formed.

  Due to the miniaturization of elements in accordance with the recent demand for higher integration, the width of Cu wiring is becoming narrower. Therefore, it is important to reduce the increase in parasitic capacitance between Cu wirings.

In Patent Document 1, an interlayer insulating film 34, an etching stopper film 35, and an upper insulating film 36 on a lower wiring layer are etched into a via hole shape, and then the upper insulating film 36 is etched into a groove shape using the etching stopper film 35. The technique to do is described (FIG. 10). It is described that the etching prevention film 35 can prevent the etching of the interlayer insulating film 34. Examples of the etching stopper film 35 include a SiN film, a SiC film, and a SiO ₂ film.

  As a method of reducing the parasitic capacitance between the wirings, for example, in Patent Document 2, in the wiring groove 44 formed in the low dielectric film 43 on the insulating film 42, the groove width from the top to the bottom is described. Is disclosed (FIG. 11).

JP 2004-119872 A Japanese Patent Laid-Open No. 10-64995

  In the technique described in Patent Document 1, an etching stopper film 35 is formed. Since the etching stop film 35 is made of a SiN film, a SiC film, or the like to stop etching, the dielectric constant is higher than that of a normal interlayer insulating film. Therefore, when the etching stopper film 35 is formed, there is a problem that the capacitance between the wirings increases.

A semiconductor device according to the present invention includes:
A semiconductor substrate and a first interlayer insulating film formed on the semiconductor substrate;
A second interlayer insulating film formed on the first interlayer insulating film and having a dielectric constant lower than that of the first interlayer insulating film;
A wiring penetrating through the second interlayer insulating film and having a bottom portion entering the first interlayer insulating film;
With
The wiring has a shape whose width is narrowed downward at least at the bottom, and the wiring in the first interlayer insulating film is more inclined than the inclination of the side surface of the wiring in the second interlayer insulating film. It is characterized in that the side surface has a large inclination.

A method for manufacturing a semiconductor device according to the present invention includes:
Forming a first interlayer insulating film on the semiconductor substrate;
Forming a second interlayer insulating film having a dielectric constant lower than that of the first interlayer insulating film on the first interlayer insulating film;
Forming a wiring groove penetrating through the second interlayer insulating film and having a bottom portion entering the first interlayer insulating film;
Burying a wiring material in the wiring groove to form a wiring; and
Including
In the step of forming the wiring groove,
The wiring trench is formed such that at least a bottom portion becomes narrower toward the semiconductor substrate, and the slope in the side surface of the wiring trench in the second interlayer insulating film is more than the slope in the first interlayer insulating film. The wiring groove has a large inclination on the side surface.

  In the present invention, the first interlayer insulating film, the second interlayer insulating film having a lower dielectric constant than the first interlayer insulating film, and the second interlayer insulating film are penetrated, and the bottom is the first interlayer insulating film. And a wiring penetrating the film. This wiring has a shape whose width becomes narrower downward, and the inclination of the side surface of the wiring in the first interlayer insulating film is larger than the inclination of the side surface of the wiring in the second interlayer insulating film. Yes. That is, the taper has a taper that becomes narrower downward at least at the bottom, and the taper in the first interlayer insulating film is larger than the taper in the second interlayer insulating film.

  Therefore, the side surface of the wiring in the first interlayer insulating film is inclined in a direction in which the interval between adjacent wirings is increased at least in a portion located in the first interlayer insulating film. Thereby, the space | interval of the wiring in a 1st interlayer insulation film becomes wider than the space | interval of the wirings in a 2nd interlayer insulation film. Therefore, even if the wiring trench reaches the first interlayer insulating film having a high dielectric constant, it is possible to suppress an increase in capacitance between the wirings due to the wiring being formed in the first interlayer insulating film.

  According to the present invention, a semiconductor device in which an increase in capacitance between wirings is suppressed and a manufacturing method thereof are realized.

1 is a cross-sectional view showing a semiconductor device according to a first embodiment. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows an example of the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. They are a partial enlarged sectional view (a), a plan view (b), and a partially enlarged sectional view (c) of the semiconductor device according to the present invention. They are a partial enlarged sectional view (a), a plan view (b) and a partially enlarged sectional view (c) of the semiconductor device according to the present invention. It is the partial expanded sectional view (a) of the semiconductor device as a comparative example, a top view (b), and a partial expanded sectional view (c). It is sectional drawing which shows the modification of a semiconductor device. It is sectional drawing which shows the modification of a semiconductor device. It is sectional drawing which shows the conventional semiconductor device. It is sectional drawing which shows the conventional semiconductor device. It is sectional drawing which shows the semiconductor device as a comparative example.

  Hereinafter, preferred embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted. In the cross-sectional view, the semiconductor device cut along a plane including the central axis of the contact is shown.

(First embodiment)
FIG. 1 is a cross-sectional view showing a semiconductor device 10 according to the first embodiment. In the present embodiment, the semiconductor device 10 has a single damascene structure. The positional relationship between the contact 111 and the Cu wiring 141 cut along the plane including the central axis of the contact 111 is as shown in FIG. FIG. 5A is a partially enlarged cross-sectional view as seen from AA ′ in FIG.

  The semiconductor device 10 in this embodiment includes a semiconductor substrate 100, an interlayer insulating film 110 (first interlayer insulating film) formed on the semiconductor substrate 100, and an interlayer formed on the first interlayer insulating film 110. An interlayer insulating film 120 (second interlayer insulating film) having a dielectric constant lower than that of the insulating film 110 and a Cu wiring 141 penetrating the interlayer insulating film 120 and entering the interlayer insulating film 110 at the bottom are provided. .

  The semiconductor substrate 100 is, for example, a silicon substrate. The semiconductor substrate 100 includes a field effect including a source / drain region 104 formed in the well 102, a gate oxide film 105 formed on the semiconductor substrate 100, and a gate electrode 106 formed on the gate oxide film 105. A transistor (FET) is formed. Further, sidewalls 107 are formed on both side surfaces of the gate electrode 106. Each FET is isolated from other elements by an element isolation region 101 such as STI formed in the semiconductor substrate 100.

  On the semiconductor substrate 100, an interlayer insulating film 110, an interlayer insulating film 120, and a diffusion prevention film 160 formed on the gate electrode 106 are sequentially stacked.

The interlayer insulating film 120 has a dielectric constant lower than that of the interlayer insulating film 110. Examples of the interlayer insulating film 110 include a SiO ₂ film. The interlayer insulating film 120 is a film containing Si, C, O, and H, for example, a SiCOH film. Moreover, the dielectric constant with respect to the vacuum of the interlayer insulating film 110 is, for example, 4.0 to 4.7, and the dielectric constant with respect to the vacuum of the interlayer insulating film 120 is, for example, 1.8 to 3.3.

  That is, in this embodiment, the semiconductor device 10 has the interlayer insulating film 110 and the interlayer insulating film 120 in direct contact with each other, and does not have an etching stop film between the interlayer insulating film 110 and the interlayer insulating film 120. The etching stopper film is an insulating film composed of Si, C, and N elements, and examples thereof include a SiN film, a SiC film, and a SiCN film.

  Contacts 111 (111 a and 111 b) are embedded in the interlayer insulating film 110. The Cu wiring 141 is formed on the contact 111 (111a and 111b). Therefore, the bottom of the Cu wiring 141 is formed in the interlayer insulating film 110. The contact 111a electrically connects the gate electrode 106 and the Cu wiring 141 formed thereabove, and the contact 111b electrically connects the source / drain region 104 and the Cu wiring 141 formed thereabove. is doing.

  The Cu wiring 141 has a shape whose width becomes narrower downward, and the inclination of the side surface of the Cu wiring 141 in the interlayer insulating film 110 is larger than the inclination of the side surface of the Cu wiring 141 in the interlayer insulating film 120. ing. In other words, at least the bottom portion has a taper whose width becomes narrower downward, and the taper in the interlayer insulating film 110 is larger than the taper in the interlayer insulating film 120. That is, the Cu wiring 141 is inclined in a direction in which the interval between adjacent Cu wirings 141 is increased at least in a portion located in the interlayer insulating film 110. In the present embodiment, the side surface of the Cu wiring 141 in the interlayer insulating film 110 is inclined inward from the boundary between the interlayer insulating film 110 and the interlayer insulating film 120. Thereby, the space | interval of Cu wiring 141 in the interlayer insulation film 110 is expanded.

  The diffusion prevention film 160 prevents Cu in the Cu wiring 141 from diffusing. As the diffusion preventing film 160, SiN, SiCN, SiC, a laminated film of SiCN and SiC, or the like can be used.

  Next, an example of a method for manufacturing the semiconductor device 10 will be described with reference to FIGS. 2 and 3 are cross-sectional views illustrating an example of a manufacturing process of the semiconductor device 10 according to the first embodiment.

  First, as shown in FIG. 2A, a transistor including an element isolation region 101, a well 102, a gate oxide film 105, a source / drain region 104 and a gate electrode 106 is formed on a semiconductor substrate 100. Further, sidewalls 107 are formed on both side surfaces of the gate electrode 106 by dry etching.

  Subsequently, as illustrated in FIG. 2B, an interlayer insulating film 110 is formed on the semiconductor substrate 100. Thereby, an interlayer insulating film 110 is formed on the gate electrode 106.

  Next, an opening reaching the gate electrode 106 and the source / drain region 104 is formed in the interlayer insulating film 110, and a conductor is embedded in the opening. In general, the conductor is embedded by depositing a barrier metal film (not shown) by sputtering and then plating the conductor by electrolytic plating using the barrier metal film as a seed film. As a result, a contact 111 is formed in the interlayer insulating film 110. As shown in FIG. 2C, the contact 111 a is connected to the gate electrode 106, and the contact 111 b is connected to the source / drain region 104.

  Next, as illustrated in FIG. 3A, an interlayer insulating film 120 having a dielectric constant lower than that of the interlayer insulating film 110 is formed on the interlayer insulating film 110 and the contact 111.

  Subsequently, a photoresist film 150 is formed on the interlayer insulating film 120, and dry etching is performed using the photoresist film 150 as a mask.

  Since the interlayer insulating film 110 has a higher dielectric constant than the interlayer insulating film 120, the interlayer insulating film 110 has a higher density and is less likely to be etched than the interlayer insulating film 120. That is, when etching is performed under the same etching conditions, the interlayer insulating film 110 has a higher density than the interlayer insulating film 120, and thus the interlayer insulating film 110 has a lower etching rate than the interlayer insulating film 120. By etching using this property, the interlayer insulating film 110 can be etched under the etching conditions of the interlayer insulating film 120 to form a large slope in the etching groove. That is, since the interlayer insulating film 110 has a lower etching rate than the interlayer insulating film 120, when etching is performed under the same etching conditions, the gradient of the side surface of the interlayer insulating film 110 is closer to the side surface of the interlayer insulating film 120. Greater than the slope.

  By such etching, it has a shape that becomes narrower in the downward direction as shown in FIG. 3B, and the interlayer insulating film 110 is more inclined than the inclination of the side surface of the wiring trench 140 in the interlayer insulating film 120. A wiring groove 140 having a large inclination of the side surface of the wiring groove 140 is formed. Note that the depth of the wiring trench 140 may not be uniform with each other.

  Further, the upper surface of the contact 111 is exposed at the bottom of the wiring groove 140 by etching. Thereby, the connection between the Cu wiring 141 formed thereafter and the contact 111 can be ensured.

  Next, a barrier metal film 144 is formed on the entire surface of the interlayer insulating film 120 by using, for example, a sputtering method and an electroplating method. Next, a Cu wiring material is formed by an electrolytic plating method using the barrier metal film 144 as a seed film. By forming a film, a Cu wiring material is embedded in the wiring groove 140. Subsequently, excess Cu on the interlayer insulating film 120 is removed by, for example, a CMP method to form a Cu wiring 141 as shown in FIG. Thus, the Cu wiring 141 has a shape whose width becomes narrower downward, and the inclination of the side surface of the Cu wiring 141 in the interlayer insulating film 110 is larger than the inclination of the side surface of the Cu wiring 141 in the interlayer insulating film 120. Is formed. In other words, at least the bottom has a taper that becomes narrower in the downward direction, and the Cu wiring 141 in the interlayer insulating film 110 is larger than the taper in the interlayer insulating film 120.

  Thereafter, a diffusion prevention film 160 is formed on the Cu wiring 141 and the interlayer insulating film 120 (FIG. 1). Thus, the semiconductor device 10 is obtained.

  Next, effects of the semiconductor device 10 according to the present embodiment will be described. 12A to 12D are cross-sectional views showing a semiconductor device as a comparative example and are based on the inventors' consideration.

  12A and 12B, an etching stopper film 310 is formed on the semiconductor device 30. In addition, there is a corner at the bottom of the wiring 341. Other configurations are the same as those of the semiconductor device 10.

  Here, since the etching stopper film 310 is an insulating film usually composed of Si, C, and N elements, the dielectric constant is higher than that of the interlayer insulating film. For this reason, there is a possibility that the capacitance between the wirings of the semiconductor device increases.

  12C and 12D, the etching stopper film 310 is not formed on the semiconductor device 31. In addition, there is a corner at the bottom of the wiring 341. Other configurations are the same as those of the semiconductor device 10.

  In the semiconductor device 31, since the etching stopper film 310 is not formed, an increase in the dielectric constant due to the etching stopper film 310 can be prevented, but since the etching stopper film 310 is not present, the depth of the groove is controlled when the wiring groove is formed. In some cases, the wiring trench penetrates the interlayer insulating film 120 and reaches the interlayer insulating film 110. At this time, since the dielectric constant of the interlayer insulating film 110 is higher than the dielectric constant of the interlayer insulating film 120 and the distance between the wirings 341 in the interlayer insulating film 110 is short, the wiring is formed in the interlayer insulating film 110. As a result, the capacitance between the wires tends to increase.

  That is, in any of the semiconductor devices shown in FIGS. 12A to 12D, an increase in capacitance between wirings cannot be suppressed.

  On the other hand, in the present invention, the interlayer insulating film 110, the interlayer insulating film 120 having a lower dielectric constant than the interlayer insulating film 110, and the Cu penetrating through the interlayer insulating film 120 and entering the interlayer insulating film 110 at the bottom. Wiring 141. The Cu wiring 141 has a shape whose width becomes narrower downward, and the inclination of the side surface of the Cu wiring 141 in the interlayer insulating film 110 is larger than the inclination of the side surface of the Cu wiring 141 in the interlayer insulating film 120. . In other words, the Cu wiring 141 has a taper whose width becomes narrower downward at least at the bottom, and the taper in the interlayer insulating film 110 is larger than the taper in the interlayer insulating film 120.

  That is, the side surface of the Cu wiring 141 in the interlayer insulating film 110 is inclined in a direction that widens the interval between adjacent Cu wirings 141 at least in a portion located in the interlayer insulating film 110. Thereby, even if the Cu wiring 141 reaches the interlayer insulating film 110, the spacing between the Cu wirings 141 in the interlayer insulating film 110 becomes wider than the spacing between the Cu wirings 141 in the interlayer insulating film 120. Therefore, even when the Cu wiring 141 reaches the interlayer insulating film 110, it is possible to suppress an increase in capacitance between the wirings.

  Furthermore, it demonstrates that the semiconductor device 10 has another effect using FIGS. This structure has the following effects in the single damascene method in which the via hole and the Cu wiring 141 are separately formed. Below, the effect by the via first method which forms a via hole ahead of Cu wiring 141 is explained.

  FIG. 5A is a partially enlarged sectional view cut along a plane including the central axis of the contact 111 of the semiconductor device 10 according to the present invention, and FIG. 5B is a perspective plan view seen from above. FIG. 5A is a cross-sectional view taken along the line A-A ′ in FIG. FIG. 5C is an enlarged cross-sectional view taken along the line A-A ′ of FIG. 5B after the wiring groove 140 is formed and the barrier metal film 144 is formed by sputtering. 6A is a partially enlarged cross-sectional view of the semiconductor device 10 according to the present invention, and FIG. 6B is a perspective plan view seen from above. FIG. 6A is a cross-sectional view taken along the line A-A ′ in FIG. FIG. 6C is an enlarged cross-sectional view taken along the line A-A ′ of FIG. 6B after the wiring groove 140 is formed and the barrier metal film 144 is formed by sputtering. FIG. 7A is a partially enlarged sectional view of a semiconductor device as a comparative example, and FIG. 7B is a perspective plan view seen from above. FIG. 7A is a cross-sectional view taken along the line A-A ′ in FIG. FIG. 7C is an enlarged cross-sectional view taken along the line A-A ′ of FIG. 7B after the wiring groove 340 is formed and the barrier metal film 344 is formed by sputtering.

  As shown in FIG. 7C, in the semiconductor device of the comparative example, the lower portion of the wiring groove 340 has a corner. For this reason, when, for example, a wiring material is embedded in the wiring groove 340, it is difficult to sufficiently distribute the wiring material to the lower corner of the wiring groove 340. Therefore, as shown in FIG. 7A, the void 22 may be formed between the wiring 341 formed in the wiring groove 340.

  On the other hand, as shown in FIGS. 5C and 6C, in the semiconductor device 10, the wiring groove 140 has a shape that becomes narrower in the downward direction, and the side surface of the interlayer insulating film 120 has The inclination of the side surface in the interlayer insulating film 110 is larger than the inclination. That is, the wiring trench 140 has a taper whose width becomes narrower at least at the bottom in the interlayer insulating film 110. For this reason, the slope formed on the lower side surface of the wiring groove 140 makes it easy to embed the wiring material between the wiring groove 140 and the contact 111. This makes it difficult for voids to be formed between the Cu wiring 141 and the contact 111.

  Further, as shown in FIG. 6, even when the contact 111 is not formed immediately below the Cu wiring 141 and misalignment of the photoresist mask or the like occurs, the position of the Cu wiring 141 and the contact 111 is shifted. The effect that it is easy to embed a wiring material in the bottom of the wiring groove 140 is obtained. Since the bottom of the wiring groove 140 has a taper whose width becomes narrower downward, the wiring material is easily embedded, and voids are hardly formed between the Cu wiring 141 and the contact 111. On the other hand, in the wiring groove 340 shown in FIG. 7 (wiring groove for forming the wiring 341), when the contact 111 is shifted to the right from the middle of FIG. Moreover, it becomes more difficult to embed wiring materials.

(Second Embodiment)
FIG. 4 is a cross-sectional view showing a semiconductor device according to the second embodiment.

  As shown in FIG. 4, the semiconductor device 20 further includes an adhesive film 115 between the interlayer insulating film 110 and the interlayer insulating film 120 that improves the adhesiveness between the interlayer insulating film 110 and the interlayer insulating film 120. Other configurations are the same as those of the semiconductor device 10.

  The adhesive film 115 is a film that improves the adhesiveness between the interlayer insulating film 110 and the interlayer insulating film 120. As for the adhesive film 115 and the interlayer insulating film 120, the adhesive film 115 is first formed in the same process, and then the interlayer insulating film 120 is formed. The adhesion between the adhesive film 115 and the interlayer insulating film 120 is ensured by being continuously formed in the same process, and the film quality of the interlayer insulating film 110 can be made closer by reducing C of the adhesive film 115. Is possible. As a result, the adhesion between the adhesive film 115 and the interlayer insulating film 110 can also be improved. The adhesive film 115 is made of Si, C, O, and H, and is a film having less C than the interlayer insulating film 120.

  In the method of manufacturing the semiconductor device 20, the contact 111 is formed on the interlayer insulating film 110 after the interlayer insulating film 110 is formed, as in the semiconductor device 10. Next, the adhesive film 115 and the interlayer insulating film 120 are successively formed on the interlayer insulating film 110 and the contacts 111. For example, the adhesive film 115 and the interlayer insulating film 120 can be continuously formed in the same process by switching the film forming conditions in the middle of one CVD apparatus. Thereafter, similarly to the semiconductor device 10, the semiconductor device 20 can be manufactured by forming the Cu wiring 141 penetrating the interlayer insulating film 120 and the adhesive film 115 and having the bottom portion entering the interlayer insulating film 110.

In this embodiment, an adhesive film 115 is formed between the interlayer insulating film 110 and the interlayer insulating film 120. Thereby, the adhesion between the interlayer insulating film 110 and the interlayer insulating film 120 can be increased.
Other effects of this embodiment are the same as those of the above embodiment.

  The semiconductor device and the manufacturing method thereof according to the present invention are not limited to the above-described embodiments, and various modifications can be made.

  As shown in FIG. 8, an interlayer insulating film 110, an interlayer insulating film 120, and an interlayer insulating film 130 are formed in order, a Cu wiring 141 penetrates the interlayer insulating film 130 and the interlayer insulating film 120, and the bottom is an interlayer insulating film. 110 may be included.

The interlayer insulating film 130 is, for example, a film containing SiO ₂ or Si, C, O, and H. However, even if the interlayer insulating film 130 and the interlayer insulating film 120 have the same component element, the component ratios of the component elements are different.

  In the present embodiment, the single-layer Cu wiring 141 is illustrated, but a plurality of Cu wiring layers may be provided. In that case, via plugs and other Cu wirings may be alternately stacked on the Cu wiring 141. For example, as shown in FIG. 9, an interlayer insulating film 120, a diffusion preventing film 160, and an interlayer insulating film 130 are laminated in this order, and a Cu wiring 142 (a first wiring) is formed on the interlayer insulating film 130 on the Cu wiring 141 (first wiring). A second wiring) may be formed.

  Further, in plan view, the width of the contact 111 and the width of the Cu wiring 141 (or the wiring groove 140) may be the same, or the Cu wiring 141 may be larger than the width of the contact 111. Further, the contact 111 may be larger than the width of the Cu wiring 141. Even in this case, since the bottom of the wiring groove 140 has a taper that becomes narrower downward, an increase in capacitance can be suppressed while facilitating embedding of the wiring material.

  In the above embodiment, the example in which the contact 111 is connected under the Cu wiring 141 has been described. However, the contact 111 may not be connected under the Cu wiring 141.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 20 Semiconductor device 30 Semiconductor device 31 Semiconductor device 100 Semiconductor substrate 101 Element isolation region 102 Well 104 Source / drain region 105 Gate oxide film 106 Gate electrode 107 Side wall 110 Interlayer insulating film 111 Contact 111a Contact 111b Contact 115 Adhesive film 120 Interlayer Insulating Film 130 Interlayer Insulating Film 140 Wiring Groove 141 Cu Wiring 142 Cu Wiring 144 Barrier Metal Film 150 Photoresist Film 160 Diffusion Prevention Film 310 Etching Stopper Film 340 Wiring Groove 341 Wiring 344 Barrier Metal Film

Claims (12)

A semiconductor substrate and a first interlayer insulating film formed on the semiconductor substrate;
A second interlayer insulating film formed on the first interlayer insulating film and having a dielectric constant lower than that of the first interlayer insulating film;
A wiring penetrating through the second interlayer insulating film and having a bottom portion entering the first interlayer insulating film;
With
The wiring has a shape whose width is narrowed downward at least at the bottom, and the wiring in the first interlayer insulating film is more inclined than the inclination of the side surface of the wiring in the second interlayer insulating film. A semiconductor device characterized in that the side surface has a large inclination. The semiconductor device according to claim 1,
An adhesive film for improving adhesion between the first interlayer insulating film and the second interlayer insulating film is provided between the first interlayer insulating film and the second interlayer insulating film. Semiconductor device. The semiconductor device according to claim 2,
The first interlayer insulating film is a SiO ₂ film,
The second interlayer insulating film is a film containing Si, C, O and H,
2. The semiconductor device according to claim 1, wherein the adhesive film includes Si, C, O, and H, and the C is less than C in the second interlayer insulating film. The semiconductor device according to claim 1,
In the semiconductor device, the first interlayer insulating film and the second interlayer insulating film are in direct contact with each other. The semiconductor device according to claim 1,
The semiconductor device includes a transistor including a gate electrode formed on the semiconductor substrate,
The first interlayer insulating film is formed on the gate electrode;
A semiconductor device comprising a contact embedded in the first interlayer insulating film and connecting the gate electrode and the wiring. The semiconductor device according to claim 1,
The semiconductor device has a single damascene structure. The semiconductor device according to claim 1,
The semiconductor device, wherein the wiring is formed on the contact. Forming a first interlayer insulating film on the semiconductor substrate;
Forming a second interlayer insulating film having a dielectric constant lower than that of the first interlayer insulating film on the first interlayer insulating film;
Forming a wiring groove penetrating through the second interlayer insulating film and having a bottom portion entering the first interlayer insulating film;
Burying a wiring material in the wiring groove to form a wiring; and
Including
In the step of forming the wiring groove,
The wiring trench is formed such that at least a bottom portion becomes narrower toward the semiconductor substrate, and the slope in the side surface of the wiring trench in the second interlayer insulating film is more than the slope in the first interlayer insulating film. A method of manufacturing a semiconductor device, wherein a side surface of a wiring groove has a large inclination. In the manufacturing method of the semiconductor device according to claim 8,
Forming a transistor including a gate electrode on the semiconductor substrate before the step of forming the first interlayer insulating film,
Forming a contact connected to the gate electrode in the first interlayer insulating film between the step of forming the first interlayer insulating film and the step of forming the second interlayer film; Including
In the step of forming the first interlayer insulating film,
Forming the first interlayer insulating film on the gate electrode;
In the step of forming the wiring groove,
Exposing the upper surface of the contact at the bottom of the wiring trench;
In the step of forming the wiring,
A method of manufacturing a semiconductor device, wherein the contact and the wiring are connected. In the manufacturing method of the semiconductor device according to claim 8 or 9,
Between the step of forming the first interlayer insulating film and the step of forming the second interlayer insulating film, the first interlayer insulating film and the second interlayer are formed on the first interlayer insulating film. And a step of forming an adhesive film for improving the adhesiveness with the interlayer insulating film. In the manufacturing method of the semiconductor device according to claim 10,
A method of manufacturing a semiconductor device, wherein the step of forming the adhesive film and the step of forming the second interlayer insulating film are continuously performed. In the manufacturing method of the semiconductor device according to claim 10 or 11,
The first interlayer insulating film is a SiO ₂ film,
The second interlayer insulating film is a film containing Si, C, O and H,
The method for manufacturing a semiconductor device, wherein the adhesive film contains Si, C, O, and H, and the C is less than C of the second interlayer insulating film.

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