JP4243099B2 - Method for forming metal wiring of semiconductor element - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a metal wiring of a semiconductor device by a dual damascene process.
[0002]
[Prior art]
As the degree of integration of semiconductor elements increases, a metal wiring layer having a multilayer wiring structure is required, and the interval between the metal wirings in the semiconductor element gradually decreases. As a result, the influence of the parasitic resistance R and the capacitance C component existing between the metal wiring layers adjacent to each other on the same layer or between the wiring layers adjacent to each other up and down has become the most important problem.
[0003]
Parasitic resistance and capacitance components in metal wiring systems degrade the electrical performance of the device due to RC induced delays. Further, parasitic resistance and capacitance components existing between the wiring layers increase the total power consumption of the chip and increase the amount of signal leakage.
[0004]
Therefore, it is a very important problem to develop a multilayer wiring technique with a small RC in the ultra-highly integrated semiconductor device.
[0005]
In order to form a high-performance multilayer wiring structure having a small RC, it is necessary to form a wiring layer using a metal having a low specific resistance or to use an insulating film having a low dielectric constant.
[0006]
In order to reduce the resistance in the metal wiring layer, researches using a metal having a low specific resistance, for example, copper, as a metal material for forming the metal wiring layer are being actively conducted.
[0007]
It is difficult to obtain a copper wiring by direct patterning using a photo etching technique. Therefore, the dual damascene process is mainly used to form the copper wiring.
[0008]
1 to 5 are cross-sectional views illustrating a conventional method for forming a metal wiring of a semiconductor device according to a process sequence.
[0009]
Referring to FIG. 1, a stopper film 104 is formed on a semiconductor substrate 100 on which a predetermined conductive layer 102 is formed.
[0010]
Subsequently, an interlayer insulating film 106 is formed on the stopper film 104.
[0011]
Next, a first photoresist pattern 108 having a first width W1 and having a first opening H1 exposing a part of the upper surface of the interlayer insulating film 106 is formed on the interlayer insulating film 106. That is, after applying a photoresist on the interlayer insulating film 106, the photoresist is exposed and developed to form a first photoresist pattern 108.
[0012]
Referring to FIG. 2, the interlayer insulating film 106 is etched using the first photoresist pattern 108 as an etching mask. The etching is performed until the stopper film 104 is exposed. By the etching, a via hole 110 having a first width W1 is formed in the interlayer insulating film 106a.
[0013]
Next, the first photoresist pattern 108 is removed. The first photoresist pattern 108 can be removed using an ordinary method, for example, an ashing process.
[0014]
Referring to FIG. 3, a second opening H2 having a second width W2 larger than the first width W1 and partially exposing the interlayer insulating film 106a is provided on the interlayer insulating film 106a in which the via hole 110 is formed. A second photoresist pattern 112 is formed. The position of the second opening H2 is formed so as to correspond to the position of the via hole 110.
[0015]
Referring to FIG. 4, the interlayer insulating layer 106a is dry-etched using the second photoresist pattern 112 as an etching mask. By the etching, a wiring region 114 having a second width W2 is formed in the interlayer insulating film 106b, and a first width W1 for connecting the conductive layer 102 and the wiring region 114 is formed below the wiring region 114. A via hole 110a having the structure is formed. However, the stopper film 104 exposed through the via hole (110; see FIG. 3) during the etching may also be etched to expose the conductive layer 102 to the outside. The interlayer insulating film 106b uses a material having a high etching selectivity with respect to the stopper film 104a. However, the stopper film 104 exposed through the via hole (110; see FIG. 3) is also etched at a predetermined speed when the interlayer insulating film 106a is etched. . Therefore, after the etching of the interlayer insulating film 106b is completed, the exposed stopper film 104 may be completely etched and the conductive layer 102 may be exposed to the etching atmosphere. When the conductive layer 102, for example, a copper wiring layer, is exposed to an etching atmosphere, a hard polymer (not shown) is formed along the side wall. However, the hard polymer has a disadvantage that it is not easy to remove. Such development becomes more serious as the depth of the interlayer insulating film 106a to be etched is deeper, the thickness of the stopper film 104a is thinner, and the etching selectivity of the stopper film 104a to the interlayer insulating film 106b is smaller. is there.
[0016]
Referring to FIG. 5, the second photoresist pattern 112 is removed using an ashing process. The ashing process uses oxygen-based plasma. Accordingly, the conductive layer 102 exposed during the second photoresist pattern 112 removal process, that is, the ashing process, is combined with oxygen to form the metal oxide layer 116. When the metal oxide layer 116 is formed, the electric resistance rapidly increases, and even if a conductive material is embedded in the wiring region 114 and the via hole 110a, the metal wiring (not shown), the conductive layer 102, May be lifted up without being electrically connected, that is, a lifting phenomenon may occur. Further, since the ashing process using oxygen-based plasma is performed after the wiring region 114 and the via hole 110a are formed, the surface of the interlayer insulating film 106b is damaged by the ashing process. That is, the ashing process causes H ₂ O, OH, CO ₂ , H ₂ Are induced and fixed to the surface of the interlayer insulating film 106b, and this acts as a factor for rapidly increasing the dielectric constant of the interlayer insulating film 106b.
[0017]
6 to 9 are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device according to another conventional example in the order of steps.
[0018]
Referring to FIG. 6, a stopper film 204 is formed on a semiconductor substrate 200 on which a predetermined conductive layer 202 is formed.
[0019]
Subsequently, an interlayer insulating film 206 is formed on the stopper film 204.
[0020]
Next, a first photoresist pattern 208 having a first width W1 having a first width H1 and exposing a part of the upper surface of the interlayer insulating film 206 is formed on the interlayer insulating film 206. That is, after applying a photoresist on the interlayer insulating film 206, the photoresist is exposed and developed to form a first photoresist pattern 208.
[0021]
Referring to FIG. 7, a portion of the interlayer insulating film 206 is etched using the first photoresist pattern 208 as an etching mask. In the etching, only a part of the interlayer insulating film 206 is etched, and the interlayer insulating film 206 having a predetermined thickness is left without being etched. The partial via hole 210 having the first width W1 is formed in the interlayer insulating film 206a by the etching.
[0022]
Next, the first photoresist pattern 208 is removed. The first photoresist pattern 108 can be removed using an ordinary method, for example, an ashing process.
[0023]
Referring to FIG. 8A, a second opening H2 having a second width W2 larger than the first width W1 and partially exposing the interlayer insulating film 206a is formed on the interlayer insulating film 206a in which the partial via hole 210 is formed. The provided second photoresist pattern 212 is formed. The position of the second opening H2 is formed so as to correspond to the position of the partial via hole 210. However, when the second photoresist pattern 212 is formed on the interlayer insulating film 206a, the photoresist 212 may remain at the bottom of the partial via hole 210 in some cases. The photoresist 212 remaining at the bottom of the partial via hole 212 may serve as a barrier for the subsequent etching of the interlayer insulating film 206a to form a via hole that is not opened when the remaining interlayer insulating film 206a is etched. A detailed description thereof will be described later.
[0024]
On the other hand, FIG. 8B illustrates an example of a second photoresist pattern that is misaligned. Although not shown in the drawing, as described with reference to FIG. 8A, the photoresist may remain on the bottom of the partial via hole 210 in this case as well.
[0025]
Referring to FIG. 9A, the interlayer insulating layer 206a is dry-etched using the second photoresist pattern 212 as an etching mask. By the etching, a wiring region 214 having a second width W2 is formed in the interlayer insulating film 206b, and a first width W1 for connecting the conductive layer 202 and the wiring region 214 is formed below the wiring region 214. A via hole 210a is formed. However, the photoresist 212 remaining at the bottom of the partial via hole (210; see FIG. 8A) during the etching acts as a barrier to the etching. Therefore, the interlayer insulating film 206b existing below the partial via hole (210; see FIG. 8A) is not etched any more, resulting in an unopened via hole 210a.
[0026]
On the other hand, FIG. 9B shows that when the misaligned second photoresist pattern 212 is formed, the interlayer insulating film 206a is etched using the misaligned second photoresist pattern 212 as an etching mask to form the wiring region 214 and the via hole 210a. This state is illustrated. As shown in FIG. 9B, when misalignment occurs, the width of the via hole 210a is narrower than the first width W1, and the profile of the via hole 210a becomes defective. Further, as described with reference to FIG. 9A, a via hole (not shown) that is not opened may be formed when photoresist remains at the bottom of the partial via hole (210; see FIG. 8B).
[0027]
FIG. 10A shows an example of a metal wiring layer having an unopened via hole. Referring to FIGS. 9A and 10A, the second photoresist pattern 212 is removed using an ashing process. The photoresist 212 remaining in the via hole (210a; see FIG. 9A) during the ashing process is also removed. However, as described above, the via hole 210a that is not opened is formed and the wiring region 214 and the conductive layer 202 are not connected. Further, since the ashing process using oxygen-based plasma is performed after the wiring region 214 and the via hole 210a are formed, the surface of the interlayer insulating film 206b is damaged by the ashing process. That is, the ashing process causes H ₂ O, OH, CO ₂ , H ₂ Are induced and fixed to the surface of the interlayer insulating film 206b, which acts as a factor for rapidly increasing the dielectric constant of the interlayer insulating film 206b.
[0028]
On the other hand, FIG. 10B illustrates a state after the second photoresist pattern 212 is removed when a misalignment of the second photoresist pattern 212 occurs. As shown in FIG. 10B, the via hole 210a having a width smaller than the first width W1 is formed, resulting in a poor profile of the via hole 210a. As described above, when photoresist remains at the bottom of the partial via hole (210; see FIG. 8B), a via hole (not shown) that is not opened is formed, and the wiring region 214 and the conductive layer 202 are formed. It may not be connected.
[0029]
[Problems to be solved by the invention]
The present invention is intended to solve the above-described problems in the prior art, and the technical problem to be achieved by the present invention is that the stopper film is etched when the wiring layer and the via hole are formed by etching the interlayer insulating film. By exposing the conductive layer to the outside, it is possible to prevent a problem that a metal oxide layer is formed on the conductive layer in the second photoresist pattern removing process, and to prevent damage due to the ashing process. It is possible to solve the problem that the photoresist remains in the partial via hole when the pattern is formed and the via hole is not opened, and it is possible to prevent the profile defect of the via hole from occurring even if the second photoresist pattern is misaligned. A method for forming a metal wiring of a semiconductor device is provided.
[0030]
[Means for Solving the Problems]
A method for forming a metal wiring of a semiconductor device according to the first and second embodiments for achieving the technical problem includes a step of forming a stopper film on a conductive layer formed on a semiconductor substrate, and a method of forming a stopper film on the stopper film. A step of forming an interlayer insulating film; a step of forming a hard mask layer on the interlayer insulating film; and a first photoresist pattern having a first width defining a via hole corresponding to the conductive layer on the hard mask layer Forming a via hole that exposes the surface of the stopper film formed on the conductive layer by etching the hard mask layer and the interlayer insulating film using the first photoresist pattern as an etching mask. Removing the first photoresist pattern; filling the via hole with a mediator; and Forming a second photoresist pattern having a second width greater than the first width on the embedded semiconductor substrate; and etching a portion of the hard mask layer using the second photoresist pattern as an etching mask. Forming a pattern defining a wiring region overlapping at least a part of the via hole, removing the mediator from the second photoresist pattern and the via hole, and using the hard mask pattern as an etching mask Etching a part of the interlayer insulating film to form a wiring region; removing the stopper layer remaining in the via hole; and embedding a conductive material in the via hole and the wiring region. And execute the steps in the order listed .
[0031]
The interlayer insulating film is formed by laminating a first interlayer insulating film, a second stopper film, and a second interlayer insulating film on the stopper film. At this time, in the step of forming the wiring region, the second insulating film The second interlayer insulating film may be etched by using the stopper film as an etching stopper layer.
[0032]
The hard mask layer is made of at least one of a silicon oxide film, a silicon nitride film, a silicon carbide film, polysilicon, a metal oxide, a metal nitride, or a metal having a high etching selectivity with respect to the interlayer insulating film. Preferably, the mediator layer is the interlayer insulating film. , It is made of a carbon-based organic BARC film or SOG film having an etching selectivity, and the SOG film is an inorganic HSQ film, MSQ film or porous SiO having an etching selectivity. ₂ Can be a membrane.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the following examples are provided so that those skilled in the art can fully understand the present invention, and can be modified in various other forms. Is not limited to the examples described below. In the following description, when a layer is described as being on top of another layer, it may be directly on top of the other layer, with a third layer interposed therebetween. In the drawings, the thickness and size of each layer are exaggerated for convenience of explanation and clarity. The same reference numerals refer to the same elements in the drawings.
[0034]
<First embodiment>
11 to 17 are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.
[0035]
Referring to FIG. 11, a stopper film 704 is formed on a semiconductor substrate 700 on which a predetermined conductive layer 702 is formed. The conductive layer 702 may be an impurity doping region, a Cu wiring layer, or other metal wiring layer formed in the semiconductor substrate 700. The stopper film 704 is a material having a high etching selectivity with respect to the interlayer insulating film 706 formed thereon, for example, Si. _Three N _Four Or it is desirable to consist of SiC.
[0036]
Next, an interlayer insulating film 706 is formed over the stopper film 704. The interlayer insulating film 706 is, for example, a SiOC film or porous SiO. ₂ Membrane, PSG (phosphorous silicate glass) membrane, BPSG (boron phosphorous silicate glass) membrane, USG (undoped silicate glass) membrane, FSG (fluorinated doped silicate m s, PE layer, hde PE sigmite, DP h membrane, DP h membrane PE layer It is desirable to use a material film having a low dielectric constant such as a -tetraethyl silicate (SOE) film or a SOG (spin on glass) film. The interlayer insulating film 706 is made of a material film having a high etching selectivity with respect to the stopper film 704.
[0037]
Next, a hard mask layer 708 is formed over the interlayer insulating film 706. The hard mask layer 708 is a material having a high etching selectivity with respect to the interlayer insulating film 706, for example, a silicon nitride film, a silicon oxide film, a silicon carbide film, a metal oxide such as polysilicon or aluminum oxide, or a metal nitride such as TiN. It is desirable to be made of a metal such as aluminum or titanium.
[0038]
Next, a first photoresist having a first opening H1 exposing a part of the upper surface of the hard mask layer 708 defining a via hole (described later) having a first width W1 and corresponding to the conductive layer 702 on the hard mask layer 708. A pattern 710 is formed. That is, after applying a photoresist on the hard mask layer 708, the photoresist is exposed and developed to form a first photoresist pattern 710.
[0039]
Referring to FIG. 12, the hard mask layer 708 and the interlayer insulating layer 706 are etched using the first photoresist pattern 710 as an etching mask to form a via hole 712 exposing the stopper layer 704.
[0040]
Next, the first photoresist pattern 710 is removed. The first photoresist pattern 710 may be removed using a normal method, for example, an ashing process.
[0041]
Referring to FIG. 13, a mediator material layer 714 is applied on the semiconductor substrate 700 in which the via hole 712 is formed to fill the via hole 712. The mediator material layer 714 may be formed only in the via hole 712, or may be formed thin on the hard mask layer 708a by a predetermined height. The intermediary material layer 714 may be formed of a carbon-based organic anti-reflection coating (BARC) film as an organic material film. The BARC film can be formed by a spin coating method. At this time, it is desirable that the rotation speed of the spin coater is about 1000 to 5000 rpm. After the organic material film is applied by the spin coating method, baking is performed at a temperature of about 100 ° C. to 150 ° C.
[0042]
Meanwhile, the mediator layer 714 may be an SOG film. The SOG film may be, for example, an inorganic HSQ (hydrosilsesquioxane) film, MSQ film, or porous SiO ₂ A membrane is desirable.
[0043]
Referring to FIG. 14, a second opening H2 having a second width W2 larger than the first width W1 and partially exposing the mediator material layer 714 on the semiconductor substrate 700 on which the mediator material layer 714 is formed. A second photoresist pattern 716 is formed. The position of the second opening H2 is formed so as to correspond to the position of the via hole 712, and the second opening H2 is positioned above the via hole 712 so as to overlap with at least a part of the via hole 712.
[0044]
Referring to FIG. 15, the intermediate material layer 714 and the hard mask layer 708a over the interlayer insulating layer 706 are dry-etched using the second photoresist pattern 716 as an etching mask. If the mediator layer 714 is an organic material BARC film, the etching may be ₂ Containing N or N ₂ And H ₂ A gas containing is used as an etching gas. Or C _x F _y Gas or C _x H _y Fz-based gas, inert gas such as Ar, and CO or O ₂ An etching gas containing a gas may be used. At this time, the intermediate material layer 714 in the via hole 712 is also recessed to some extent during the etching.
[0045]
On the other hand, when the mediator layer 714 is an SOG film, the dry etching is performed using CxFy gas or CxHyFz gas, an inert gas such as Ar, and CO, CO. ₂ Or O ₂ An etching gas containing a gas is used. The dry etching is preferably performed at a pressure of 5 to 50 mTorr and a power of 1000 to 5000 W for 1 to 2 minutes.
[0046]
Referring to FIG. 16, the second photoresist pattern 716 is removed. The second photoresist pattern 716 can be removed using a conventional method, for example, an ashing process. At this time, if the mediator layer 714 is organic, the organic material film is also removed. That is, the mediator material layer 714 made of an organic material film present on the upper portion of the hard mask layer 708a and in the via hole 712 is also removed in the removal process of the second photoresist pattern 716, for example, an ashing process. If the second photoresist pattern 716 and the mediator layer 714 are removed, the hard mask layer 708b having an opening having the second width W2 is exposed.
[0047]
In the case where the mediator layer 714 is an SOG film, the SOG film formed in the upper portion of the hard mask layer 708b and in the via hole 712 is removed by wet etching. It is desirable to use an etching solution, such as an HF solution, that can etch the SOG film with respect to the interlayer insulating film 706 at a high speed and can selectively remove only the SOG film. An SOG film such as HSQ has a very high etching rate with an HF solution, whereas an interlayer insulating film 706, eg, a SiOC film, is hardly etched with an HF solution.
[0048]
Referring to FIG. 17, the interlayer insulating film 706 is dry-etched using the hard mask layer 708b as an etching mask to simultaneously form a wiring region 718 and a via hole 712a. That is, a wiring region 718 having a second width W2 is formed in the interlayer insulating film 706, and a via hole 712a having a first width smaller than the second width W2 is formed below the wiring region 718. On the other hand, since the hard mask layer 708b is used as an etching mask, the hard mask layer 708b must have a sufficient thickness to withstand while the interlayer insulating film 706 is etched.
[0049]
Next, the stopper film 704 exposed through the via hole 712a is removed by etching. At this time, the hard mask layer 708b may also be removed by etching, or the hard mask layer 708b may be left as it is and a subsequent process may be performed.
[0050]
Next, a barrier layer (not shown) and a conductive layer (not shown) are formed along the step on the semiconductor substrate 700 from which the stopper film 704 has been removed, and then planarized to complete the formation of metal wiring having a dual damascene structure. To do.
[0051]
<Second embodiment>
18 to 24 are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in order of processes. Compared to the first embodiment, the second embodiment is the same as the first embodiment except that a first interlayer insulating film 805, a second stopper film 806, and a second interlayer insulating film 807 are used instead of the interlayer insulating film 706 of the first embodiment. .
[0052]
Referring to FIG. 18, a first stopper film 804 is formed on a semiconductor substrate 800 on which a predetermined conductive layer 802 is formed. Next, a first interlayer insulating film 805, a second stopper film 806, and a second interlayer insulating film 807 are sequentially formed on the first stopper film 804.
[0053]
Next, a hard mask layer 808 is formed on the second interlayer insulating film 807. The hard mask layer 808 is a material having a high etching selectivity with respect to the interlayer insulating film 706, for example, a silicon nitride film, a silicon oxide film, a silicon carbide film, a metal oxide such as polysilicon or aluminum oxide, or a metal nitride such as TiN. It is desirable to be made of a metal such as aluminum or titanium.
[0054]
Next, a first photoresist having a first opening H1 exposing a part of the upper surface of the hard mask layer 808 defining a via hole (described later) having a first width W1 and corresponding to the conductive layer 802 on the hard mask layer 808. A pattern 810 is formed.
[0055]
Referring to FIG. 19, the etching conditions of the hard mask layer 808, the second interlayer insulating film 807a, the second stopper film 806, and the first interlayer insulating film 806 are sequentially changed using the first photoresist pattern 810 as an etching mask. A via hole 812 that exposes the stopper layer 804 is formed by etching. Next, the first photoresist pattern 810 is removed.
[0056]
Referring to FIG. 20, the via hole 812 is filled with a mediator material layer 814. The mediator material layer 814 may be formed only in the via hole 812, or may be formed thin on the hard mask layer 808a by a predetermined height. The mediator material layer 814 may be a carbon-based organic anti-reflective coating (BARC) film or an SOG film as an organic material film as in the first embodiment.
[0057]
Referring to FIG. 21, a second opening H2 having a second width W2 larger than the first width W1 and partially exposing the mediator material layer 814 on the semiconductor substrate 800 on which the mediator material layer 814 is formed. A second photoresist pattern 816 is formed. The position of the second opening H2 is formed so as to correspond to the position of the via hole 812, and the second opening H2 is positioned above the via hole 812 so as to overlap with at least part of the via hole 812 to form a dual damascene structure. Let
[0058]
Referring to FIG. 22, the intermediate material layer 814 and the hard mask layer 808b are dry-etched using the second photoresist pattern 816 as an etching mask. At this time, the intermediate material layer 814 in the via hole 812 is also recessed to some extent during the etching.
[0059]
Referring to FIG. 23, the second photoresist pattern 816 is removed. The second photoresist pattern 816 may be removed using a normal method such as an ashing process. Next, the mediator material layer 814 remaining in the via hole 812 is removed as in the first embodiment.
[0060]
Referring to FIG. 24, the wiring region 818 is formed by dry etching the second interlayer insulating film 807b until the second stopper film 806 is exposed using the hard mask layer 808b as an etching mask. Next, the first stopper film 804 exposed through the via hole 812a is removed by etching. At this time, both the hard mask layer 808b may be removed by etching, or the hard mask layer 808b may be left without being removed and the subsequent process may proceed.
[0061]
Next, as in the first embodiment, a barrier layer (not shown) and a conductive layer (not shown) are formed along the step on the semiconductor substrate 800 from which the first stopper film 804 has been removed, and then planarized. Complete metal wiring formation of dual damascene structure.
[0062]
The present invention has been described in detail with reference to the preferred embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention.
[0063]
【The invention's effect】
According to the method for forming a metal wiring of a semiconductor device according to the present invention, a stopper film (or a first stopper film) is formed when a wiring region and a via hole are formed by etching an interlayer insulating film (or a second interlayer insulating film and a first interlayer insulating film). ) Is etched and the conductive layer is not exposed to the outside. Therefore, the conventional problem that the metal oxide layer is formed on the conductive layer in the second photoresist pattern removing process does not occur.
[0064]
In addition, in the present invention, since the partial via hole is embedded with an organic or inorganic material after the partial via hole is formed and before the second photoresist pattern is formed, the photoresist is formed at the bottom of the partial via hole when the second photoresist pattern is formed. The conventional problem that the via hole is not left open does not occur.
[0065]
In addition, according to the present invention, since the partial via hole is filled with an organic material or an inorganic material after the partial via hole is formed and before the second photoresist pattern is formed, a conventional via hole is formed even if misalignment of the second photoresist pattern occurs. No profile failure occurs.
[0066]
Further, in the present invention, after the second photoresist pattern is removed, the hard mask layer is used as an etching mask to form a wiring region and a via hole, so that it is not damaged by the ashing process that appears on the surface of the interlayer insulating film as in the prior art. Further, as in the first and second embodiments of the present invention, a full via hole may be applied using a mediator layer.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a conventional example in order of steps.
FIG. 2 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a conventional example in the order of steps.
FIG. 3 is a cross-sectional view illustrating a conventional method for forming a metal wiring of a semiconductor device according to a process sequence.
FIG. 4 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a conventional example in the order of steps.
FIG. 5 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a conventional example in the order of steps.
FIG. 6 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to another conventional example in the order of steps.
FIG. 7 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to another conventional example in the order of steps.
FIG. 8 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to another conventional example in the order of steps.
FIG. 9 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to another conventional example in the order of steps.
FIG. 10 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to another conventional example in the order of steps.
FIG. 11 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.
FIG. 12 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.
FIG. 13 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.
FIG. 14 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.
FIG. 15 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.
FIG. 16 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.
FIG. 17 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a first preferred embodiment of the present invention in the order of steps.
FIG. 18 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.
FIG. 19 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.
FIG. 20 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.
FIG. 21 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.
FIG. 22 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.
FIG. 23 is a cross-sectional view illustrating a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.
FIG. 24 is a cross-sectional view showing a method of forming a metal wiring of a semiconductor device according to a second preferred embodiment of the present invention in the order of steps.
[Explanation of symbols]
104,204,704 Stopper film
804 First stopper film
806 Second stopper film
106,206,706 Interlayer insulating film
805 First interlayer insulating film
807 Second interlayer insulating film
110,210 Partial beer hall
110a, 210a, 712, 812 Via hole
114, 214, 718, 818 Wiring area

Claims (9)

Forming a stopper film on the conductive layer formed on the semiconductor substrate;
Forming an interlayer insulating film on the stopper film;
Forming a hard mask layer on the interlayer insulating film;
Forming a first photoresist pattern having a first width on the hard mask layer to define a via hole corresponding to the conductive layer;
Etching the hard mask layer and the interlayer insulating film using the first photoresist pattern as an etching mask to form a via hole exposing a surface of a stopper film formed on the conductive layer;
Removing the first photoresist pattern;
Filling the via hole with a mediator;
Forming a second photoresist pattern having a second width greater than the first width on the semiconductor substrate in which the via hole is filled with a medium;
Etching a part of the hard mask layer using the second photoresist pattern as an etching mask to form a pattern defining a wiring region overlapping with at least a part of the via hole;
Removing the mediator from the second photoresist pattern and the via hole;
Etching a part of the interlayer insulating film using the hard mask pattern as an etching mask to form a wiring region;
Removing the stopper layer remaining in the via hole;
Burying a conductive material in the via hole and the wiring region;
Unrealized, the metal wiring formation method of a semiconductor device which is characterized in that performed in the order listed each stage.   2. The metal wiring of a semiconductor device according to claim 1, wherein the interlayer insulating film is a laminate of a first interlayer insulating film, a second stopper film, and a second interlayer insulating film on the stopper film. Forming method.   3. The method of forming a metal wiring of a semiconductor device according to claim 2, wherein the step of forming the wiring region is formed by etching the second interlayer insulating film using the second stopper film as an etching stopper layer.   3. The method as claimed in claim 1, wherein the stopper film and the second stopper film are made of a silicon nitride film or a silicon carbide film having an etching selectivity with respect to the interlayer insulating film. _{3. The} interlayer insulating film is made of an SiOC film, a porous SiO ₂ film, a PSG film, a BPSG film, a USG film, an FSG film, an HDP film, a PE-TEOS film, or an SOG film. The metal wiring formation method of the semiconductor element of description.   The hard mask layer is made of at least one of a silicon oxide film, a silicon nitride film, a silicon carbide film, polysilicon, a metal oxide, a metal nitride, or a metal having a high etching selectivity with the interlayer insulating film. The method for forming a metal wiring of a semiconductor element according to claim 1. 2. The method of claim 1, wherein the intermediate material layer is formed of the interlayer insulating film , a carbon-based organic BARC film having an etching selectivity , or an SOG film. 8. The method according to claim 7, wherein the SOG film is the interlayer insulating film , an inorganic HSQ film having an etching selectivity, an MSQ film, or a porous SiO ₂ film. The mediator substance, a metal wiring formation method of a semiconductor device according to claim 1, characterized in that it is formed by a layer a predetermined height to the via hole to embed Mutotomoni the hard mask layer.

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