JP2003124309A - Method of forming via and trench in copper dual damascene process - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form vias and trenches in a copper (Cu) dual damascene process. SOLUTION: First, a substrate 40 embedded with a copper conductive region 46 is formed and, successively, a dielectric layer 44 in sequence to form vias is deposited. Afterwards, the vias are filled with low dielectric constant materials 60 serving as sacrificial layers in a spin-coating process followed by using a chemical mechanical polishing or etching back to remove the excess low dielectric constant material. Another dielectric layer 80 is deposited and forms trenches 100 which are combined with the vias to complete a dual damascene structure. As the vias and the trenches are etched separately, the depth of focus can be controlled easily and a photoresist pattern can be defined completely so as to form a better etching profile for small dimension integrated circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring forming method for an integrated circuit device, and more particularly to a via and trench manufacturing method in a copper dual damascene process.

[0002]

BACKGROUND OF THE INVENTION One of the goals of integrated circuit (IC) processes is to reduce IC size to increase IC integration and reduce product cost. In addition, the speed performance of the entire IC depends not only on the circuit design using the transistor but also on the via between the metal wiring and the dielectric layer in the device. The main reason that influences the speed performance is the resistance R of the trench and the parasitic capacitance C between the metal wirings. As is well known in the art, lower RC products have smaller delay times. Thus, aluminum-based processes are being replaced by copper-based processes, that is, vias and trenches filled with copper, tend to replace conventional processes for etching aluminum. In the dual damascene process, the formation of vias and trenches can effectively improve the speed performance within the IC. Undoubtedly, technological activities to achieve the goals of the semiconductor industry will be spread all over the world.

Referring to FIGS. 1A and 1B, in a dual damascene structure, a via is first formed before forming a trench. The first dielectric layer 10 is deposited on the IC area (not shown), and the surface of the conductive area is flush with the surface of the first dielectric layer 10 between the conductive areas 15. To be embedded. A first silicon nitride layer (SiN) 11, a second dielectric layer 12, a second silicon nitride layer 13, and a third dielectric layer 14 are sequentially formed using a standard growth process. It Next, the via 16 is formed by stopping the etching on the first silicon nitride layer 11 by the etching process, and further, the second silicon nitride layer 13 as an etching stopper is formed between the vias 16. Etch until exposed to form trenches 17 between vias 16. The drawback of this process is that when forming the via 16, three layers are formed: the second dielectric layer 12, the second silicon nitride layer 1.
Third, the third dielectric layer 14 must be etched directly and continuously. Since the aspect ratio of the opening including the via 16 and the trench 17 is higher, it is difficult to fill the formed opening with a sacrificial film so that the shape of the etched via 16 is not exposed to the outside. In such a configuration, the trench 1
The shape of the via 16 is broken when forming 7.

Referring to FIGS. 2A and 2B, in a dual damascene structure, a trench is first formed before forming a via. This process is the same as in FIGS. 1A and 1B except that the second silicon nitride layer 22 acts as an etching stopper to form the trench 24, and then for the formation of the via 25. Etching is performed to form vias 25 such that the etching is stopped on the first dielectric layer 20. The disadvantage of these processes is that if the selectivity of the photoresist to the dielectric layer during formation of the via 25 is too low, the shape of the formed trench 24 will be destroyed. Further, it is difficult to control the depth of focus of the photoresist pattern for various dielectric layers, which causes misalignment in exposure and development. Therefore, in the conventional technique, the second dielectric layer 2
If a step is formed between the first and third dielectric layers 23, the conductive wiring step cannot be minimized.

As a result, the aspect ratio of the via becomes larger, the etching shape becomes worse, and the phenomenon that the depth of focus cannot be controlled easily occurs because the multilayer dielectric layer is formed before the formation of the via and the trench. .

Referring to FIGS. 3A and 3B, in a dual damascene process, a buried hard mask is used to form vias and trenches. A first dielectric layer 30 is deposited in the area of the IC (not shown) and is embedded in the conductive area 34 such that its surface is flush with the surface of the first dielectric layer 30. A first silicon nitride layer 31, a second dielectric layer 32, and a buried hard mask 33 such as a silicon nitride layer are sequentially formed using a conventional deposition process. In the next step, the buried hard mask 33 is etched to form a via 3 in the buried hard mask 33.
After forming an opening with the same width as the width of the third dielectric layer 3
6 is deposited and the third dielectric layer 36 is patterned such that trenches 37 and vias 35 are formed separately. The disadvantage of this process is that it does not require etching of one dielectric layer as compared to the process of FIGS. 1A and 1B, but the second dielectric layer 32 and the third dielectric layer 36 are not.
However, it must be etched at the same time. The film thickness of the buried hard mask 33 must be sufficiently thick as a protective film.

[0007]

Therefore, the conventional method of forming vias and trenches with the above-described structure is as follows.
It has the following disadvantages: (a) There is a limit to the ability of the sacrificial film to have a buried capacity to protect the vias, as the thicker dielectric layer is subsequently etched;
(B) The surface of the spin-coated photoresist pattern does not have a uniform distribution due to the steps between the dielectric layers;
Further, (c) the depth of focus cannot be controlled in the subsequent exposure and development processes due to the influence of the step formed between the dielectric layers, which is not preferable for forming a minute gap.

[0008]

The main object of the present invention is to:
It is to provide a novel process for forming a dual damascene structure. In a copper (Cu) dual damascene process where the sacrificial film and the photoresist film are removed at the same time, the vias are filled with a low dielectric constant material that acts as a sacrificial film. Further, the via and the trench are sequentially formed by separate etching so as to correspond to the dielectric layer. In addition, the shape of the vias and trenches presents a flat surface so that the depth of focus between the vias and the trenches is controllable, which favorably forms and connects the metal multi-layer connection pattern.

In the preferred embodiment of the present invention, the vias and trenches are formed by the following methods: (1) First, a semiconductor substrate is prepared and a first dielectric layer is deposited;
Embedded in a conductive region having a surface coplanar with the top surface of the first dielectric layer; (2) silicon nitride is deposited over the conductive region and the first dielectric layer;
(3) A second dielectric layer is deposited over the silicon nitride layer using chemical vapor deposition (CVD); (4) a first photoresist pattern used to determine the via shape. Formed over the second dielectric layer; (5) the first photoresist pattern is transferred to the second dielectric layer using an anisotropic etching process, and silicon nitride acts as an etch stopper; (6) A sacrificial film is evenly spin-coated on the second dielectric layer; (7) the extra portion of the sacrificial film is exposed, for example, by chemical mechanical polishing (CMP) or etchback. A planarization process is used to remove the second dielectric layer until it is exposed to form a planar surface; (8) a third dielectric layer as a dielectric layer for etching the trench is CVD method. Deposited on a flat surface by (9) Photoresist pattern is deposited over the third dielectric layer for trench shape determination; (10) a second photoresist pattern is formed on the third dielectric layer using an anisotropic etching process. Transcribed;
Then, (11) the second photoresist pattern on the third dielectric layer and the sacrificial film in the via are simultaneously removed to form a dual damascene structure having the via and the trench.

As a result, according to the present invention, in the dual damascene process, the vias are filled with the low dielectric constant material functioning as a sacrificial film and are removed simultaneously with the photoresist pattern to form the vias and trenches.
It facilitates the formation of a metal connection portion having a multi-layer structure and the connection between the metal connection portions, improves the drawbacks listed in the background of the invention, and enables fine wiring of a device. The foregoing features of the invention and many of the attendant advantages thereof will be further understood by reference to the following detailed description in conjunction with the accompanying drawings, and
It will be understood promptly.

[0011]

DETAILED DESCRIPTION OF THE INVENTION Given the above-described prior art of vias and trenches in a copper dual damascene process, there is always an inherent problem. The present invention provides an effective solution to these problems. In the present invention, a copper dual damascene is formed on a substrate, a low dielectric constant material is used as a sacrificial film for forming vias and trenches,
The sacrificial film is removed at the same time as the photoresist pattern.

Referring to FIG. 4, silicon nitride and a second dielectric layer are separately deposited on a semiconductor substrate containing integrated circuits (not shown). A first dielectric layer 40 is deposited on the semiconductor substrate and buried in the conductive region 46 such that the surface of the conductive region is flush with the first dielectric layer 40. The conductive region 46 is, for example, a gate region,
Source / drain regions or wiring metal, and the material of the conductive region 46 is copper or aluminum.

Still referring to FIG. 4, in a preferred embodiment of the present invention, a silicon nitride 4 having a film thickness of 300 Å (Å) to 1000 Å (Å).
2 is first deposited on the first dielectric layer 40. next,
The second dielectric layer 44 is formed using chemical vapor deposition (CVD). Silicon nitride 42 is used as a barrier layer against copper diffusion. After the second dielectric layer 44 is deposited on the silicon nitride 42, a first photoresist pattern (not shown) is formed on the second nitride layer 44 having a film thickness of 3000 angstroms (Å) to 7000 angstroms (Å). Formed on the dielectric layer 44 to determine the via shape. The second dielectric layer 44 is made of one material selected from the group consisting of silicon oxide (SiO _x ) and fluorosilicate glass. Silicon nitride (Si
N) 42 can also be replaced by silicon carbide as a suitable material for the barrier layer against diffusion of copper.

Referring to FIG. 5, vias are formed in the second dielectric layer using an anisotropic etching process. The first photoresist pattern transferred from the mask is transferred to the second dielectric layer 44 by an anisotropic etching process,
The silicon nitride 42 functions as an etching stopper. Then, the via 50 is formed when the first photoresist pattern is removed. In this step, the silicon nitride 42 is selectively etched or not etched. An advantage of the next etching step is that silicon nitride can protect the conductive regions 46 from damage. The mixed gas used for etching is C ₄ F ₈ , CF ₄ , CHF ₃ , N ₂ , Ar,
It is a mixture of CO.

Referring to FIG. 6, a sacrificial film is spin coated on the via and on the surface of the second dielectric layer. Film thickness 40
A sacrificial film 60 of 00 angstroms (Å) to 8000 angstroms (Å) is uniformly spin-coated to fill the vias 50 on the second dielectric layer 44 and removed simultaneously with the photoresist pattern. In the preferred form of the invention, a low dielectric constant organic material such as FLARE or SiLK is introduced as a sacrificial film to form the vias 50 and trenches. Also, the etching selectivity of the two layers is greater than that of the second dielectric layer 44 or the silicon nitride layer 42. Therefore, the two organic materials are the second dielectric layer 44, the silicon nitride layer 42 and the via 50.
Can function as a protective film for keeping the shape of the shape better. In addition, the two organic materials are 400 ℃
It retains better properties even at temperatures from ~ 450 ° C, so it can withstand high temperature damage during the deposition process, and
Form a uniform spin-coated surface with good flatness.

Referring to FIG. 7, the excess portion of the sacrificial film is removed using a planarization process. The excess portion of sacrificial film 60 is removed using a planarization process such as CMP or etchback until the second dielectric layer 44 is exposed, forming a flat surface 70.

Referring to FIG. 8, a third dielectric layer is deposited on the flat surface. The third dielectric layer 80 having a film thickness of 3000 angstroms (Å) to 7000 angstroms (Å) is formed on the flat surface 70 by using a CVD method in order to form a trench composed of the dielectric layers by etching. Is deposited. The third dielectric layer 80 is Si
O _X, consisting of one material selected FSG, from the group consisting of PSG.

Referring to FIG. 9, the trench is completely defined by the second photoresist pattern. A second photoresist pattern 90 is formed on the third dielectric layer 80 to define the trench shape. The third dielectric layer 80 exhibits a fairly good flat surface so that the second photoresist pattern 90 formed thereon can be a good pattern for trench formation.

Referring to FIG. 10, a second photoresist pattern (third layer) is formed using an anisotropic etching process.
(To the dielectric layer 80). The anisotropic etching process is used to transfer the second photoresist pattern 90 transferred from the mask to the third dielectric layer 80, while the sacrificial film 60 functions as an etching stopper. 100 is formed.

Referring to FIG. 11, the extra portion of the sacrificial film and the second photoresist pattern are simultaneously removed. The second photoresist pattern 90 on the third dielectric layer 80 and the sacrificial film 60 in the via 50 are simultaneously removed to form a dual damascene structure including the via 50 and the trench 100. Second photoresist pattern 9
If 0 and the sacrificial film 60 can be removed at the same time, it is advantageous in that the entire IC process is simplified and the sacrificial film that deteriorates the device characteristics does not remain in the device. Second photoresist pattern 90 and sacrificial film 60
O ₂ is used as the ashing gas for removing the oxygen.

The method of forming vias and trenches in the copper dual damascene process of the present invention disclosed above has the following features: (1) Defects because the vias and trenches are formed by separate etching processes. It is possible to easily fill the via with sacrificial film material without causing: (2) In the process of forming the via and the trench, the photoresist pattern is spin-coated on a perfectly flat surface, It enables formation of a uniform photoresist pattern that is advantageous for exposure and development;
(3) Since the step is not formed on the dielectric layer, the depth of focus can be controlled to form a better photoresist pattern; and (4) the selection of the sacrificial film in the via with respect to the dielectric layer. Since the ratio is higher, the formed via shape will be protected.

As will be apparent to those skilled in the art, the preferred embodiments of the invention described above are not intended to limit the invention. Various modifications and similar forms within the spirit and scope of the appended claims are included in the technical concept intended by the present invention, and the technical scope of the claims of the present invention include such modifications. And all similar structures should be broadly interpreted to include within its scope.

[Brief description of drawings]

1A and 1B are cross-sectional views of a prior art semiconductor substrate in which a via is first formed in a dual damascene process prior to trench formation.

2A and 2B are cross-sectional views of a prior art semiconductor substrate in which a trench is first formed in a dual damascene process prior to the formation of vias.

3A and 3B are cross-sectional views of a prior art semiconductor substrate in which a buried hard mask is used to form vias and trenches in a dual damascene process.

FIG. 4 illustrates that a silicon nitride and a second dielectric layer according to the present invention are separately deposited on a semiconductor substrate containing an integrated circuit (not shown).

FIG. 5 illustrates a via formed in a second dielectric layer using an anisotropic etching process according to the present invention.

FIG. 6 illustrates how a sacrificial film is spin coated over the via and over the surface of the second dielectric layer according to the present invention.

FIG. 7 illustrates how an excess portion of a sacrificial film is removed using a planarization process according to the present invention.

FIG. 8 illustrates how a third dielectric layer according to the present invention is deposited on a planarized surface.

FIG. 9 shows how the shape of the trench is completely determined by the second photoresist pattern according to the present invention.

FIG. 10 illustrates how an anisotropic etching process is used to form a trench by transferring a second photoresist pattern according to the present invention.

FIG. 11 illustrates a state in which an excess portion of a sacrificial film and a second photoresist pattern are simultaneously removed according to the present invention.

[Explanation of symbols]

40 First dielectric layer 42 Silicon nitride 44 Second dielectric layer 46 Conductive area 50 vias 60 sacrificial film 80 Third dielectric layer 90 Second photoresist pattern 100 trench

Claims (29)

[Claims] 1. A method of forming vias and trenches on a substrate in a copper (Cu) dual damascene process, the method comprising: forming a semiconductor substrate on which a first dielectric layer having a conductive region is deposited; A step of forming the surface of the first dielectric layer and the surface of the conductive region in the same plane; and a silicon nitride (SiN) layer covering the conductive region and the first dielectric layer. Forming, forming a second dielectric layer on the silicon nitride layer, forming a via in the second dielectric layer, forming the via and the second dielectric layer Spin-coating a sacrificial film to fill the surface of the substrate, applying a planarization process to remove excess portions of the sacrificial film to form a planar surface, and a third step on the planar surface. A step of forming a dielectric layer, and the third dielectric layer The method comprising the steps of forming a trench, the. 2. The method of claim 1, wherein the silicon nitride layer is replaced with a silicon carbide film. 3. The second dielectric layer comprises SiO _x and FS.
A material comprising one material selected from the group containing G.
The method described in. 4. The method of claim 1, wherein the second dielectric layer has a thickness in the range of 3000 (Å) to 7000 (Å). 5. The step of forming a via further comprises: forming a via on the second dielectric layer to define the via.
A step of forming a first photoresist pattern; a step of anisotropically etching the second dielectric layer using the first photoresist pattern as a mask and the nitride layer as an etching stopper; Removing the first photoresist pattern to form the via. 6. The method according to claim 1, wherein the sacrificial film is an organic material having a low dielectric constant. 7. The method of claim 6, wherein the low dielectric constant organic material is FLARE. 8. The method of claim 6, wherein the low dielectric constant organic material is SiLK. 9. The sacrificial film is from 4000 (Å) to 800.
The method according to claim 1, having a film thickness in the range of 0 (Å). 10. The method of claim 1, wherein the planarization process is a chemical mechanical polishing (CMP) method. 11. The method of claim 1, wherein the planarization process is etchback. 12. The method of claim 1, wherein the planarization process is performed until the second dielectric layer is exposed. 13. The third dielectric layer comprises SiO _x and F.
The method of claim 1 comprising one material selected from the group comprising SG. 14. The third dielectric layer is 3000 (Å)
The method according to claim 1, having a film thickness in the range of 1 to 7000 (Å). 15. The forming of the trench step further comprises forming a second photoresist pattern on the third dielectric layer to define the trench, and the first photoresist pattern. Is used as a mask, and the sacrificial film is used as an etching stopper.
The method of claim 1, further comprising: anisotropically etching the dielectric layer of, and removing the sacrificial film in the via. 16. In a copper dual damascene process,
A method of forming vias and trenches on a substrate, comprising: a semiconductor substrate on which a first dielectric layer having a conductive region is deposited, a surface of the first dielectric layer and a surface of the conductive region. Forming the same planar shape, a step of forming a silicon nitride layer covering the conductive region and the first dielectric layer, and a second dielectric layer on the silicon nitride layer. A step of forming a layer, a step of forming a via in the second dielectric layer, a step of spin-coating a sacrificial film to fill the surfaces of the via and the second dielectric layer, and a planarization process Is applied to remove the excess portion of the sacrificial film to form a flat surface, a step of forming a third dielectric layer on the flat surface, and a step of forming a third dielectric layer on the flat surface. Second to determine the trench to
Forming a photoresist pattern, and using the sacrificial film as an etching stopper to transfer the second photoresist pattern to the third photoresist pattern.
Anisotropic etching of the dielectric layer, and simultaneously removing the sacrificial film in the second photoresist pattern and the via to form a dual damascene structure including the via and the trench. A method having ,. 17. The method of claim 16, wherein the silicon nitride layer is replaced with a silicon carbide film. 18. The second dielectric layer comprises SiO _x and F.
The method according to claim 16, comprising one material selected from the group comprising SG. 19. The second dielectric layer is 3000 (Å)
17. The method according to claim 16, having a film thickness in the range of 1 to 7000 (Å). 20. The step of forming a via further comprises: forming a via on the second dielectric layer to define the via.
A step of forming a first photoresist pattern; and a step of anisotropically etching the second dielectric layer using the first photoresist pattern as a mask and the silicon nitride layer as an etching stopper. 17. Removing the first photoresist pattern to form the via. 21. The method of claim 16, wherein the sacrificial film is a low dielectric constant organic material. 22. The method of claim 21, wherein the low dielectric constant organic material is FLARE. 23. The method of claim 21, wherein the low dielectric constant organic material is SiLK. 24. The sacrificial film is from 4000 (Å) to 80.
The method according to claim 16, having a film thickness in the range of 00 (Å). 25. The method of claim 16, wherein the planarization process is a chemical mechanical polishing (CMP) method. 26. The method of claim 16, wherein the planarization process is etchback. 27. The method of claim 16, wherein the planarization process is performed until the second dielectric layer is exposed. 28. The third dielectric layer comprises SiO _x and F.
The method according to claim 16, comprising one material selected from the group comprising SG. 29. The third dielectric layer is 3000 (Å)
17. The method according to claim 16, having a film thickness in the range of 1 to 7000 (Å).