JP3533022B2 - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a stacked via in which a through hole connecting upper wirings is arranged directly above a through hole connecting wirings. The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having a (Stacked Via) structure.

[0002]

2. Description of the Related Art In recent years, the integration of LSI has progressed, and the upper layer A
Since the aspect ratio (depth / diameter of the through hole) of the through hole connecting the 1 wiring and the Al wiring of the lower layer is increasing, it is possible to secure the conduction reliability of the wiring in the through hole formed in the interlayer insulating film. In order to do so, a so-called W plug technique of burying a W (tungsten) film in the through hole is used.

To embed a W film in the through hole, a W film is deposited on the interlayer insulating film having the through hole by a CVD method, and then the W film is etched back to form the W film only inside the through hole. leave. At this time, since F (fluorine) plasma is used for etching the W film, a Ti film is previously formed below the W film in order to prevent the underlying interlayer insulating film (silicon oxide film) from being etched by the F plasma. T
It is customary to lay a barrier metal composed of a laminated film or the like with an iN film.

Further, the barrier metal composed of the laminated film of the Ti film and the TiN film has a high resistance to electromigration and stress migration, and has a high effect of preventing the halation of the photoresist by the exposure light. Therefore, for the wiring of the LSI manufactured under the design rule of the submicron order, the Al composite film (TiN / T) in which the barrier metal is laminated on and under the Al film is used.
i / Al-Si-Cu / Ti / TiN) is used. The Al composite film of this type is described in, for example, Press Journal Co., Ltd., “Semiconductor World” p196 to p205, published on November 20, 1992.

[0005]

According to a study made by the present inventor, the conventional technique has the following problems.

(1) To embed a W film in a through hole, a W film is deposited on the interlayer insulating film by a CVD method, and then the W film on the interlayer insulating film is etched back to form a W film only inside the through hole. After the film is left, it is necessary to further wash the surface of the barrier metal (Ti / TiN laminated film) on the interlayer insulating film exposed by removing the W film.

This is because dry etching using F plasma is used for etching back the W film, so that etching residue (F in the plasma) on the surface of the barrier metal on the interlayer insulating film exposed by the removal of the W film is used. However, if an Al film is deposited without cleaning the surface of the barrier metal after etching back, the adhesive force at the interface between the barrier metal and Al will be reduced due to the etching residue. Is.

As described above, the conventional W plug technique requires the work of depositing, etching back, and cleaning the W film, and thus has a drawback that the process becomes complicated.

(2) In the W plug technique, the W film on the interlayer insulating film must be completely removed by overetching in order to leave the W film only inside the through hole. At this time, the surface of the W film in the through hole is also etched by overetching, so that a step is generated between the surface of the interlayer insulating film and the surface of the W film in the through hole.

Therefore, when an Al wiring is deposited on this interlayer insulating film, a step is also formed on the surface of the Al wiring just above the through hole due to the step. As a result, if an attempt is made to form a second through hole that connects the Al wiring and an Al wiring in an upper layer in the interlayer insulating film immediately above the through hole, the processing accuracy of the second through hole is reduced. It is difficult to realize a so-called stacked via structure in which an upper layer through hole is arranged directly above the through hole.

(3) As a technique for avoiding the above-mentioned problems of the W plug technique, a semiconductor substrate is kept at a high temperature and an Al film is deposited while being reflowed by the heat to secure the coverage in the through hole. Al reflow technology has been proposed.

However, the Al film (especially, A containing Cu added thereto)
Al-reflow technology has a problem that when a (1-Si-Cu film, Al-Cu film, etc.) is deposited at a high temperature, a reaction precipitate is generated in the film, which becomes a new cause of reducing the processing accuracy of Al wiring by dry etching. However, there are still many problems in introducing it into the mass production process.

It is an object of the present invention to provide a technique capable of realizing a stacked via structure without complicating the process.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) The semiconductor integrated circuit device of the present invention has the wiring of three or more layers on the semiconductor substrate, and the first wiring for electrically connecting the first wiring and the second wiring of the upper layer. A semiconductor integrated circuit device in which a second through hole for electrically connecting the second wiring and a third wiring above the second wiring is arranged directly above the through hole, and at least a part of the wiring. Is an adhesive layer deposited by sputtering and CVD
Embedded layer deposited by sputtering method, low resistance main conductive layer deposited by sputtering method, sputtering method or CVD
And a light reflection preventing layer deposited by a method.

(2) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, after forming the first through hole in the first interlayer insulating film on the semiconductor substrate, the inside of the first through hole is included. An adhesive layer is deposited on the first interlayer insulating film by a sputtering method, a buried layer is deposited on the adhesive layer by a CVD method, and a low resistance main conductive layer is deposited on the buried layer by a sputtering method. A step of depositing a light reflection preventing layer on the resistance main conductive layer by a sputtering method or a CVD method; and patterning the light reflection preventing layer, the low resistance main conductive layer, the embedding layer, and the adhesive layer. And forming a second through hole in the second interlayer insulating film directly above the first through hole after depositing a second interlayer insulating film on the first interconnect. Forming step and the second step Wherein including the inside of the through hole second
An adhesive layer is deposited on the interlayer insulating film of by a sputtering method,
Next, a buried layer made of a conductive film is deposited by the CVD method, then a low-resistance main conductive layer made of a conductive film is deposited by the sputtering method, and then a light reflection preventing layer made of the conductive film is deposited by the sputtering method or the CVD method. By the step of depositing and patterning the light reflection preventing layer, the low resistance main conductive layer, the embedding layer and the adhesive layer, the layers were electrically connected to the first wiring through the second through holes. Second
And the step of forming the wiring.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

In this embodiment, a MOS having a three-layer wiring is used.
・ It is applied to LSI and its manufacturing method is shown in
It demonstrates in order of a process using FIG.

[0020] First, as shown in FIG. 1, p ^- after the type of p-type impurities into the main surface of the semiconductor substrate 1 made of single crystal silicon (boron) to form a p-type well 2 by ion implantation, p
A field oxide film 3 for element isolation is formed on the main surface of the mold well 2 by a selective oxidation (LOCOS) method. Subsequently, a gate oxide film 5 is formed on the main surface of the p-type well 2 surrounded by the field oxide film 3 by a thermal oxidation method, and then p-type impurities (boron) are ion-implanted into the p-type well 2 to perform field oxidation. The p-type channel stopper layer 4 is formed in the p-type well 2 including the lower part of the film 3.
To form.

Next, after a polycrystalline silicon film and a silicon oxide film 9 are sequentially deposited on the semiconductor substrate 1 by the CVD method,
By patterning the two-layer film by dry etching using a photoresist as a mask, the MISFET
The gate electrode 6 is formed. An n-type impurity (for example, P) is introduced into the polycrystalline silicon film forming the gate electrode 6 in order to reduce its resistance value. The gate electrode 6 is formed by WSix, MoSix on the polycrystalline silicon film.
, TiSix, TaSix, etc. may be formed of a polycide film in which refractory metal silicide films are laminated.

Next, after depositing a silicon oxide film on the semiconductor substrate 1 by the CVD method, reactive ion etching (RI
The side wall spacer 8 is formed on the side wall of the gate electrode 6 by anisotropically etching the silicon oxide film by the method E).

Next, an n-type impurity (phosphorus) is added to the p-type well 2.
Are ion-implanted to form n-type semiconductor regions 7 and 7 forming source and drain regions of the MISFET in the p-type well 2 on both sides of the gate electrode 6.

Next, as shown in FIG. 2, a silicon oxide film 10 and a BPSG film 11 are formed on the semiconductor substrate 1 by the CVD method.
Are sequentially deposited, and then the BPSG film 11 and the silicon oxide film 1 are dry-etched using a photoresist as a mask.
By etching 0 and the gate oxide film 5,
A contact hole 12 that reaches one semiconductor region 7 of the MISFET is formed.

Next, as shown in FIG. 3, a Ti film 13 (thickness 30 nm) and a TiN film 14 (thickness 7) are formed on the BPSG film 11 including the inside of the contact hole 12 by a sputtering method.
Then, a W film 15 (film thickness 250 nm) is deposited on the TiN film 14 by the CVD method.

Next, as shown in FIG. 4, the W film 15 and Ti are dry-etched by using a photoresist as a mask.
By patterning the N film 14 and the Ti film 13, the wiring 16 of the first layer is formed.

Of the three layers of conductive films forming the wiring 16 of the first layer, the lowermost Ti film 13 functions as an adhesive layer for ensuring adhesiveness with the silicon substrate (semiconductor region 7). . Further, since the Ti film 13 reacts with the silicon substrate to form a low resistance Ti silicide layer at the interface between the two, the contact resistance of the wiring 16 can be reduced. The TiN film 14 functions as an adhesive layer for ensuring the adhesiveness between the Ti film 13 and the W film 15. Since the W film 20 deposited by the CVD method has better coverage than the W film deposited by the sputtering method, it is well embedded in the contact hole 12.

Next, as shown in FIG. 5, a first interlayer insulating film 17 (having a thickness of 0.5 to 2 μm) is deposited on the upper layer of the wiring 16 and then dry etching is performed using a photoresist as a mask. The through hole 1 is formed in the interlayer insulating film 17 on the W wiring 16.
8 is formed. The interlayer insulating film 17 is composed of, for example, a three-layer film including a silicon oxide film deposited by the CVD method, a spin-on-glass film deposited by the spin coating method, and a silicon oxide film deposited by the CVD method. The diameter of the through hole 18 is 0.3-
It is 0.5 μm.

Next, as shown in FIG. 6, the through hole 1
A W film 19 (film thickness 20 to 200 nm) is deposited on the inter-layer insulating film 17 including the inside of 8 by a sputtering method, and then CV
A W film 20 (film thickness 100 to 500 nm) is deposited by the D method, and an Al alloy (Al-Si-Cu) is further deposited by the sputtering method.
A film 21 (film thickness 200 to 2000 nm) is deposited, and finally a W film 22 (film thickness 20 to 200 nm) is deposited by a sputtering method.

The W film 19 as the lowermost layer functions as an adhesive layer for ensuring adhesiveness with the first layer wiring 16 made of W. Since the W film 20 deposited by the CVD method has better coverage than the W film 19 deposited by the sputtering method,
It functions as a buried layer inside the through hole 18. A
The l-alloy film 21 has a lower electric resistance than the W films 19 and 20, and thus functions as a low-resistance main conductive layer. Top W film 2
Since 2 has a lower light reflectance than the Al alloy film 21, it functions as a light reflection preventing layer that prevents halation when patterning the Al alloy film 21 by dry etching using a photoresist as a mask.

By embedding the W film 20 having a good coverage in the through hole 18 with a film thickness of a certain degree or more, the Al alloy film 21 deposited on the upper layer thereof is hardly embedded in the through hole 18. Therefore, as shown in the figure, the Al alloy film 21 above the through hole 18 is formed.
Surface becomes flat. However, if the W film 20 is not provided, a part of the Al alloy film 21 enters the inside of the through hole 18, so that the Al alloy film 2 on the through hole 18 is formed.
A step occurs between the surface of No. 1 and the surface of the Al alloy film 21 on the interlayer insulating film 17. Therefore, good coverage
The film thickness of the W film 20 is such that it does not exceed the certain level.
It is sufficient to embed it in the inside of the ruler 18 and
Of the wiring layer including the alloy film 21 and the coverage W film 20
The resistance is mainly the low resistance conductive layer of Al,
Compared with the case where the inside of the through hole is flattened with the W film 20,
Compared with the same total thickness, resistance value is low and thin W film
Since this is sufficient, there is an advantage that pattern processing becomes easy.

Next, as shown in FIG. 7, the W film 22 and Al are dry-etched by using a photoresist as a mask.
By patterning the alloy film 21, the W film 20, and the W film 19, the wiring 23 of the second layer is formed. The wiring 23 is the wiring 1 of the first layer through the through hole 18.
6 is electrically connected.

In this embodiment, since the adhesive layer, the burying layer and the light reflection preventing layer of the wiring 23 are made of the same material (W), it is possible to pattern these films with one kind of etching gas. The processing throughput is improved.

Next, as shown in FIG. 8, a second interlayer insulating film 24 (film thickness 0.5 to 2 μm) is deposited on the upper layer of the wiring 23, and then dry etching is performed using a photoresist as a mask. A through hole 25 is formed in the interlayer insulating film 24 immediately above the through hole 18 formed in the interlayer insulating film 17. The interlayer insulating film 24 has the same CV as the interlayer insulating film 17.
It is composed of a three-layer film of a silicon oxide film deposited by the D method, a spin-on-glass film deposited by the spin coating method, and a silicon oxide film deposited by the CVD method. The diameter of the through hole 25 is 0.3 to 0.5 μm, which is the same as the diameter of the through hole 18.

Next, as shown in FIG. 9, the through hole 2
A Ti film 26 (film thickness 20 to 200 nm) is deposited on the inter-layer insulating film 24 including the inside of No. 5 by the sputtering method, and then C
A TiN film 27 (film thickness 100 to 500 nm) is deposited by the VD method, and then an Al alloy (Al-Si-C) is deposited by the sputtering method.
u) A film 28 (film thickness 200 to 2000 nm) is deposited, and a Ti film 29 (film thickness 100 to 500) is formed by a sputtering method.
nm) and a TiN film 30 (film thickness 20 to 200 nm) are sequentially deposited.

The Ti film 26 of the lowermost layer is the wiring 2 of the second layer.
3 and the interlayer insulating film 24 to function as an adhesive layer for ensuring adhesiveness. TiN film 27 deposited by CVD method
Has a better coverage than the TiN film 30 deposited by the sputtering method, and thus functions as a buried layer inside the through hole 25. The Al alloy film 28 is the Ti film 26, 2
9. Since it has a lower electric resistance than the TiN films 27 and 30, it functions as a low resistance main conductive layer. The top TiN film 30
Has a light reflectance lower than that of the Al alloy film 28.
It functions as a light reflection preventing layer that prevents halation when patterning 28 . Therefore, good coverage
The thickness of the TiN film 27 does not exceed the certain level.
It is enough to fill the inside of the hole, and the upper Al
Wiring including alloy film 28 and coverage TiN film 27
The resistance of the layer is mainly the low resistance conductive layer of Al,
When the inside of the through-hole is flattened with the TiN film 27
Compared with, the resistance value is lower when compared with the same total thickness,
Since a thin TiN film is sufficient, pattern processing becomes easy.
There are advantages.

Then, as shown in FIG. 10, the TiN film 3 is formed by dry etching using a photoresist as a mask.
By patterning 0, the Ti film 29, the Al alloy film 28, the TiN film 27, and the Ti film 26, the wiring 31 of the third layer is formed. The wiring 31 is electrically connected to the wiring 23 of the second layer through the through hole 25.

In the present embodiment, the surface of the wiring 23 of the second layer is flat above the through hole 18 formed in the interlayer insulating film 17 of the first layer. The Ti film 26 and Ti in the through hole 25 formed in the upper interlayer insulating film 24
The coverage of the N film 27 becomes good. As a result, the reliability of the connection between the wiring 23 and the wiring 31 inside the through hole 25 is secured, so that the stacked via structure in which the through hole 25 is arranged directly above the through hole 18 can be realized with high yield.

Further, in the present embodiment, since the conductive film is embedded inside the through holes 18 and 25 without using the W plug technique, the stacked via structure can be realized without complicating the process. it can.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above-described embodiment, the adhesive layer and the light reflection preventing layer are made of W, Ti, TiN, etc. deposited by the sputtering method, but other refractory metals or refractory metal compounds (eg Mo, TiW, (Ti silicide, Mo silicide, etc.). Moreover, what was deposited by the CVD method may be used instead of the sputtering method.

Although the buried layer and the low resistance conductive layer are made of different materials in the above-mentioned embodiment, for example, Al or Cu (copper) is used.
By depositing a low resistance conductive material such as by the CVD method, it becomes possible to use both the buried layer and the low resistance conductive layer as one material. Further, if the adhesiveness between the embedded layer of the upper wiring and the lower wiring is good, the adhesive layer of the upper wiring may be omitted.

In the above-described embodiment, the M including the three-layer wiring is used.
The case of application to the OS / LSI has been described. However, by applying to an LSI provided with multilayer wiring of four layers or more, a through hole for connecting the wiring of the second layer and the wiring of the third layer is formed. A through hole for connecting the third-layer wiring and the fourth-layer wiring is arranged directly above, or the fourth-layer wiring and the upper-layer wiring are connected directly above this through-hole. Through holes can be arranged.

Further, the first-layer wiring and the second-layer wiring are provided directly above the contact holes connecting the semiconductor substrate and the first-layer wiring.
It is also possible to arrange a through hole for connecting to the wiring of the layer.

[0045]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the present invention, it is possible to realize a stacked via structure in which a through hole is arranged directly above the through hole with a high yield, so that the degree of freedom in wiring design is improved and the LSI is miniaturized. , High integration can be promoted.

(2) Further, according to the present invention, the stacked via structure can be realized in a smaller number of steps as compared with the W plug technique.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

[Explanation of symbols]

1 Semiconductor substrate 2 p-type well 3 field oxide film 4 channel stopper layer 5 Gate oxide film 6 Gate electrode 7 n-type semiconductor region (source / drain region) 8 Sidewall spacer 9 Silicon oxide film 10 Silicon oxide film 11 BPSG film 12 contact holes 13 Ti film 14 TiN film 15 W film 16 wiring 17 Interlayer insulation film 18 through holes 19 W membrane 20 W film 21 Al alloy film 22 W film 23 wiring 24 Interlayer insulation film 25 through holes 26 Ti film 27 TiN film 28 Al alloy film 29 Ti film 30 TiN film 31 wiring

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/768

Claims (5)

(57) [Claims] 1. A semiconductor substrate having three or more layers of wiring,
Directly above the first through hole that electrically connects the first wiring and the second wiring on the upper layer, the second wiring and the third wiring on the upper layer are electrically connected. Two through holes are arranged , and at least a part of the second wiring and the third wiring are deposited by a sputtering method, an adhesive layer deposited by a CVD method, and a sputtering method. In a semiconductor integrated circuit device having a laminated structure including a low resistance main conductive layer and a light reflection preventing layer deposited by a sputtering method or a CVD method.
The buried layer deposited by the CVD method is
Without flattening the upper surface in the hole,
The low resistance main conductive layer deposited by the sputtering method is
It has a thickness not embedded in the through hole,
The hole part is formed by the sputtering method of the low resistance main conductive layer.
A semiconductor integrated circuit device characterized in that it is planarized by deposition by . 2. The semiconductor integrated circuit device according to claim 1, wherein the adhesive layer and the light reflection preventing layer are made of a refractory metal or a refractory metal compound, and the buried layer is made of W or TiN. 2. The semiconductor integrated circuit device according to claim 1, wherein the low resistance main conductive layer is made of Al alloy or Cu. 3. The semiconductor integrated circuit device according to claim 1, wherein the adhesive layer, the burying layer and the light reflection preventing layer are made of the same conductive material. 4. A semiconductor substrate having three or more layers of wiring,
Directly above the first through hole that electrically connects the first wiring and the second wiring on the upper layer, the second wiring and the third wiring on the upper layer are electrically connected. is arranged a second through hole, the second wiring and the third at least a portion of the wiring, and a buried layer which is deposited by the CVD method, a low resistance main conductor layer deposited by sputtering,
A semiconductor integrated circuit having a laminated structure including a light reflection preventing layer deposited by a sputtering method or a CVD method.
Buried layer deposited by the CVD method in a channel device
Is to flatten the upper surface in the through hole portion.
A low resistance, which is not present and is deposited by the sputtering method
Shape formed by the thickness of the conductive layer is not embedded in the through hole
The through-hole portion is formed of the low resistance main conductive layer.
A semiconductor integrated circuit device characterized by being flattened by deposition by a puttering method . 5. A first interlayer insulating film on a semiconductor substrate is provided with a first
Of the first through hole, a first adhesive layer is deposited on the first interlayer insulating film including the inside of the first through hole by a sputtering method, and CV is formed on the first adhesive layer.
Depositing a first buried layer by the D method, depositing a first low resistance main conductive layer on the first buried layer by the sputtering method,
Said first depositing a first anti-reflection layer by sputtering or CVD to a low resistance main conductive layer, the first anti-reflection layer, the first low-resistance main conductive layer,
By patterning the first buried layer and the first adhesive layer, forming a first wiring, after depositing a second interlayer insulating film on the first wiring, the first Forming a second through hole in the second interlayer insulating film immediately above the through hole, and forming a second through hole on the second interlayer insulating film including the inside of the second through hole by a sputtering method . , An adhesion layer is deposited, and then a second burying layer made of a conductive film is deposited by a CVD method.
Next, a step of depositing a second low-resistance main conductive layer made of a conductive film by a sputtering method, and then a second light reflection preventing layer made of a conductive film by a sputtering method or a CVD method ; A light reflection preventing layer, the second low resistance main conductive layer,
Wherein by the second buried layer and patterning said second adhesive layer, a semiconductor and a step of forming a second wiring that is electrically connected to the first wiring through the second through hole In manufacturing method of integrated circuit device
The buried layer deposited by the first or second CVD method is
The top surface of the first or second through hole is flat.
Deposited by the above-mentioned sputtering method without supporting
The first or second low resistance main conductive layer is
Or formed with a thickness that does not fill the second through hole
However, the through-hole portion has the first or second low resistance.
Flattened by sputtering deposition of anti-main conductive layer
A method for manufacturing a semiconductor integrated circuit device, comprising: