JP2779186B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor device, and more particularly to a technique for forming a fine wiring above a connection hole formed in an insulating film.

[Conventional technology]

Conventionally, wiring materials for semiconductor integrated circuits have low electric resistance, good adhesion to silicon oxide films (SiO ₂ films),
Aluminum (A
l) is used.

However, when the wiring is miniaturized with the high integration of the semiconductor integrated circuit, a connection hole (contact hole) for connecting the semiconductor substrate and the wiring and a connection hole for connecting the upper and lower wirings are formed. As a result of an increase in the aspect ratio (depth / diameter of the connection hole) of the connection hole (through hole), a decrease in the step coverage of the wiring conductive film inside the connection hole becomes a serious problem.

As a countermeasure, a conventionally proposed method is to embed a conductive film such as a refractory metal or its silicide or polysilicon in a connection hole and to connect a wiring to a semiconductor substrate (or a lower wiring) through the conductive film. Is a technology to connect. To bury these conductive films in the connection holes, a selective CVD method or an etch-back method is used. In addition, regarding the technology for embedding the connection hole using the high melting point metal, for example, “Solid State Technology (Solid State Technology),
Japanese edition, February 1986, "Tungsten selection process by low pressure CVD" (EKBroadbent, WTStacy).

[Problems to be solved by the invention]

However, according to the study of the present inventor, the above-described technique of embedding the connection hole has the following problems.

FIGS. 7 and 8 show a semiconductor substrate in which wiring is connected to a connection hole in which a conductive film is buried. In the drawings, reference numeral 20 denotes a semiconductor substrate made of silicon single crystal;
Reference numeral 21 denotes a diffusion layer formed on the semiconductor substrate 20. On the semiconductor substrate 20, insulating films 22 and 23 made of, for example, SiO ₂ are deposited, and in the insulating films 22 and 23 above the diffusion layer 21, the connection holes 2 and 23 are formed.
4 is perforated.

In the inside of the connection hole 24, a conductive film 25 such as tungsten (W) deposited by a selective CVD method is embedded.
On the conductive film 25, a wiring 26 made of, for example, an Al alloy is connected.

To connect the wiring 26 on the connection hole 24, a wiring conductive film is deposited on the insulating film 23 by, for example, a sputtering method, and then the wiring conductive film is etched using a photoresist mask. At this time, a margin for misalignment between the connection hole 24 and the photoresist mask is required. Therefore, in the related art, a wide flange 27 is provided on the wiring 26 above the connection hole 24.

However, if a flange 27 is provided on a part of the wiring 26, the wiring
Since the line width of 26 becomes large, there is a problem that miniaturization of an integrated circuit is hindered.

On the other hand, if the flange 27 is abolished and the line width of the wiring 26 is reduced, the photoresist mask may be misaligned when etching the wiring conductive film. Conductive film 25
Is partially etched together with the wiring conductive film. At this time, the present inventor has proposed that when the inner wall of the connection hole 24 is opened perpendicularly to the main surface of the semiconductor substrate 20 as shown in FIG. And conductive film 25
Since a gap (S) is likely to be formed at the interface between the conductive layer 25 and the diffusion layer 21, the lower diffusion layer 21 is also over-etched through the gap (S). And that the electrical characteristics of the integrated circuit element are degraded.

It is an object of the present invention to provide a technique capable of realizing high integration of a semiconductor device by miniaturizing a wiring connected to an upper part of a connection hole in which a conductive film is embedded.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

The method of manufacturing a semiconductor device according to the present invention includes the following steps (a):
To (c).

(A) opening an insulating film deposited on a main surface of a semiconductor substrate to form a connection hole having an upper diameter larger than a bottom diameter; (b) the insulating film including the inside of the connection hole (C) embedding the first conductive film in the connection hole by etching and removing the first conductive film on the insulating film after depositing the first conductive film on the entire upper surface of the insulating film. After depositing a second conductive film over the entire upper surface of the insulating film, the second conductive film is etched using a photoresist as a mask, so that the diameter of the upper portion of the connection hole is equal to the diameter of the bottom of the connection hole. Or forming a wiring having a line width equal to or less than that.

[Action]

According to the above-described means, the second layer deposited on the connection hole
Etching the conductive film to make it equal to the diameter of the bottom of the connection hole,
Or, when forming a wiring having a line width smaller than that, even if misalignment occurs between the photoresist and the connection hole, the first conductive film of a large diameter portion is etched inside the connection hole, The connection reliability of the connection hole can be ensured by preventing over-etching of the insulating film. As a result, the wiring flange can be eliminated, and the wiring can be miniaturized.

Embodiment 1 FIG. 1 is a sectional view of a main part of a semiconductor substrate showing a semiconductor device according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (h) show a method of manufacturing this semiconductor device. FIG. 3 is a sectional view of a main part of a semiconductor substrate.

In FIG. 1, a semiconductor substrate 1 is made of, for example, a p-type silicon single crystal, and has, for example, an n-type diffusion layer 2 on a part of its main surface. On the semiconductor substrate 1, for example,
A field insulating film 3 made of SiO ₂ is formed, and an integrated circuit element such as a MOS / FET is formed in an element forming region (not shown) surrounded by the field insulating film 3. An insulating film 4a made of, for example, SiO ₂ is formed on the field insulating film 3.
Is formed, and the integrated circuit element is covered with the insulating film 4a.

Above the diffusion layer 2, the field insulating film 3 and the insulating film 4a
A contact hole (contact hole) 5a is formed. The connection hole 5a has a lower region in the semiconductor substrate 1
Is opened perpendicularly to the main surface of the substrate, and the diameter of the lower region is 0.5 μm, for example. In the upper region of the connection hole 5a, a tapered large diameter portion 6a is provided.

A conductive film 7a made of a refractory metal such as tungsten (W) is embedded in the connection hole 5a. The conductive film 7a is embedded so that the film thickness is larger than the height from the bottom of the connection hole 5 to the large diameter portion 6a.

On the conductive film 7a, for example, an aluminum alloy (Al-Si-
The first layer wiring 8a made of Cu) is connected. The line width of the wiring 8a is the same as the diameter of the lower region of the connection hole 5a, for example, 0.5 μm, and no flange is formed.

On the wiring 8a, for example, BPSG (Boro Phospho Silicate
An interlayer insulating film 9 made of, for example, glass (glass) is formed thereon.
Are formed. For example, PSG (Phospho
A passivation film 11 composed of two layers of silicate glass and Si ₃ N ₄ is formed to protect the integrated circuit from the external environment.

Next, a process of forming the connection hole 5a and the wiring 8a of the semiconductor device will be described with reference to FIGS.

FIG. 2A shows that, for example, Si
This shows a state in which an insulating film 4a made of O _{2 is applied} by a CVD method.

Thereafter, first, a photoresist mask 12 for connection holes is formed on the insulating film 4a (FIG. 2B).

Next, a portion of the insulating film 4a is opened by isotropic etching using, for example, a 5% hydrofluoric acid aqueous solution to form a large diameter portion 6a (FIG. 2 (c)).

Subsequently, the insulating film below the large-diameter portion 6a is subjected to, for example, reactive ion etching using a parallel plate type dry etching apparatus.
4a and the field insulating film 3 thereunder are opened vertically to form a connection hole 5a reaching the semiconductor substrate 1. The reaction gas used is, for example, a fluorocarbon-based gas such as CHF ₃ , CF ₄ , C ₂ F ₆ . (FIG. 2 (d)).

After that, for example, phosphorus (P),
Implant n-type impurity ions such as arsenic (As)
An n-type diffusion layer 2 is formed on the semiconductor substrate 1 below 5a.
(FIG. 2 (e)).

Next, for example, WF ₆ and a silane compound S represented by SiH ₄
gas mixture with i _n H _{2n + 2} (n = 1,2 ...) or WF ₆ and Si
A conductive film 7a made of W is buried in the inside of the connection hole 5a by a low-pressure CVD method using a reaction gas made of a mixed gas with Cl ₂ H ₂ (second example).
Figure (f). At this time, the thickness of the conductive film 7a is supposed to be greater than the height from the lower part of the connection hole 5a to the large diameter part 6a.

Subsequently, after a wiring conductive film 13 made of an aluminum alloy (Al-Si-Cu) is deposited on the semiconductor substrate 1 by, for example, a sputtering method, a wiring photoresist mask 14 is formed on the wiring conductive film 13. (FIG. 2 (g)).

Next, the wiring conductive film 13 is sputter-etched to connect the wiring 8a to the connection hole 5a (FIG. 2 (h)). At this time, if the line width of the wiring 8a is equal to or less than the diameter of the bottom of the connection hole 5a, if the misalignment between the connection hole 5a and the photoresist mask 14 occurs even slightly, as illustrated, The surface of the conductive film 7a embedded in the connection hole 5a is sputter-etched. However, in the first embodiment, since the large-diameter portion 6a is provided in the upper region of the connection hole 5a, only the conductive film 7a in the large-diameter portion 6a is sputter-etched, and the conductive film 7a in the lower region is sputter-etched. Never.

Therefore, even if a gap is formed at the interface between the inner wall of the lower region of the connection hole 5a and the conductive film 7a, the lower diffusion layer 2 is not over-etched through this gap.

As described above, according to the first embodiment, the following effects can be obtained.

(1). Along with providing the large diameter portion 6a in the upper region of the connection hole 5a, by embedding a conductive film 7a thicker than the height from the bottom to the large diameter portion 6a inside the connection hole 5a,
The diffusion layer 2 is not over-etched when the wiring conductive film 13 is sputter-etched to form the wiring 8a.

As a result, poor conduction between the conductive film 7a and the diffusion layer 2,
Since the electrical characteristics of the integrated circuit element can be reliably prevented from deteriorating, the connection reliability between the diffusion layer 2 and the wiring 8a connected via the conductive film 7a is improved, and the production yield of the semiconductor device is improved. .

(2). According to the above (1), the connection reliability between the diffusion layer 2 and the wiring 8a connected via the conductive film 7a can be secured without providing a flange on the wiring 8a connected above the connection hole 5a. In addition, the wiring 8a can be miniaturized, and high integration of the semiconductor integrated circuit can be realized.

Embodiment 2 FIG. 3 is a cross-sectional view of a main part of a semiconductor substrate showing a semiconductor device according to another embodiment of the present invention, and FIGS.
FIG. 9 is a cross-sectional view of a main part of a semiconductor substrate, illustrating a method for manufacturing the semiconductor device.

In FIG. 3, a semiconductor substrate 1 is made of, for example, a p-type silicon single crystal, and an n-type diffusion layer 2 is formed on a part of its main surface. A field insulating film 3 made of, for example, SiO ₂ is formed on the semiconductor substrate 1, and an integrated circuit element such as a MOSFET is formed in an element forming region (not shown) surrounded by the field insulating film 3. .

An insulating film 4a made of, for example, SiO ₂ is formed on the field insulating film 3, and the integrated circuit element is covered with the insulating film 4a.

On the insulating film 4a, a second insulating film 4b is laminated.
The insulating film 4a and the insulating film 4b, the etching rate is formed mutually different materials, when the insulating film 4a is SiO _2, the insulating film 4b
Is, for example, SOG (Spin On Glass).

Above the diffusion layer 2, a field insulating film 3 and an insulating film 4
A connection hole 5b formed by opening a and 4b is formed. The connection hole 5b is opened so that its cross section is stepped, and the upper region is a large diameter portion 6b. A conductive film 7b made of, for example, low-resistance polysilicon is buried in the connection hole 5b. The conductive film 7b is embedded so that the film thickness is larger than the height from the bottom of the connection hole 5b to the large diameter portion 6b.

On the conductive film 7b, for example, an aluminum alloy (Al-Si-
The first layer wiring 8a made of Cu) is connected. Wiring 8a
Under the lower layer, a thin barrier metal layer 8b made of, for example, metal silicide (WSi ₂ , MoSi _2, etc.) is formed for the purpose of improving the migration resistance of the wiring 8a. Wiring 8a
The line width of the barrier metal layer 8b is, for example, 0.5 μm like the diameter of the lower part of the connection hole 5b, and no flange is formed.

An interlayer insulating film 9 made of, for example, BPSG is formed on the wiring 8a, and a second-layer wiring 10 made of, for example, an aluminum alloy is formed thereon. On the wiring 10, for example, a passivation film 11 composed of two layers of PSG and Si ₃ N ₄
Are formed to protect the integrated circuit from the external environment.

Next, a process of forming the connection hole 5b and the wiring 8a of the semiconductor device will be described with reference to FIGS.

FIG. 4A shows that, for example, Si
After the insulating film 4c made of O _{2 is} deposited by the CVD method, the insulating film 4c is formed.
On a, for example, using a spin coating device (spinner), SOG
2 shows a state in which an insulating film 4b made of is adhered.

Thereafter, first, a photoresist mask 12 for connection holes is formed on the insulation film 4b, and then the insulation films 4a and 4b and the field insulation film 3 are opened by wet etching using, for example, a 5% hydrofluoric acid aqueous solution to form connection holes. Form 5b. At this time, SO
The insulating film 4b made of G has a higher etching rate than the insulating film 4a made of SiO ₂ and the field insulating film 3, so that it is quickly etched, and the upper region of the connection hole 5b (the region where the insulating film 4b is removed) is formed. The large diameter portion 6b is formed. (FIG. 4 (b)).

Next, n-type impurity ions such as phosphorus (P) and arsenic (As) are implanted into the surface of the semiconductor substrate to form an n-type diffusion layer 2 in the semiconductor substrate 1 below the connection hole 5b. _4, and H _2, PH ₃ (or AsH ₃₎ and by a CVD method using a reaction gas comprising a mixed gas insulating film 4b depositing a conductive film 7b made of low-resistance polysilicon on (FIG. 4 (C)). At this time, since the connection hole 5b has a stepped cross section and a large diameter portion 6b in the upper region, even when the aspect ratio is large, the conductive film 7b is completely embedded therein. Can be.

Subsequently, the conductive film 7b on the insulating film 4b is removed by an etch-back method, leaving the conductive film 7b inside the connection hole 5b (FIG. 4 (d)). In order to etch back the conductive film 7b, for example, reactive ion etching using a parallel plate dry etching device is used.

Thereafter, a barrier metal and a conductive film for wiring are sequentially deposited on the insulating film 4b by, for example, a sputtering method.

The barrier metal is, for example, a metal silicide such as WSi ₂ or MoSi ₂ , and the conductive film for wiring is, for example, an aluminum alloy.

Next, a photoresist mask for wiring is formed on the conductive film for wiring.
After forming 14, a conductive film for wiring and a barrier metal are sputter-etched to form a barrier metal layer 8b on the connection hole 5a.
The wiring 8a is connected via the. (FIG. 4 (e)). At this time, if the line width of the barrier metal layer 8b and the wiring 8a is equal to or smaller than the diameter of the bottom of the connection hole 5b, if there is a slight misalignment between the connection hole 5b and the photoresist mask 14, it is shown in FIG. As described above, the surface of conductive film 7b embedded in connection hole 5b is sputter-etched. However, in the second embodiment, the large diameter portion is provided in the upper region of the connection hole 5b.
Since 6b is provided, only the conductive film 7b of the large diameter portion 6b is sputter-etched, and the conductive film 7b in the lower region is not sputter-etched.

That is, even when a gap is formed at the interface between the inner wall of the lower region of the connection hole 5b and the conductive film 7b, even the lower diffusion layer 2 is not over-etched through the gap. The same effect as described above can be obtained.

In the second embodiment, the insulating film 4a is formed on the insulating film 4a.
Since the insulating film 4b having a higher etching rate than the insulating film 4b is applied, the opening of the connection hole 5b and the formation of the large-diameter portion 6b can be simultaneously performed by a single etching. The throughput of the step of forming 6b is improved.

Furthermore, since the insulating film 4b made of SOG is deposited on the insulating film 4a, the surface of the insulating film 4a is flattened, and the reliability of the wirings 8a and 10 formed thereon is improved.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the first and second embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

In the above embodiment, when a large diameter portion is provided in a part of the connection hole,
Although a part of the inner wall of the connection hole was processed into a tapered shape (Example 1) or a stepped shape (Example 2), the present invention is not limited to these methods. For example, as shown in FIG.
A part of the inner wall of 5c is processed into a reverse taper shape to provide a large diameter portion 6c, or as shown in FIG. 6, a part of the connection hole 5d is processed into a taper shape, and then processed into a reverse taper shape. Alternatively, a large diameter portion 6d can be provided.

In the first and second embodiments, the case where an Al alloy is used as the conductive film material for wiring is described. However, the present invention is not limited to this. For example, a refractory metal, a silicide compound thereof, polysilicon, TiN Or the like may be used.

In the first and second embodiments, the case where the present invention is applied to the connection hole (contact hole) for connecting the diffusion layer of the semiconductor substrate and the wiring is described. It can also be applied.

〔The invention's effect〕

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

That is, according to the present invention, when the second conductive film deposited on the connection hole is etched to form a wiring having a line width equal to or smaller than the diameter of the bottom of the connection hole,
Since over-etching of the insulating film can be prevented, the flange of the wiring can be eliminated and miniaturization can be achieved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor substrate showing a semiconductor device according to an embodiment of the present invention, and FIGS. 2 (a) to (h) are main parts of a semiconductor substrate showing a method of manufacturing the semiconductor device. FIG. 3 is a cross-sectional view of a main part of a semiconductor substrate showing a semiconductor device according to another embodiment of the present invention. FIGS. 4 (a) to 4 (e) show a method of manufacturing the semiconductor device. 5 and 6 are cross-sectional views of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 7 is a cross-sectional view of a conventional semiconductor device. 8 is a sectional view taken along line VII-VII of FIG. 8, FIG. 8 is a schematic plan view of the semiconductor device, and FIG. 9 is a sectional view of a main part of a conventional semiconductor device. 1,20 ... semiconductor substrate, 2,21 ... diffusion layer, 3 ... field insulating film, 4a, 4b, 22, 23 ... insulating film, 5a, 5b, 5c, 5d, 24 ...
... Connection holes, 6a, 6b, 6c, 6d ... Large diameter parts, 7a, 7b, 25 ... Conductive films, 8a, 10, 26 ... Wiring, 8b ... Barrier metal layers, 9 ...
Interlayer insulating film, 11 passivation film, 12, 14 photoresist mask, 13 conductive film for wiring, 27 flange, S gap.

Claims (1)

(57) [Claims] 1. A method of manufacturing a semiconductor device, comprising the following steps (a) to (c): (a) opening an insulating film deposited on a main surface of a semiconductor substrate, Forming a connection hole having a diameter larger than the diameter of the bottom portion; (b) depositing a first conductive film over the entire upper surface of the insulating film including the inside of the connection hole; (1) a step of embedding the first conductive film inside the connection hole by etching and removing the conductive film; (c) depositing a second conductive film over the entire upper surface of the insulating film; Forming a wiring having a line width equal to or less than the diameter of the bottom of the connection hole above the connection hole by etching the second conductive film.