JP2988943B2 - Method of forming wiring connection holes - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to wiring of a semiconductor element,
It is suitable for wiring connection holes, that is, contact holes.

(Prior Art) In an integrated circuit device in which the integration degree is further improved and CD (Cost Down) is desired, lithography (Lithogra
There is a demand for a technique for forming fine contact holes by reducing misalignment occurring in the phy) process. A method of forming a contact hole used in a conventional integrated circuit device will be described with reference to FIGS. Although the figure shows an integrated circuit element having a multi-layer wiring, the structure below the first-layer wiring (closer to the semiconductor substrate), which is not directly related to the present invention, is simplified and only the insulator layer and the semiconductor substrate are used. showed that. In this multilayer wiring element, an active or passive region (not shown) is formed by introducing and diffusing an impurity of the opposite conductivity type into the semiconductor substrate 1 having a certain conductivity type made of, for example, silicon. An electrode made of a conductive metal and a wiring layer are provided here, and a second layer wiring is formed of a conductive metal on an interlayer insulating layer covering the electrode and the wiring layer. As shown in FIG. 1, the insulating layer 2 formed on the surface of the silicon semiconductor substrate 1 includes a conductive metal such as Al or an Al alloy (Al-Si-Cu, Al-Si And the like, and a first wiring 3 made of such a material is provided, and this is covered with an interlayer insulating film 4.
In forming the contact hole 5 in the interlayer insulating film 4 by etching, the first wiring 3 functions as a stopper in a step of removing the corresponding interlayer insulating layer 4 by etching, so that over-etching is considered. No need. As shown in FIG. 1, the first wiring 3
In addition to the diameter a of the contact hole 5 formed so that an electrical connection can be made, an alignment margin b required at the time of the lithography process must be considered in advance. On the other hand, FIG. 2A and FIG. 2B show an example in which the first wiring dimension is reduced in which the matching margin b is omitted for miniaturization of the element pattern, but this improves the integration density of the integrated circuit.

(Problems to be Solved by the Invention) As shown in FIG. 1, when the diameter of the contact hole 5 is a, there is a need for a margin b between the first wiring 3 and the first wiring 3. The width c is a + 2b, and the diameter is limited by the lithography resolution and cannot be reduced unnecessarily. In order to actually form a diameter of 2 μm × 2 μm, a margin b is 1.5 μm, that is, a total of 5 μm. It becomes considerably larger than the wiring 2 μm. This degrades the integration density, which requires wasted space. On the other hand, when the wiring of the first layer is not used as a stopper in the etching step as shown in FIGS. 2A and 2B, it must be stopped at an appropriate time.

By the way, in the semiconductor integrated circuit device, various components are formed monolithically from the first wiring 3 to the semiconductor substrate. Therefore, the interlayer insulating layer 4 subjected to the planarization process has a film thickness corresponding to the components. Differences occur.

For example, in the structure shown in FIG. 2A in which a double layer of a polycrystalline silicon layer 6 having a thickness of 0.3 μm and an oxide film 7 having a thickness of about 0.1 μm formed near its surface is arranged as the first wiring 3, 2. The thickness of the interlayer insulating layer is smaller than that of the structure shown in FIG. Therefore, when the structure shown in FIGS. 2A and 2B coexists in the same semiconductor substrate 1, the etching process is continued until one (FIG. 2B) contact hole 5 is completed. Over-etching.

For this reason, as apparent from the figure, a groove 8 which penetrates is formed at a position K which deviates from the first wiring. This causes so-called step breaks or step lines to occur in the second layer wiring 9 deposited in the contact holes, and impairs the reliability of the semiconductor integrated circuit device.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method of forming a contact hole for preventing disconnection or a step of a wiring layer deposited on the contact hole.

[Structure of the invention]

(Means for Solving the Problems) According to the method for forming a wiring connection hole of the present invention, a plurality of wiring layers made of conductive materials having different top surfaces from each other are formed on a semiconductor substrate via an insulator layer. And forming an interlayer insulating layer on the upper surfaces of the plurality of wiring layers, and forming a portion of the interlayer insulating layer corresponding to the plurality of wiring layers on a wiring having a low top surface height. An etching step of removing the layer until the surface of the layer is exposed to form a plurality of contact windows at the same time; and, by this etching step, a fine layer formed in the interlayer insulating layer on the side of the wiring layer having a high top surface. Covering the entire surface of the interlayer insulating layer including the groove and the contact window with a filling material, and simultaneously removing portions of the filling material layer formed in this step corresponding to the plurality of contact windows to remove the plurality of contact windows. Wiring layer Exposing, leaving the filler in the microgrooves,
And connecting another wiring to the plurality of wiring layers through the plurality of contact windows.

(Operation) In some cases, the wiring for the semiconductor element is provided not only on the insulating layer formed on the semiconductor substrate but also via an intervening substance other than the insulating layer. Including. For this reason, the top surfaces of the two wirings are located on different planes, and are electrically connected to each other by another wiring extending along the other insulating layer covering the wiring, that is, the flat surface of the interlayer insulating film. In some cases.

The interlayer insulating film forming the contact hole of such a semiconductor element is subjected to a step of exposing the first and second wirings whose top surfaces are located on different planes, and a window is formed. The contact material is etched by etching the filler covering the micro-grooves generated at a position away from the wiring to expose the first wiring again. The thickness of the filler is smaller than the depth of the contact hole, but is sufficient to fill the groove formed in the step of exposing the first wiring. Since the thickness of the filler is constant, the etching step can be performed without over-etching. As a result, disconnection and disconnection of the second wiring which is deposited in the contact hole and electrically connected to the first wiring layer can be prevented, and there is an advantage that the reliability of the semiconductor element is improved, and an effect on mass production is obtained. Extremely large.

(Example) As an example according to the present invention with reference to FIGS.
This will be described using contact holes in a 16-bit AD converter. In mass production, many contact holes are formed for each bit at a time.

In this integrated circuit device, for example, a plurality of active or passive regions are formed by introducing and diffusing an impurity of the opposite conductivity type into a silicon semiconductor substrate having a certain conductivity type, and circuit elements such as resistors necessary for a circuit to be manufactured are monolithically formed. Monoly
thic). In such an active or passive area and a circuit element, a wiring layer is provided with a conductive metal layer in order to form a necessary circuit by bringing a conductive metal layer into contact with the conductive metal layer. In a circuit, a so-called multilayer wiring element is obtained by forming wiring layers in multiple stages using an interlayer insulating film.

On the other hand, the necessity of the circuit element is not limited to the multi-layer wiring element, but is also applied to the single-layer wiring element, and it is added that the method of the present invention is applicable to both of these elements. In the figures, only the silicon semiconductor substrate 10 that is directly related to the method of the present invention, that is, active or passive regions, circuit elements, and the formed insulator layer 11 are illustrated. This insulator layer 11 also assumes both an oxide film directly covering the surface of the semiconductor substrate 10 and a so-called interlayer insulator layer. This insulator layer 11
Indicates a so-called field insulator layer in a semiconductor element, and the thickness varies depending on the withstand voltage of the element, but a typical value is shown in the following description.

As apparent from FIG. 3A, the insulating layer 11 having a thickness of about 7000 to 8000 mm provided on the semiconductor substrate 10 has a thickness of 0.8 μm electrically connected to the active or passive region as described above.
A first wiring 12 having a thickness of about 1.0 μm, a polycrystalline silicon layer 13 having a thickness of about 0.4 μm electrically connected to circuit elements such as resistors, and an oxide film (thickness of about 1000 °) 14 continuous with the polycrystalline silicon layer 13; Here, a state where the first wiring 15 is overlapped is shown. Therefore,
The top surfaces of the first wirings 12 and 15 are located on different planes. In addition, Al or Al
Use alloys (Al-Si-Cu, Al-Si, etc.).

Next, a specific manufacturing process will be described. An Al alloy containing 1% by weight of Si in Al is deposited to a thickness of 1.0 μm for the first and second wirings 12 and 15 by a sputtering process. Reactive ion etching (Reactive
Patterning is performed by an Ion Etching method, and an oxide film 14 is continuously formed on the insulator layer 11 and the polycrystalline silicon layer 13.
The first and second wirings 12 and 15 are formed on top of each other.

The polycrystalline silicon layer 13 and the oxide film 14 continuous with the polycrystalline silicon layer are regarded as inclusions in the claims, but the following description is based on the former.

Next, a silicon oxide layer 16 that functions as an interlayer insulating layer and covers the first wirings 12 and 15 is formed by chemical vapor deposition (Ch).
The layer is deposited to a thickness of about 1.5 μm by an emical vapor deposition method. Further, the surface of the silicon oxide layer 16 corresponding to the first and second wirings 12 and 15 is formed on the surface of the silicon oxide layer 16 by a normal resist etch back method using a reactive ion etching method as a part of the formation process. A flattening step was performed. Subsequently, a window 18 for a contact hole 17 is provided by ordinary photolithography and reactive ion etching to expose the first wirings 12 and 15. The end point of the reactive ion etching process is about 10% over (Over) after the etching proceeds to the top surface of the first wiring 12.
It was decided from the etching rate to be etched,
The wirings 12 and 15 are slightly displaced from the contact holes 17 and a thin groove K is formed in the vicinity of the thickness of the first wiring 15. This is shown in FIG.
By depositing a silicon oxide film 19 having a thickness of about 0.3 μm by the method, the narrow groove K is filled, and the side wall 20 of the window 18 and the surface of the silicon oxide layer 16 are also covered. Becomes The silicon oxide film 19 that functions as such a filler is shown as a filler in the claims.

Next, as shown in FIG. 3C, the entire surface is etched back by reactive ion etching in order to remove the silicon oxide film 19 at the bottom of the window 18 and expose the first wirings 12, 15. This amount was determined so that 10% overetching was performed after the silicon oxide film 19 was etched. At this time the window
Since the silicon oxide film 19 in 18 has the same thickness at all positions, it is all over-etched by 10%.

This etch-back step may be an isotropic etching means instead of a reactive ion etching method, that is, an anisotropic etching means. This is because when the depth and width of the narrow groove K are large, anisotropic etching is good, but when it is small, isotropic etching does not affect the surroundings, so that it is possible. In this manner, a contact hole 17 is formed. As shown in FIG. 3D, a second wiring 21 made of Al or an Al alloy is deposited by a sputtering method and electrically connected to the first wirings 12 and 15. Connecting.

As a result, the multilayer wiring of the 16-bit AD converter is completed, and silicon nitride or PSG (Phosphor Sillcate
The semiconductor integrated circuit device is completed through a passivation layer forming step including glass or a mixed layer of both. As described above, the embodiment for the 16-bit AD converter has a multilayer wiring structure, but it is to be noted that the present invention is naturally applicable to a single-layer wiring element as described above.

〔The invention's effect〕

As described above, according to the method of the present invention, the plurality of wires can be formed with a diameter equal to or less than the dimension of the contact hole regardless of the installation location of the plurality of wires constituting the first layer wire. The degree of integration is much higher than in the prior art, which was possible only when the wirings to be provided existed on the same plane.

For example, the chip size of a 7000-element bipolar LSI [2 μm wiring rule (Rule)] is conventionally 4.3 × 4.6 mm but 3.4 × 3.8.
mm, and the area was reduced by about 35%.

Further, when the method of the present invention is not performed, the yield is reduced due to the disconnection of the second-layer wiring, and the difference in the yield of the bipolar LSI is about 20%, which is an extremely effective means.

Furthermore, in a reliability test of a semiconductor device and a semiconductor integrated circuit device formed of a single-layer wiring, a 50% life improvement effect was recognized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and FIGS. 2a and 2b are cross-sectional views showing the structure of a conventional contact hole, and FIGS. 3a to 3d are cross-sectional views for each step of the method of the present invention. 1, 10: semiconductor substrate, 2, 11: insulating layer, 3, 12, 15: first wiring, 4, 16: interlayer insulating layer, 5, 17: contact hole, 6, 13: polycrystalline silicon, 7, 14: oxide film, 18: window, 19: silicon oxide film, 20: side wall, 21: second wiring.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Osamu Hirata, Inventor 1 Komukai Toshiba-cho, Saiyuki-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Toshiba Tamagawa Plant Co., Ltd. (56) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/88

Claims (1)

(57) [Claims] A step of forming a plurality of wiring layers made of a conductive material having different top surfaces from each other via an insulating layer on a semiconductor substrate; and forming an interlayer insulating layer from the upper surfaces of the plurality of wiring layers. Stacking and forming a plurality of contact windows, removing portions of the interlayer insulating layer corresponding to the plurality of wiring layers until the surface of the wiring layer having a lower top surface is exposed, And an etching step of simultaneously forming the trench and the entire surface of the interlayer insulating layer including the fine grooves and the contact windows formed in the interlayer insulating layer on the side of the wiring layer having a high top surface. A step of coating with a filler material, and simultaneously removing portions of the filler layer formed in this step corresponding to the plurality of contact windows to expose the plurality of wiring layers, and filling the filler in the minute groove. Leave Process and method of forming the wiring connection hole, characterized in that a step of connecting the other wiring to the plurality of wiring layers via a plurality of contact windows.