JPH0358424A - Formation of wiring connecting hole - Google Patents

Abstract

PURPOSE:To avoid the cut due to step and electrical disconnection of wiring layers deposited in contact holes thereby enhancing the reliability by a method wherein the covering process of a fine groove filler on the whole surface of the other insulator layer including windows exposing the first wiring layer as well as an etching process leaving the filler in the fine groove made in the position isolated from the first wiring layer are provided. CONSTITUTION:Within an interlayer insulating film 16 wherein contact holes 17 of semiconductor element are to be formed, the process to expose the first and second wiring 12, 15 mounted on different levels is performed to form windows 18 and then the contact holes 17 are formed by etching away a filler 19 covering fine groove K made in the position where the first wiring 12 is isolated from the contact holes 17 to expose the first tiring 12 again. The thickness of the filler 19 is specified to be less than the depth of the contact holes 17 but to be sufficient to fill up the groove K made during the exposure process of the first wiring 12. Through these procedures, the electriccal disconnection and the cut due to step between the first wiring layer 12 and the second wiring layer 15 electrically connecting to the first layer 12 depositing in contact holes 17 can be avoided thereby enhancing the reliability.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Application in Industry) The present invention relates to wiring of semiconductor devices, and is particularly suitable for wiring connection holes, that is, contact holes. As the degree of C. D (CostD
In integrated circuit devices, which are desired to be fully integrated, there is a need for techniques for forming fine contact holes by reducing misalignment that occurs during the lithography process. The shape and method of contact holes conventionally used in integrated circuit devices will be explained with reference to FIGS. 1 and 2. Although the figure shows an integrated circuit element with multilayer wiring, the structure below the first layer wiring (closer to the semiconductor substrate), which is not directly related to the present invention, is simply drawn, and the insulator layer and semiconductor substrate only showed. In this multilayer wiring element, for example, silicon exhibits various conductivity types, and an active or passive region (not shown) is formed by introducing and diffusing impurities of the opposite conductivity type into the semiconductor substrate 1 on which an insulating layer is provided. Thereafter, an electrode and a wiring layer made of a conductive metal are provided, and a second layer wiring is formed of a tetraconductive metal on an interlayer insulating layer covering the electrode and wiring layer. Specifically, as shown in FIG.
-Cu. A first wiring 3 made of (AM-Si, etc.) is installed, and this is covered with an interlayer insulation 11 and a hollywood 4. When forming the contact hole 5 in this interlayer insulating film 4 by etching, over-etching must be taken into consideration since the first wiring 3 functions as a stopper during the etching removal process of the corresponding interlayer insulating layer 4. There's no need. As shown in FIG. 1, in addition to the diameter a of the contact hole 5 that is formed so as to make a one-dimensional connection to the first wiring 3, a fitting margin b required during the lithography process is taken into account in advance. I have to be there. On the other hand, FIG. 2a shows an example of reduction in the first wiring size in which the alignment margin b is omitted for miniaturization of the element pattern. As explained in b., this improves the integration density of integrated circuits. (Problem to be Solved by the Invention) When the diameter of the contact hole 5 is a as shown in FIG. The width C is a + 2b, and #l cannot be made unnecessarily small due to constraints due to the resolution of phosphorography, and in order to form an actual diameter of 2 μm x 2 μrn, the margin b is 1.5 μm, making a total of 5 μm. wiring 2μ
m becomes larger. This requires wasted space and deteriorates the integration density. On the other hand, if the first layer wiring is not used as a stopper in the etching process as shown in FIGS. 1 and 8, b, the etching process must be stopped at an appropriate point.

By the way, in a semiconductor integrated circuit device, various components are monolithically formed from the first wiring 3 toward the semiconductor substrate, so that the interlayer insulating layer 4 subjected to the planarization process is not compatible with the components. There will be a difference in film thickness. For example, as the first wiring IIA3, a polycrystalline silicon layer 6 with a thickness of 0.3 μm and a layer with a thickness of 0.1 μm formed near the surface thereof.
In the structure shown in FIG. 2a in which a double layer of oxide film 7 of approximately m thickness is arranged, the thickness of the interlayer insulating layer is thinner than in the structure shown in FIG. 2b. Therefore, in the same semiconductor substrate 1, as shown in FIG. When structures b coexist, one (Fig. 2 b
), the etching process continues until the contact hole 5 is completely etched, resulting in over-etching for the other contact hole 5. Therefore, as is clear from the figure, a penetrating groove 8 is formed at a location K that deviates from the first wiring. This causes so-called broken lines or broken lines to occur in the second layer green layer 9 deposited in the contact hole, impairing the reliability of the semiconductor integrated circuit element. The present invention has been made in view of the above-mentioned circumstances, and in particular, it is an object of the present invention to provide a method for forming a contact hole that prevents breaks and dashed lines in the wiring layer deposited in the contact hole.

[Structure of the invention]

(Means for Solving the Problem) A step of installing a first wiring made of a conductive metal on an insulating layer covering a semiconductor substrate, a step of wrapping the first wiring with another insulating layer, A step of forming a window that exposes the l-th wiring whose top surface is located on a different plane by removing another insulating layer corresponding to the l-th wiring, and removing the entire m1 of other insulating layers including this window. an etching process that leaves the filler in the micro grooves where the window is located away from the first wiring; The feature of the contact hole forming method according to the present invention lies in the step of connecting the contact holes.

(Function) In addition to being installed on an insulating layer formed on a semiconductor substrate, wiring for a semiconductor element may also be provided through an intervening material other than this insulating layer, but the method of the present invention naturally allows wiring for both. including.

For this reason, the top surfaces of both wirings are located on different planes,
Further, there are cases where the two are electrically connected by another wiring extending along the flat surface of another insulating layer covering this wiring, that is, an interlayer insulating film.

After forming a window in the interlayer IIIt film that forms the contact hole of such a semiconductor element by performing a step of exposing the first and second wirings whose top surfaces lie on different planes,
The contact hole is formed by etching the filler covering the micro groove where the contact hole is formed away from the first wiring to expose the first wiring again. The thickness of the filling material is made thinner than the depth of the contact hole, but the first
Make the ttlt part formed by the UA thick enough to block the wiring. Since the thickness of this filler is constant, the L-etching process can be performed without over-etching.As a result, it is deposited in the contact hole.
It has the advantage of preventing dashed lines and breakage of the second wiring which are connected to the wiring of the first conductor, improving the reliability of the semiconductor cable, and improving production efficiency. Extremely large.

(Embodiment) Referring to FIG. 3a=d, an embodiment of the present invention will be explained using a contact hole in a 16 bisotho AL converter. In mass production, a large number of contact holes must be formed for each type. This integrated circuit element C is manufactured by, for example, introducing impurities of the opposite conductivity type into a silicon semiconductor substrate exhibiting a certain conductivity type to form a plurality of active or passive regions. 1
The circuit elements such as the resistance necessary for the path are monolithic (N
onolythie). In such active or passive regions and 111 path elements, a wiring layer is provided with a conductive metal layer in order to establish electrical continuity by contacting the conductive metal layer and to configure a necessary circuit. In complex circuits, wiring scraps are constructed in multiple stages using interlayer insulating films to obtain so-called multilayer wiring elements.

On the other hand, circuit elements are required in multilayer circuits; A-14;
It should be noted that the method of the present invention is applicable not only to single-layer wiring elements but also to single-layer wiring elements.
In addition, only the silicon semiconductor substrate 10 directly relevant to the method of the invention, i.e. the active or passive regions, the circuit elements and the formed insulator layer 1l are shown in the figure; this insulator layer l1 is also part of the semiconductor substrate lO. This insulating layer 1l, which is assumed to be both an oxide film directly coated on the surface and a so-called interlayer insulating layer, refers to a so-called field insulating layer in a semi-integrated device, and is a material that increases the breakdown voltage of the device. As for the thickness, Barrack has shown typical values in the following description. Furthermore, in the claims, the interlayer insulating layer is described as another insulating layer.4 As is clear from FIG. 3a. E
The thickness of the electrical connection to the active or passive area as shown in (). 8μm = t, 0μ(n first wiring 1
2, and Jlisa 0 electrically connected to the circle elements such as resistance.
．． A polycrystalline silicon layer 13 with a thickness of about 4 μm and an oxide film I4 (thickness about IOOOA) connected thereto are provided. Here, the first wiring 15 is shown in a flat state.Therefore, the first wiring 12, the fli plane of i5, is located in a different position.Matsuo, wiring 12. 15 and the wiring described below,
^Use Q or AQ alloys (AQ-Si-Cu.AQ-Si, etc.).

Next, to explain the specific manufacturing staff Pa, the first and second allocations are $12. After depositing 1.0 μm of A4 alloy containing 1% Si by sputtering process on the legs for No. 15, normal photolithography and reactive ion etching were performed.
Pat.terni Kano L
Then, the insulator layer 11 and the polycrystalline silicon layer l3 are continuously oxidized! This polycrystalline silicon layer 13 and the oxide film l4 continuous thereto, which are formed by overlapping the L-th and second wirings i2 and l5 on Jl4, are treated as inclusions within the scope of the patent and J-request, but will be described later. is due to the former.

Next, a silicon oxide layer 16 that covers the first wirings 12 and 15 and functions as an interlayer insulating layer is formed by chemical vapor deposition.
on) method to a thickness of approximately 1.5 μm. In addition, the surface of the silicon oxide layer 16 corresponding to the first and second wirings 12 and 15 is etched by a normal resist etch back method using a reactive ion etching method as part of the formation process. A flattening process was performed. Subsequently, a window 18 for the contact hole 17 is provided by conventional photolithography and reactive ion etching to expose the first interconnections IiAl2 and 15.

The end point of this reactive ion etching process is approximately 10% further after the etching progresses to the top surface of the first wiring l2.
Although it was determined based on the etching speed that the first wiring 12, ]5 and the contact hole l7 were to be over-etched, a thin groove K was formed near the thickness direction of the first wiring 15 and the contact hole l7 was slightly misaligned. The state will be as follows.

This is shown in FIG. 3b. Furthermore, by depositing a silicon oxide film l9 with a thickness of approximately 0.3 μm by plasma CVD method, the narrow groove K is consolidated, and the side wall 20 of the window l8 and the silicon oxide layer are deposited. The surface of 16 is also coated, resulting in the cross-sectional structure shown in FIG. 3b. The silicon oxide film l9 that functions as such a filler is indicated as a filler in the claims.

Next, as shown in FIG. 3C, the entire surface is etched back by reactive ion etching in order to remove the silicon oxide film 19 at the bottom of the window l8 and expose the l-th regions gtz and l5. This amount was determined so that the silicon oxide film 19 would be over-etched by 10% after being etched. At this time, the silicon oxide 11119 within the window 18 has the same film thickness at all positions, so it is all over-etched by 10%.

This etching back process may be a reactive ion etching method, that is, an isotropic etching method rather than an anisotropic etching method. This is because when the depth and width of the narrow groove K are large, anisotropic etching is better, but when the depth and width of the narrow groove K are small, even isotropic etching is possible because it may affect the surroundings. In this way, a contact hole 17 is formed, in which a second wiring 2 made of AQ or an alloy is formed as shown in FIG.
1 by sputtering method to form the first wiring i2.
, 15.

As a result,! The multi-layer wiring of the 6-bit AD converter has been completed, and the post-processing process of silicon oxide and PSG (Phosph) has been completed.
or Silicate Glass) or a mixed layer of both.
ion) is completed as a semiconductor integrated circuit element through layer formation or other processes. In this way, although the embodiment targeting a 16-bit AD converter has a multi-layer wiring structure, it should be noted that it is naturally applicable to a single-layer wiring element as described above. [Effects of the Invention] As described above, in the method of the present invention, regardless of the installation location of the plurality of wirings constituting the first layer wiring, the plurality of wirings can be formed with a diameter equal to or smaller than the dimension of the contact hole.
The degree of integration is much improved compared to the conventional example, which was possible only when the wiring constituting the first layer wiring exists in the same plane.

For example, the chip size of a bibolar LSI [2 μm wiring rule] with 7000 wires is conventionally 4.3×4.
Six screens can be reduced to 3.4 x 3.8 m, which is a reduction in area of approximately 35%.

Furthermore, if the method of the present invention is not carried out, the yield will decrease due to breakage of the second layer wiring, and the difference in yield of bibolar LSI will be about 20%, so it must be said that it is an extremely effective method.

Furthermore, in a reliability test of a semiconductor element and a semiconductor integrated circuit (t4), which had no problem with single-layer wiring, a 50% life improvement effect was observed.

[Brief explanation of drawings]

Figures 1 and 2 a. 3b is a cross-sectional view showing the structure of a conventional contact hole, and FIGS. 3a and 3d are cross-sectional views of each step of the method of the present invention. 3.l
2, 15: first wiring, 4, l6: interlayer insulating layer, 5
% l7: contact hole, 6, l3: polycrystalline silicon, 7, l4: oxide film, 18: window, l9: silicon oxide film, 20: side hawk, 21: second wiring.

Claims (1)

[Claims] A step of installing a first wiring made of conductive metal on an insulating layer covering a semiconductor substrate, a step of covering this first wiring with another insulating layer, and a step of installing another wiring corresponding to this first wiring. a step of removing the insulating material layer to form a window that exposes the first wiring whose top surface is located on a different plane; and a step of covering the entire surface of the other insulating material layer including this window with a micro-groove filling material. , 1st
Formation of a wiring connection hole characterized by comprising an etching process that leaves a filler in a micro groove generated at a position away from the wiring, and a process of connecting a second wiring to a first wiring whose top surface is different. Method