JPS63237443A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce an area of an opening at a connecting hole by a method wherein the connecting hole which pierces a first wiring layer and a second wiring layer and reaches a diffusion layer on the surface of a semiconductor substrate is formed and a conductive metal is filled into said connecting hole so that said first wiring layer, said second wiring layer and said diffusion layer are connected electrically. CONSTITUTION:An oxide film 2, an insulating film 3, a first wiring layer 5, an interlayer insulating film 6 and a second wiring layer 8 are formed on a diffusion layer 1 on the surface of a semiconductor substrate by an ordinary method. The second wiring layer 8 is dry-etched, the interlayer insulating film 6 is etched anisotropically and the first wiring layer 5 is dry-etched by making use of a part other than the part to become a connecting hole 9 as a mask. Then, the insulating film 3 and the oxide film 2 are removed by an anisotropic etching method. In this way, the connecting hole 9 which pierces the first wiring layer 3 and the second wiring layer 8 and reaches the diffusion layer 1 on the surface of the semiconductor substrate is formed. A conduc tor such as amorphous silicon is deposited inside the connecting hole 9 by a low- pressure CVD method. Then, the conductor 15 is etched anisotropically; a conductive metal 11 each as tungsten is deposited inside the connecting hole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which the connection between a diffusion layer on a semiconductor surface and a metal wiring is improved.

[Prior Art] In a semiconductor device having a multilayer wiring structure in which a plurality of metal wiring layers are laminated, basic steps are achieved by electrically connecting each of the metal wiring layers to a diffusion layer on the surface of a semiconductor substrate. The conductor device is completed.

FIG. 2 is a sectional view of a conventional semiconductor device, and is a sectional view of a contact hole portion.

In the figure, reference numeral 1 denotes a diffusion layer on the surface of a semiconductor substrate, and an oxide film 2 is formed on one part of the diffusion layer 1 on the surface of the semiconductor substrate. An insulating film 3 made of, for example, PSG is formed on -L of the oxide film 2. A contact hole 4 is formed in the insulating film 3, and a first wiring 5 is connected to this contact hole 4. The first wiring 5 is formed of, for example, an aluminum wiring. For example, SiO□ is used for 1- of the first wiring.
, an interlayer insulating film 6 made of silicon nitride is formed. A through hole 7 is formed in the layered insulating film 6, and the second wiring 8 is electrically connected to the first wiring 5 through the through hole 7. That is, the second wiring 8 is directly connected to the contact hole 4.
Rather than being electrically connected to, via the first wiring 5,
It is electrically connected to the contact hole 4.

[Problems to be Solved by the Invention] Conventional wiring systems for semiconductor devices are configured as follows. That is, the diffusion layer 1 on the semiconductor surface and the second arrangement g
When connecting the second wiring 8 to the contact hole 4, the second wiring 8 is not directly electrically connected to the contact hole 4, but is connected to the first wiring 5 as a path.
It is electrically connected to the contact hole 4 via. Therefore, opening areas for both the contact hole 4 and the through hole 7 are required, which has been a problem in increasing the degree of integration of semiconductor devices. Further, in order to increase the degree of integration of a semiconductor device, it is necessary to efficiently arrange these (contact holes 4 and through holes 7), but there is also a problem that the design thereof is troublesome.

This invention was made to solve the above-mentioned problems, and it reduces the area required for connection hole openings, improves flexibility in wiring design, and enables highly integrated semiconductors. The purpose is to provide equipment.

[Means for Solving the Problems] The present invention relates to a semiconductor device having a multilayer wiring structure in which at least a first wiring layer and a second wiring layer are stacked on a semiconductor substrate with an insulating film interposed therebetween. Then, forming a connection hole extending across the first wiring layer and the second wiring layer to the diffusion layer on the surface of the semiconductor substrate, and forming a conductor layer on the inner wall of the connection hole, It is characterized in that the first wiring layer, the second wiring layer, and the diffusion layer are electrically connected.

[Function] By forming a connection hole extending across the first wiring layer and the second wiring layer to the diffusion layer on the surface of the semiconductor substrate, and forming a conductive layer on the inner wall of the connection hole, Since the first wiring, the second wiring layer, and the diffusion layer are electrically connected, the area of the contact hole opening required for connecting the metal wiring and the diffusion layer on the semiconductor surface can be reduced.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment, and is a cross-sectional view of the vicinity of a connection hole.

An oxide film 2 is formed on -L of the diffusion layer 1 on the surface of the semiconductor substrate, and an insulating film 3 is formed on the oxide film 2.

On the insulating film 3, there is a first layer made of aluminum, for example.
A wiring 5 is formed, and an interlayer insulating film 6 made of silicon oxide, silicon nitride, etc. is formed on the first wiring 5. A second wiring 8 is formed on the interlayer insulating film 6.

Then, a connection hole 9 is formed which extends across the first wiring 5 and the second wiring 8 to the diffusion layer 1 on the surface of the semiconductor substrate. A conductor layer 10, such as amorphous silicon, is formed on the inner wall of the connection hole 9, and the first
The wiring layer 5, the second wiring layer 8, and the diffusion layer 1 are electrically connected.

A conductive metal 11 such as tungsten is embedded in the connection hole 9 .

Next, a method for forming the connection hole 9 will be explained.

An oxide film 2. is formed on the diffusion layer 1 on the surface of the semiconductor substrate by a conventional method.
Insulating film 3. A first wiring 59 and an interlayer insulating film 6. A second wiring 8 is formed. Next, the second wiring layer 8 is first dry-etched while masking the portions other than the portions that will become the connection holes 9. Next, using the same mask, the interlayer insulating film 6 is anisotropically etched.

Thereafter, the first wiring 5 is dry etched using the same mask. Next, using the same mask, anisotropic etching is performed to remove the insulating film 3. Thereafter, anisotropic etching is performed using the same mask to remove the oxide film 2. As described above, the connection hole 9 is formed which extends across each of the first wiring 3 and the second wiring 8 to the diffusion layer 1 on the surface of the semiconductor substrate.

After the connection hole 9 is formed, a reduction JEC
A conductor such as amorphous silicon is deposited by the VD method. Next, the conductor 10 is anisotropically etched using a mask so as to leave the conductor layer 10 on the inner wall of the connection hole. Next, a conductive metal 11 such as tungsten is deposited inside the connection hole 9 .

If there are only 10 layers of conductive material such as amorphous silicon, the resistance will be high, so a conductive metal 11 such as tungsten having low resistance is deposited in the connection hole 9 to increase the conductivity.

In the above embodiment, the conductive metal 11 is placed inside the connection hole 9.
Although the present invention is not limited to this, the diffusion layer 1, the first wiring layer 5, and the second wiring 8 can be electrically connected even if the conductive metal 11 is not buried. Needless to say, they are connected.

In addition, in the embodiment, the connection hole 9 is connected to the diffusion layer l on the surface of the semiconductor substrate.
Although the case is shown in which it is formed perpendicularly, the present invention is not limited to this.

Furthermore, although the example shows the case where the conductor layer is formed of amorphous silicon, the present invention is not limited to this.

[Effects of the Invention] As explained above, according to the semiconductor device having the multilayer wiring structure according to the present invention, a contact hole extending across the first wiring layer and the second wiring layer to the diffusion layer on the surface of the semiconductor substrate is formed. By forming a conductive layer on the inner wall of the contact hole, the first wiring layer, the second wiring layer, and the diffusion layer are electrically connected, so that the diffusion between the metal wiring and the surface of the semiconductor substrate is prevented. The area of the connection hole opening required for connecting the layers can be reduced. This contributes to higher integration of semiconductor devices and improves flexibility in wiring design.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of a conventional semiconductor device. In the figure, 1 is a diffusion layer on the surface of a semiconductor substrate, 2 is an oxide film, 3 is an insulating film, 5 is a first wiring, 6 is an interlayer insulating film, 8 is a second wiring, 9 is a connection hole, and 10 is a conductor layer. , 11 are conductive metals. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) In a semiconductor device having a multilayer wiring structure in which at least a first wiring layer and a second wiring layer are stacked on a semiconductor substrate via an insulating film, the semiconductor A connection hole extending to the diffusion layer on the surface of the substrate is formed, and a conductive layer is formed on the inner wall of the connection hole to electrically connect the first wiring layer, the second wiring layer, and the diffusion layer. A semiconductor device characterized by: (2) The semiconductor device according to claim 1, wherein a conductive metal is embedded in the connection hole. (3) The semiconductor device according to claim 1 or 2, wherein the connection hole is formed perpendicularly to the surface of the semiconductor substrate.