JPS5890763A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5890763A JPS5890763A JP19109981A JP19109981A JPS5890763A JP S5890763 A JPS5890763 A JP S5890763A JP 19109981 A JP19109981 A JP 19109981A JP 19109981 A JP19109981 A JP 19109981A JP S5890763 A JPS5890763 A JP S5890763A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- layers
- semiconductor device
- layer
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 5
- 230000002787 reinforcement Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012779 reinforcing material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、多層構造をもつ半導体装置に係り、特に各
層の積層の仕方に関するものＣある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a multilayer structure, and particularly relates to a method of laminating each layer.
第１図は従来の多層構造をもつ半導体装置を示す断面図
Ｃあり、図において、（１１はシリコン（Ｓｌ）ウェハ
ーからなる半導体基板、（３ａ）〜（３ｄ）は配線、能
動系子が組み込まれ、半導体装置としての１つの機能を
有するシリコン（Ｓｌ）膜からなる半４体層、（２ａ）
〜（２ｆ）はこれら半導体層（２ａ３〜（２ｆ）の谷
ノー間に形成され４気的に絶縁する層間絶縁膜である。Figure 1 is a cross-sectional view C showing a conventional semiconductor device with a multilayer structure. (2a) A semi-quaternary layer made of silicon (Sl) film having one function as a semiconductor device.
-(2f) are interlayer insulating films formed between the valleys of these semiconductor layers (2a3-(2f)) to provide electrical insulation.
しかるに、このように構成され九多Ｊｍｉｌｌ造をもつ
半導体装置にあっては、各ｌ−間、つまり半導体層（３
ａ）〜（３ｄ）間の配線をしようとした場合、ノー間絶
縁［’）通して数カ所のスルーホールを開けるか、各層
間をワイヤーボンドするといった方法がとられ、各層間
の配線が複雑になるという欠点が生じた。However, in a semiconductor device configured in this way and having a Kuta Jmill structure, the semiconductor layer (3
When attempting to wire between a) and (3d), the method of making several through holes through the no insulation [') or wire bonding between each layer is taken, making the wiring between each layer complicated. A drawback arose.
この発明は、上記した点に鑑みてなされたものであり、
半導体層が複数積層された多層構造をもつ半導体装置に
おいて、半導体層の数層間あるいは全層を共通に接続す
る区域を形成して、各層間の記様の容易化、各層間に共
通する回路の形成、そして、半４体層が応力により、た
わみ、ひずみ等を生じることへの補強等の働きをなさし
めることを目的としている。This invention was made in view of the above points,
In a semiconductor device with a multilayer structure in which a plurality of semiconductor layers are laminated, a common connection area between several or all semiconductor layers is formed to facilitate the description between each layer and to connect common circuits between each layer. The purpose of this is to form a half-four body layer and to perform a reinforcing function to prevent deflection, distortion, etc. caused by stress.
以下にこの発明の一実施例を第２図に基づいて説明する
と、図において、（４）は半導体基板は）と半導体層（
３Ｃ）との間に介在され、半導体層（３ａ）および（３
ｂ）とが接続されるように形成された共通区域で、半導
体基板＋１１および半導体層（３ａ）〜（３ｃ）−４を
結ぶ４４が集中化されるとともに、半導体基板ｆｉ＋お
よび半４体層（３ａ）〜（３Ｃ）に共通する回路が？＃
成されているものである。An embodiment of the present invention will be described below based on FIG. 2. In the figure, (4) indicates the semiconductor substrate ( ) and the semiconductor layer (
3C), and the semiconductor layers (3a) and (3
44 connecting the semiconductor substrate +11 and the semiconductor layers (3a) to (3c)-4 is concentrated in the common area formed so as to connect the semiconductor substrate fi+ and the semi-quartet layer ( What circuit is common to 3a) to (3C)? #
It is something that has been done.
このように構成された多層構造をもつ半導体装直におい
ては、共通区域（４１が存在して、半導体基板（１１３
よび半導体層（３ａ）〜（３Ｃ）間を結ぶ配線が集中化
してυす、回路構成を量系化できるとともに、半都体邑
板（１）および半導体＋１（３ａ）〜（３Ｃ）に共通す
る回路を構成できることとなる。このような共通区域（
４）が成膜処理工程中に導入される、ひｒみ等の補強材
としての機能を果たすものである。In a semiconductor device having a multilayer structure constructed in this way, there is a common area (41) and a semiconductor substrate (113).
The wiring connecting the semiconductor layers (3a) to (3C) is centralized, and the circuit configuration can be scaled up. This means that it is possible to configure a circuit that Such common areas (
4) is introduced during the film forming process and serves as a reinforcing material for warps and the like.
なお、上記実施例では共通区域（４ンを半導体基板（１
１および半４体ＰｆＡ（３ａ） 〜（３ｃ）を接続する
ものとしたが、半導体７Ｉｌｌ（３ａ）〜（３ｆ）全ノ
ーを接続したものでもよく、共通区域１４＋の形成する
位置は、半導体層（３ａ）〜（３ｆ）の１１４１４でも
、その中央であっても艮いものＣある。また、共通区域
（４）の形状、大きさも制限されるものではない。さら
に、上記実施例では半導体層（３ａ）〜（３ｆ）をシリ
コンとしたが、ガリウム・ヒｐｇ ’（ＧａＡｓ）等で
あってもよいものである。Note that in the above embodiment, the common area (4 areas) is replaced by the semiconductor substrate (1 area).
Although the semiconductors 7Ill (3a) to (3f) may all be connected, the common area 14+ is formed at the position where the semiconductor layer 14+ is formed. Even in 11414 of (3a) to (3f), there is a strange C even in the center. Further, the shape and size of the common area (4) are not limited either. Furthermore, although the semiconductor layers (3a) to (3f) are made of silicon in the above embodiment, they may be made of gallium hippg' (GaAs) or the like.
この発明は以上に述べたように、半導体層が値数積層さ
れた多層構造をもつ半導体装置において半導体層の数ノ
ー間あ名いは全Ｆ−間を接続する共通区域を形成したの
で、各ノー間の１＆ｌ！線が聞梁化されるとともに、成
膜処理工程中に導入される、ひｒみの補強材としての役
割を果すという効果がある。As described above, in a semiconductor device having a multilayer structure in which a number of semiconductor layers are stacked, the present invention forms a common area that connects the number of semiconductor layers, also known as all F-. 1&l between no! This has the effect that the wire is made into a beam and also serves as a reinforcing material for the sag introduced during the film forming process.
第１図は従来の多層構造をもつ半導体装置の醒面図、第
２図はこの発明の一実施例を承す多層構造をもつ半導体
装置の断面図である。
図ｉこおいて、（３ａ） 〜（３ｄ）は半導体層、（２
ａ） 〜（２ｆ）はＷＩ間絶縁膜、（４１は共通区域で
ある。
代理人 Ｊｌ、野 僅 −
第１図
第２図
手続補正書（自発）
特許庁長官殿
１、事件の表示 特願昭６６−１９１０９９号２
、発明の名称
半導体装置
３、補正をする者
（１）
５、 補止の対象
図面
６、 補正の内容
図面中、第２図において添付複写図面に未配して示す如
く符号「４」およびその引出縁を追記する。
以上
第１図
第２図FIG. 1 is a top view of a conventional semiconductor device with a multilayer structure, and FIG. 2 is a sectional view of a semiconductor device with a multilayer structure according to an embodiment of the present invention. In Figure i, (3a) to (3d) are semiconductor layers, (2
a) ~ (2f) are the insulating films between WIs, (41 is the common area. Agent Jl, No. 1 - Figure 1 Figure 2 Procedural amendment (voluntary) Mr. Commissioner of the Japan Patent Office 1, Indication of case Patent application 1986-191099 No. 2
, Title of the invention: Semiconductor device 3, Person making the amendment (1) 5. Drawing subject to amendment 6, Contents of the amendment In the drawing, the symbol "4" and its numerals are not placed in the attached copy drawing in Fig. 2. Add the drawer edge. Above Figure 1 Figure 2
Claims (1)
＃膜を介して複数積層された多層構造をもつ半導体ａｍ
において、上記率・φ体層の数層間または全一間を償ｄ
する共通区域を形成したことを特徴とする半導体装置。A semiconductor am semiconductor with a multilayer structure in which a plurality of semi-quaternary layers in which wiring, active elements, etc. are incorporated are laminated via l-interval films.
In this case, the above-mentioned ratio/φ body layer may be compensated for between several layers or all the layers.
What is claimed is: 1. A semiconductor device characterized in that a common area is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19109981A JPS5890763A (en) | 1981-11-25 | 1981-11-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19109981A JPS5890763A (en) | 1981-11-25 | 1981-11-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5890763A true JPS5890763A (en) | 1983-05-30 |
Family
ID=16268832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19109981A Pending JPS5890763A (en) | 1981-11-25 | 1981-11-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5890763A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63237443A (en) * | 1987-03-25 | 1988-10-03 | Mitsubishi Electric Corp | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56144530A (en) * | 1980-04-10 | 1981-11-10 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5853822A (en) * | 1981-09-25 | 1983-03-30 | Toshiba Corp | Laminated semiconductor device |
| JPS5856454A (en) * | 1981-09-30 | 1983-04-04 | Toshiba Corp | Semiconductor device |
-
1981
- 1981-11-25 JP JP19109981A patent/JPS5890763A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56144530A (en) * | 1980-04-10 | 1981-11-10 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5853822A (en) * | 1981-09-25 | 1983-03-30 | Toshiba Corp | Laminated semiconductor device |
| JPS5856454A (en) * | 1981-09-30 | 1983-04-04 | Toshiba Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63237443A (en) * | 1987-03-25 | 1988-10-03 | Mitsubishi Electric Corp | Semiconductor device |
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