JPS63216361A - Multilayer interconnection structure - Google Patents

Multilayer interconnection structure

Info

Publication number
JPS63216361A
JPS63216361A JP5061687A JP5061687A JPS63216361A JP S63216361 A JPS63216361 A JP S63216361A JP 5061687 A JP5061687 A JP 5061687A JP 5061687 A JP5061687 A JP 5061687A JP S63216361 A JPS63216361 A JP S63216361A
Authority
JP
Japan
Prior art keywords
wiring
hole
layers
layer
connection body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5061687A
Other languages
Japanese (ja)
Inventor
Masato Tanaka
正人 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5061687A priority Critical patent/JPS63216361A/en
Publication of JPS63216361A publication Critical patent/JPS63216361A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To shorten a production process by a method wherein the connection between wiring layers is executed by using a wiring connection body coated on a through hole which has been made by exposing the side of the wring layers so that the through hole at a multilayer interconnection can be made by only one process. CONSTITUTION:The connection between wiring layers 3a-3c at a laminated structure formed by piling up insulating films 4a-4c where the wiring layers 3a-3c are buried, on a semiconductor substrate 1 is executed by using a wiring connection body 7 coated on a through hole 6 which has been made by exposing the side of the wiring layers 3a-3c to be connected. For example, the through hole 6 is made at the insulating films 4a-4c by an anisotropic dry etching method or the like so that the side of the wiring parts 3a-3c at the first to the third layers can be exposed. A Ti layer 7a and a Pt layer 7b are formed one after another as the wiring connection body 7 on the inside wall of the through hole 6 by a sputtering method; furthermore, an Au layer 7c is formed on the Pt layer 7b by a plating method; the wiring parts 3a-3c at the first to the third layers are connected electrically to one anther by using the wiring connection body 7.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の多層配線構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a multilayer wiring structure of a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、多層配線を有する半導体装置では、例えばn層の
金属配線を形成する場合、n−1回の各金属配線間の電
気的接続窓の形成、つまりスルーホール開孔を必要とし
ていた。例えば、第3図のように3層配線3a、3b、
3cを形成する場合は、配線3a、3b間のスルーホー
ル5(1)と配線3b、3c間のスルーホール5(2)
とを絶縁膜4a、4bに開孔する必要があった。
Conventionally, in a semiconductor device having multilayer wiring, when forming, for example, n-layer metal wiring, it has been necessary to form an electrical connection window between each metal wiring (n-1 times), that is, to open a through hole. For example, as shown in FIG. 3, three-layer wiring 3a, 3b,
3c, the through hole 5 (1) between the wirings 3a and 3b and the through hole 5 (2) between the wirings 3b and 3c.
It was necessary to open holes in the insulating films 4a and 4b.

上述した従来の多層配線構造では、上層配線がスルーホ
ールのエツジで断線を起こしやすいため、スルーホール
+r−パー状にエツチングする必要があシ、さらにスル
ーホール下部は下層配線をはみ出ることなく、またスル
ーホール上部は上層配線に完全に覆われている必要があ
る。このため設計上及び製造上多大の制約を受ける。
In the above-mentioned conventional multilayer wiring structure, the upper layer wiring is prone to disconnection at the edge of the through hole, so it is necessary to etch the through hole + r - par shape, and the lower part of the through hole does not protrude from the lower layer wiring. The upper part of the through hole must be completely covered by the upper layer wiring. This imposes many restrictions on design and manufacturing.

また第1層目配線からn層目配線への接続は、前記した
様にn−1ケ所のスルーホールを通して行なわれるため
、多層化するほどスルーホール部の接続不良をひきおこ
しやすいという欠点がある。
Furthermore, since the connection from the first layer wiring to the nth layer wiring is made through the (n-1) through holes as described above, there is a drawback that the more layers there are, the more likely connection failures will occur at the through hole portions.

本発明の目的は、上記の欠点を除去した、新規な配線接
続を有する多層配線構造を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer wiring structure with novel wiring connections that eliminates the above-mentioned drawbacks.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の多層配線構造は、配線層が埋設された絶縁膜を
半導体基板上に重ねて積層したもので、配線層間の接続
が、接続すべき配線層の側面を露出して開孔したスルー
ホールに被着された、配線接続体によりなされるように
している。
The multilayer wiring structure of the present invention is a structure in which insulating films in which wiring layers are embedded are stacked on top of a semiconductor substrate, and connections between wiring layers are made through through holes that expose the sides of the wiring layers to be connected. This is done by a wiring connection body attached to the.

〔実施例〕〔Example〕

以下、図面を参照して、本発明の実施例につき説明する
。第1図は、一実施例として、3層のアルミニューム配
線をなした場合の、断面図である。シリコン基板1上の
シリコン酸化膜2上に、第1層目配線3aとそれをおお
う絶縁膜4a、第2層目配線36とそれをおおう絶縁膜
4bと、第3層目配線3Cとそれをおおう絶縁j14c
とが順次積層されて形成される。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a case where three layers of aluminum wiring are formed as an example. On the silicon oxide film 2 on the silicon substrate 1, there are formed a first layer wiring 3a and an insulating film 4a covering it, a second layer wiring 36 and an insulating film 4b covering it, and a third layer wiring 3C and an insulating film 4b covering it. cover insulation j14c
are formed by sequentially stacking them.

次に第1層目配置3al第2層目配+1!3b。Next, first layer arrangement 3al second layer scale +1!3b.

第3層目配線3Cの側面が露出するように、絶縁膜4a
、絶縁膜4b、および絶縁膜4Cに異方性ドライエツチ
ング等でスルーホール6t−開孔し、配線接続体7とし
てスパッタによって順に、スルーホール6の内壁にTi
層7aPt膚7bを形成し、さらにメッキ法によってP
t層7b上にAu層7cを形成する。 配線接続体7に
よって、第1層目配線3a、第2層目配線3bおよび第
3層目配線3Cが互いに電気的に接続てれる。
The insulating film 4a is formed so that the side surface of the third layer wiring 3C is exposed.
, the insulating film 4b, and the insulating film 4C by anisotropic dry etching or the like, and then Ti is deposited on the inner wall of the through hole 6 as a wiring connection body 7 by sputtering.
A layer 7a of Pt layer 7b is formed, and further P is coated by a plating method.
An Au layer 7c is formed on the t-layer 7b. The first layer wiring 3a, the second layer wiring 3b, and the third layer wiring 3C are electrically connected to each other by the wiring connection body 7.

配線間の接続は、従来例のように、すべての配線層を介
して連結する必要はなく、直接に接続すべき配線層をス
ルーホール全弁して接続できる。第2図は、第1層目配
線3aを直接に第3層目配線3Cと配線接続体9f、介
して接続した例を示すものである。このように位置をか
えたスルーホール8によって接続される配線を変更でき
る。
Connections between wirings do not need to be made through all wiring layers as in the conventional example, and wiring layers to be directly connected can be connected through all through holes. FIG. 2 shows an example in which the first layer wiring 3a is directly connected to the third layer wiring 3C via a wiring connection body 9f. The wiring connected by the through hole 8 whose position is changed in this way can be changed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、全ての配線層形成後にス
ルーホールを形成するため、スルーホール形成工程は幾
層配線でも1回のみで行なうことができ、製造工程を短
縮できる効果、およびスルーホールの形成が各配線の側
面の一部が露出する様に行なうだけで良いので従来の様
に配線とスルーホールの設計マージンを考慮する必要が
無くなり、設計が容易になる効果がある。この他、本発
明による効果として、以下に示すように信頼度の向上が
期待できる。
As explained above, in the present invention, the through holes are formed after all the wiring layers are formed, so the through hole forming process can be performed only once no matter how many wiring layers there are, and the manufacturing process can be shortened. Since it is only necessary to form the wiring so that a part of the side surface of each wiring is exposed, there is no need to consider the design margin of the wiring and through-holes as in the conventional case, which has the effect of simplifying the design. In addition, as an effect of the present invention, an improvement in reliability can be expected as shown below.

(イ)各層の配線間の接続は、1つのスルーホールを通
して行なわれるので、スルーホール部の接続不良の発生
する確立が非常に少なくなる。
(a) Since the connections between the wirings in each layer are made through one through hole, the probability that a connection failure will occur at the through hole portion is extremely reduced.

(ロ) スルーホール上に配線を形成しないので、上層
配線のスルーホール部での断線の恐れが無くなる。
(b) Since wiring is not formed on the through-hole, there is no risk of disconnection at the through-hole portion of the upper layer wiring.

また、ゲートアレーのように配線接続が多様に要求され
る半導体装置に対し、本発明は、全ての配線を形成した
後に任意の場所に任意の配線を接続するスルーホールを
開孔できるので、非常に工期を短くすることができる。
Furthermore, for semiconductor devices such as gate arrays that require a variety of wiring connections, the present invention allows for the creation of through-holes to connect any wiring at any location after forming all the wiring. construction period can be shortened.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明の実施例の断面図、第3図は従
来例の断面図である。 1・・・シリコン基板、2・・・シリコン酸化膜、3a
、3b、3c・・・(アルミニューム)配線、4 a 
、 4 b 、 4 c −・・絶縁膜、6.8・・・
スルーホール、 7.9・・・配線接続体。
1 and 2 are cross-sectional views of an embodiment of the present invention, and FIG. 3 is a cross-sectional view of a conventional example. 1... Silicon substrate, 2... Silicon oxide film, 3a
, 3b, 3c... (aluminum) wiring, 4a
, 4 b, 4 c ---insulating film, 6.8...
Through hole, 7.9... Wiring connection body.

Claims (1)

【特許請求の範囲】[Claims] 配線層が埋設された絶縁膜を半導体基板上に重ねて形成
した積層構造を有し、配線層間の接続が、接続すべき配
線層の側面を露出して開孔したスルーホールに被着され
た、配線接続体によりなされることを特徴とする半導体
装置の多層配線構造。
It has a laminated structure in which an insulating film with embedded wiring layers is layered on a semiconductor substrate, and connections between wiring layers are made through through holes that expose the sides of the wiring layers to be connected. A multilayer wiring structure for a semiconductor device, characterized in that it is formed by a wiring connection body.
JP5061687A 1987-03-04 1987-03-04 Multilayer interconnection structure Pending JPS63216361A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5061687A JPS63216361A (en) 1987-03-04 1987-03-04 Multilayer interconnection structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5061687A JPS63216361A (en) 1987-03-04 1987-03-04 Multilayer interconnection structure

Publications (1)

Publication Number Publication Date
JPS63216361A true JPS63216361A (en) 1988-09-08

Family

ID=12863907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5061687A Pending JPS63216361A (en) 1987-03-04 1987-03-04 Multilayer interconnection structure

Country Status (1)

Country Link
JP (1) JPS63216361A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH033242A (en) * 1989-05-30 1991-01-09 Sony Corp Formation of multilayer interconnection
US5571751A (en) * 1994-05-09 1996-11-05 National Semiconductor Corporation Interconnect structures for integrated circuits
JP2008277798A (en) * 2007-04-06 2008-11-13 Semiconductor Energy Lab Co Ltd Semiconductor device, and manufacturing method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58215055A (en) * 1982-06-08 1983-12-14 Nec Corp Semiconductor integrated circuit device
JPS59171140A (en) * 1983-03-17 1984-09-27 Nec Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58215055A (en) * 1982-06-08 1983-12-14 Nec Corp Semiconductor integrated circuit device
JPS59171140A (en) * 1983-03-17 1984-09-27 Nec Corp Semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH033242A (en) * 1989-05-30 1991-01-09 Sony Corp Formation of multilayer interconnection
US5571751A (en) * 1994-05-09 1996-11-05 National Semiconductor Corporation Interconnect structures for integrated circuits
US5666007A (en) * 1994-05-09 1997-09-09 National Semiconductor Corporation Interconnect structures for integrated circuits
US5691572A (en) * 1994-05-09 1997-11-25 National Semiconductor Corporation Interconnect structures for integrated circuits
US5798299A (en) * 1994-05-09 1998-08-25 National Semiconductor Corporation Interconnect structures for integrated circuits
EP0955672A3 (en) * 1994-05-09 2000-01-12 National Semiconductor Corporation Interconnect structures for integrated circuits
JP2008277798A (en) * 2007-04-06 2008-11-13 Semiconductor Energy Lab Co Ltd Semiconductor device, and manufacturing method thereof

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