JPS62154758A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a multilayer interconnection structure, which can miniaturize the size of an element without consideration of a room for position alignment between a first interconnection layer and the through hole of an interlayer film, by conducting a second interconnection layer and the first interconnection layer in an opening part, which is formed in an interlayer insulating film, wherein the first interconnection layer is embedded and the upper surface part and the periphery of a part of the first interconnection layer are exposed. CONSTITUTION:A first interconnection layer 7 is formed on one main surface of a semiconductor substrate and embedded in an interlayer insulating film 8, which is thicker than the layer 7. An opening part 11 is formed in the interlayer insulating film 8. The part 11 has a depth so that the upper surface part of a part of the first interconnection layer 7 is exposed and has a flat bottom surface, which is expanded to the periphery of the upper surface part. A second interconnection layer 10 is conducted to the first interconnection layer 7 in this opening part 11. For example, on a surface insulating part 5, which is formed on the one main surface of the semiconductor substrate 1, ohmic contact is provided to a diffused layer 4 trough a contact hole 6. After the first interconnection layer 7 is formed, the organic insulating film 8 is thickly formed so as to bury the layer 7. A part of the organic film is etched, and the upper part of a part of the first Al interconnection layer 7 is exposed. The opening part 11, which is wider than said upper surface part, is formed. The second Al interconnection layer 10, which is connected to the first Al interconnection layer 7, is formed in the opening part 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a wiring (electrode) structure and a wiring fM (electrode) formation technique for a semiconductor device having multilayer wiring.

[Conventional technology]

The conditions required for an insulating film formed between layers in a multilayer wiring structure are the completeness of electrical insulation between wirings and the surface shape (flatness) for forming a surface wiring layer.

As techniques for planarizing interlayer films, there are two methods: one using an organic insulating film such as a surface layer, and the other using an inorganic insulating film.

Published by Kogyo Taishokukai Co., Ltd.'Electronic Materials March 1982 p38
- Multilayer wiring technology for 4Or ultra-LSI and its application to devices'' The former has poor flatness of the top surface of the insulating film, while the latter has poor heat resistance and chemical stability. The present invention is directed to the latter case, that is, the case where an organic insulating film is used.

[Problem that the invention seeks to solve]

For example, in the case of a circuit such as I2L that is formed with intricately intricate fine wiring, the alignment and dimensions of the through hole when a through hole is made in the insulating film between the electrode extraction parts that are close to each other. The study revealed that this is a problem.

FIGS. 11 to 14 are process sectional views showing an example of a conventional method for forming two-layer wiring in I2L.

In FIG. 11, 1 is an n-type Si substrate, 2 is a p-diffusion layer serving as an injector, 3 is a base p-diffusion layer of an inverse transistor, and 4 is a collector n+ layer. 5 is a thermal oxide film (Sin, film) formed on the substrate surface. This SiOt film 5 is photo-etched to form a contact hole 6.

Next, a 1 μm thick layer is deposited on the entire surface of A, 6 by vapor deposition or the like, and photoetched to form a first layer A4 wiring (electrode) 7. A polyimide resin is formed as an interlayer film on the entire surface by a coating method or the like, and a polyimide resin film 8 with a flat surface is formed to a thickness of about 2.2 μm, and a part of the first layer wiring is formed by photoetching. A through hole 9 is opened.

(FIG. 12) Thereafter, A, . (FIG. 13) When carrying out the above method, as shown in FIG. 14, the first layer A-! 3. A margin for positioning the etching mask pattern between the three-way forest 7 and the through hole 9 is required.

Also, conduction cannot be achieved unless the dimensions of the through hole 9 are made larger than the dimensions of the contact hole 60. This is especially true when it comes to fine processing. In this case, it is necessary to provide a sufficient distance between adjacent electrodes (contact holes), and the dimensions of the element must be increased considering the alignment margin and the diameter of the contact holes, which may reduce the degree of integration. It turned out to be a big deal.

The present invention has been made in order to overcome the above-mentioned problems, and it is possible to create a multilayer wiring structure that allows miniaturization of element dimensions without considering the alignment margin between the first layer wiring and the through hole of the interlayer film. The purpose is to provide dimensions that can realize this.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief summary of typical inventions disclosed in this application is as follows.

That is, the first layer and the second RI are formed on one main surface of the semiconductor substrate.
In forming multi-layered All wiring layer I via an interlayer film, after forming the first layer A and 6 wiring, a thick organic insulating film is formed to bury it, and a part of this organic insulating film is etched. Then, a part of the upper surface of the first layer A-e wiring connected to the first layer A4 wiring is exposed, and an opening wider than the upper surface is formed, and the first layer insulation is formed within this opening. This is to form a first layer A4 wiring connected to the film mK.

[For production]

According to the above-mentioned means, there is no need to consider the mask alignment margin between the first layer A, 6 wiring and the opening of the interlayer insulating film (therefore, the degree of integration is improved without increasing the device area) This achieves the above objectives.

[Example 1] Figure 1 shows a typical example of the present invention.
1 is a cross-sectional view of a semiconductor device having layer wiring.

Reference numeral 1 denotes a semiconductor substrate made of, for example, n(p) type Si. 4
is a part of a semiconductor element and is made of, for example, a p(n) type diffusion layer. 5 is a surface insulating film formed by thermal oxidation 5i02, PSG (phosphorus silicate glass), or the like. 7 is a first layer A4 wiring (electrode) that makes ohmic contact with the p(n) type diffusion layer 4 of the substrate through the contact hole 6. A first layer insulating film 8 is made of polyimide resin, for example, and is formed to be sufficiently thicker than K so as to embed the electrode 7 therein.

Reference numeral 11 denotes an opening, which is formed on the surface of the first layer insulating film;
The first I flaw A-e has a depth that exposes the upper surface of the wiring 7 (a depth that does not reach the insulating film 5), and has a flat surface that spreads to the periphery. Reference numeral 10 denotes a second layer A2 wiring, which is formed within the opening 11 so as to be connected to the first layer A2 wiring.

FIG. 2 is a plan view showing each pattern of the two-layer wiring structure in FIG. 1.

As shown in the figure, according to the present invention, there is no need to align the opening (through hole) 11 in the insulating film 8 with respect to the first layer A2 wiring 7, and compared to the first layer A2 wiring 7. All you have to do is make it wide enough.

Since the second layer A4 wiring 10 only needs to overlap the first layer A2 wiring, there is no need to consider the opening (it can be made small in size).

[Embodiment 2] FIGS. 3 to 7 show another embodiment of the present invention, and are process sectional views of a two-layer pattern forming process.

Each step will be explained in detail below.

(1) A diffusion layer 4 is prepared on the surface of a Si substrate 1 by a well-known selective diffusion process, and a contact hole 6 is formed by performing contact photoetching on the oxide film 5 used as a diffusion mask. (Figure 3) +2) A77 layer (sputtered), first layer A2 wiring (electrode) 7 that makes ohmic contact with the diffusion layer through the contact hole by photoetching
form.

(FIG. 4) (3) Polyimide resin 8 is formed as a first layer insulating film on the entire surface. This polyimide resin is produced by applying a prepolymer solution of polyimide resin obtained by reacting aromatic diamine and aromatic tetracarboxylic anhydride with a spinner, evaporating the solvent component, and heat-treating at 200-300°C. It is polymerized and cured. This first interlayer insulating film 8 is sufficiently thick (approximately 2.2 μm) so as to embed the 11+4th wiring (1 μm thick), and has a flat surface with no steps.

(FIG. 5) (4) Openings 11 are made by RIE photoetching or the like in the portions that should be electrically connected to the first layer A2 wiring. This opening 11 has a depth that exposes the upper surface of the first layer A2 pattern 7, and is opened so that it is wider than that. (@Figure 6) (5) A A wiring 10 is formed. A part of this second layer A) wiring is formed in the opening 1.
1 and connected to the first layer A2 wiring 7. (FIG. 7) According to the present invention, there is no need for special alignment when opening the opening 11 in the insulating film 8 with respect to the first layer A2 wiring 7, as in the case described in the previous embodiment, and there is no need for photo-etching. becomes easier. This is also advantageous in forming the first layer A2 wiring.

[Embodiment 3] FIGS. 8 and 9 are cross-sectional views showing an embodiment in which the present invention is applied to a two-layer wiring of a semiconductor device having l2Lx.

In this figure, the same reference numbers are used for parts common to the constituent parts explained in FIGS. 11 to 13 above.

As shown in FIG. 8, diffusion layers 2, 3.4 such as an injector, base, and collector are formed on the surface of the substrate 1, and the first layer A
On top of the 4 electrodes 7 formed, there is a polyimide L'! ! Z xM
n'2 as +"-fp 2, #A RMm k'
4 jiff Q i Iu do m, t-m
tr■ Opening 13 for extracting the collector electrode in a part of the insulating film
Open. This opening 13 is large in width and has a depth and dimensions such that a plurality of collector electrodes are exposed simultaneously.

After this, as shown in FIG. 9, the first layer A4 is connected to the first layer A2 wiring (collector electrode) exposed in the horizontally long opening.
Electrode 70 is formed.

FIG. 10 is a layout diagram of multilayer electrodes and openings corresponding to FIG. 9.

As described in this embodiment, according to the present invention, there is no need for alignment between the first layer A stone wiring and the opening, and therefore,
Through-holes can be freely formed from the collector of I''L, and at the same time, the degree of integration can be improved without increasing the element area of I2L.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples (although various changes can be made without departing from the gist of the invention). Needless to say.

For example, as shown in FIG. 15, a thick interlayer insulating film 8 is formed on the first layer Ap wiring 7, and an opening 11 for taking out the electrode to the second layer is formed, and at the same time, a bonding pad is formed. Another opening 14 may be formed at the portion where the opening 14 is located. 16 is a bonding wire.

Note that at the same time as forming the second layer A2 wiring 10, an upper layer A1 film 15 is formed on the bonding pad. This facilitates mask alignment layout, which is advantageous for on-chip circuit design.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, alignment between the first layer A2 wiring (vL pole) and the through-hole of the interlayer film becomes unnecessary, and the device area can be reduced.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a typical embodiment of the invention. FIG. 2 is a plan view corresponding to FIG. 1. 3 to 7 are process cross-sectional views showing one embodiment of the present invention. FIGS. 8 and 9 are partial process cross-sectional views showing other embodiments of the present invention. FIG. 10 is a plan view corresponding to FIG. 9. FIGS. 11 to 13 are process cross-sectional views showing an example of conventional IIL electrode formation. FIG. 14 is a plan view corresponding to FIG. 13. FIG. 15 is a sectional view of one application example of the present invention. 1... i-plate (Si), 6... contact hole, 7...
- First layer A2 wiring, 8... Interlayer insulating film (polyimide resin), 10... Second layer A2 wiring, 11... Opening.

Claims (1)

[Claims] 1. A semiconductor device in which first and second layer wiring is formed in multiple layers on one main surface of a semiconductor substrate with an interlayer insulating film interposed therebetween, wherein the first layer wiring is The opening is buried in a thick interlayer insulating film and has a depth that exposes the upper surface of a portion of the first layer wiring, and has a flat bottom extending around the upper surface. A semiconductor device characterized in that a second layer wiring is electrically connected to a first layer wiring within an opening. 2. A step of forming a contact hole in the insulating film on one main surface of the semiconductor substrate and forming a first layer wiring that connects to the surface area of the substrate through the contact hole, and forming an interlayer insulating film so as to bury the first layer wiring. a step of etching a part of the interlayer insulating film to expose the upper surface of the first layer wiring and making an opening at a depth that does not reach the substrate surface insulating film; A method for manufacturing a semiconductor device, comprising the step of forming a second layer wiring for connection. 3. The method of manufacturing a semiconductor device according to claim 2, wherein a part of the through hole is a common wide hole through which a plurality of adjacent first layer wirings are simultaneously exposed.