JPS6329549A - Multilayer interconnection structure - Google Patents

Abstract

PURPOSE:To make the electric connection of a lower interconnection having a large area and an upper interconnection excellent, by providing a plurality of pedestals independently and uprightly on the lower interconnection having the large area, forming an interlayer insulating film, on which the upper end parts of the pedestals are exposed, by etching.back thereon, and forming the upper interconnection thereon. CONSTITUTION:A plurality of pedestals 5 having minute patterns are independently provided uprightly on a lower aluminum interconnection 3, which has a wide line width of 5 mum or more. The total area of the pedestals is made to be a specified area. An interlayer insulating film 6 is formed thereon by a bias sputtering method. At this time, the thickness of the interlayer insulating film 6 is made to have value so that the pedestals 5 are completely coated. Thereafter, the interlayer insulating film 6 undergoes etching-back treatment. Then the upper end parts of all the pedestals 5 are exposed on the interlayer insulating film 6 approximately equally. Then an upper aluminum interconnection 7 is formed on the interlayer insulating film 6 and positively connected to all the pedestals 5. As a result, the interconnection is connected to the aluminum interconnection 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer wiring structure, and more particularly to a multilayer wiring structure in which upper and lower wirings are connected using a pedestal.

[Conventional technology]

Generally, in a multilayer wiring structure, it is necessary to electrically connect the lower layer wiring and the upper layer wiring through a through hole formed in the glabella insulating film. Conventionally, this type of through-hole is created by creating a fine hole in the interlayer insulating film using a selective etching method, but if this hole is smaller than a predetermined size, it becomes impossible to fill the hole with the upper wiring material. Therefore, electrical connection becomes impossible.

Therefore, the size of the hole must be larger than a predetermined value, which becomes an obstacle to miniaturization of semiconductor devices.

For this reason, in recent years, a connection structure using a pedestal has been proposed and is considered to be effective in improving the miniaturization of semiconductor devices.

The connection structure using this pedestal is as shown in Figure 3.
A pedestal 14 is provided upright on the lower wiring 13 provided on the insulating film 12 of the substrate 11, a thick interlayer insulating film 15 is formed on this, and the cold color border film 15 is etched and hacked to form the pedestal. The upper end portion of 14 is exposed on interlayer insulating film 15 .

Then, by forming the upper wiring 16 in a desired pattern and connecting it to the upper pedestal 14, the upper and lower wires 13 and 15 can be electrically connected to each other via the pedestal 14.

[Problem that the invention seeks to solve]

When constructing a connection structure using this pedestal, a bias sputtering method is usually used to form the interlayer insulating film 15, but when the area of the lower wiring 13 is large, as shown by the imaginary line in FIG. Thus, the interlayer insulating film 15 is formed thicker on the lower wiring 13 than on other parts. Therefore, if etching hacking is performed in this state, the interlayer insulating film 15 will be formed on the lower wiring 13, which has a large area, as shown by the solid line in the figure.
As a result, a portion of the contact area with the upper wiring 16 is reduced, leading to an increase in connection resistance and deterioration of device characteristics. Further, in some cases, etching back may not be sufficient, resulting in poor connection.

An object of the present invention is to provide a multilayer wiring structure in which a large-area lower wiring can be electrically connected to an upper wiring.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, a plurality of pedestals are independently erected on a lower wiring having a large area, an interlayer insulating film is formed on this by etching back to expose the upper end of the pedestal, and an upper wiring is formed on top of this. It is said that

[Effect]

According to this configuration, since the interlayer insulating film is formed on the plurality of pedestals, even when forming the glabella insulating film by bias sputtering, the film thickness in this part does not become large, and the glabella insulating film is formed on the plurality of pedestals. By etching back the film, the top surface of the pedestal can be reliably exposed and connections with the upper wiring can be made with high reliability.

[Example: FIGS. 1(a) and 1(b) are a plan view and a cross-sectional view of an embodiment of the present invention, and show an embodiment in which the present invention is applied to a two-layer wiring structure.

In FIG. 1, an aluminum wiring 3 as a lower wiring is formed in a required pattern on an insulating film 2 on the surface of a silicon substrate l, and a thin metal film 4 of molybdenum or the like is coated on the surface of this aluminum wiring 3. It is formed in one piece. A pedestal 5, which is made of an aluminum film of a required thickness and formed into a fine pattern, is erected on the aluminum wiring 3.

In this case, a plurality of finely patterned pedestals 5 are independently erected on the wide aluminum wiring 3 with a line width of 5 μm or more, and the total area of these pedestals 5 is set to be the required area. are doing.

Then, an interlayer insulating film 6 is formed to cover the aluminum wiring 3 and these pedestals 5, and the upper end of the pedestal 5 is exposed above the interlayer insulating film 6. Further, an aluminum wiring 7 as an upper wiring of a required pattern is formed on the interlayer insulating film 6 and connected to the pedestal 5, and the upper and lower aluminum wirings 3.7 are electrically connected to each other via the pedestal 5. Connected.

FIG. 2 is a cross-sectional view showing steps in manufacturing the wiring structure.

That is, after forming a molybdenum film 4 on the aluminum wiring 3 as shown in FIG. 5 in an upright state. At this time, the pedestals 5 are constructed to have a small area, and a plurality of pedestals 5 are arranged independently.

Next, an interlayer insulating film 6 is formed thereon by bias sputtering. At this time, the glabella insulating film 6 is attached to the pedestal 5.
Form to a thickness so that it is completely covered. At this time, even in the aluminum wiring 3 with a large line width, the pedestal 5
has a structure in which multiple micro-patterned pieces are installed vertically, so the aluminum The glabellar insulating film 6 formed on a3 is not partially increased in thickness, but is formed to have substantially the same thickness as other parts.

Therefore, if the glabellar insulating film 6 is etched back after this, the glabellar insulating film 6 will be approximately uniform as shown in FIG.
The thickness is reduced so that the upper ends of all the pedestals 5 are exposed on the interlayer insulating film 6 substantially equally.

As a result, if the aluminum wiring 7 is formed on the interlayer insulating film 6, the aluminum wiring A7 will cover all the pedestals 5.
As a result, it is connected to the aluminum wiring 3.

According to this configuration, when the interlayer insulating film 6 is etched back, the glabellar insulating film 6 is not left on the pedestal 5, so the upper end of the pedestal 5 can be reliably connected to the upper aluminum wiring 7. The upper and lower aluminum wiring lines 3 and 7 can be electrically connected at a high (8 inclination).

Incidentally, since the total cross-sectional area of the plurality of pedestals 5 is set to the area necessary for connection, electric abrasive resistance is not increased.

According to the embodiment described above, the following effects can be obtained.

(1) Since a plurality of pedestals are independently erected on the lower wiring with a large area, and an interlayer insulating film is formed on this, and an upper wiring is formed, the interlayer 11Th '4 & film is formed using bias sputtering. Even when the pedestal is formed, the film thickness at this portion does not become large, and the upper surface of the pedestal can be reliably exposed by etching back the interlayer insulating film, and connection with the upper wiring can be made with high reliability.

(2) Since the upper and lower wirings are electrically connected using the pedestal, the through holes can be made smaller compared to a structure in which through holes are opened in the glabella insulating film for connection.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples (although it is possible to make various changes without departing from the gist of the invention). Needless to say, for example, the number of pedestals may be different from that shown in the drawings, and the planar arrangement thereof is not limited to that of the embodiment.

In the above explanation, the invention made by the present inventor is mainly applied to the field of application which is the background of the invention, which is the case where the first layer and the 2N wiring of a semiconductor device are electrically connected, but the invention is limited to this. However, the present invention can be similarly applied to the case where electrical connections are made between wirings in the second layer or higher.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, a plurality of pedestals are independently erected on a lower wiring having a large area, an interlayer insulating film is formed on this by etching back to expose the upper end of the pedestal, and an upper wiring is formed on top of this. Therefore, the interlayer insulating film is formed on multiple pedestals, and even when the interlayer insulating film is formed by bias sputtering, the film thickness in this area does not become large, and the processing of the interlayer insulating film is easy. 5
・The top surface of the pedestal can be reliably exposed by the connecting bank, and connections with the upper wiring can be made with high reliability.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are a plan view and a cross-sectional view of an embodiment of the present invention; FIGS. 2(a) and (b) are cross-sectional views showing a part of the mold-making process; FIG. is a cross-sectional view showing a conventional structure, and FIG. 4 is a cross-sectional view M showing problems in the conventional structure. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... (color border film, 3... Lower aluminum wiring, 4... Molybdenum film, 5...
Pedestal, 6... Interlayer insulating film, 7... Upper aluminum wiring, 11... Silicon substrate, 12... Insulating film, 13... Lower wiring, 14... Pedestal, 15.
・Interlayer color border! ! q, 16 Fig. 1 (cL'+ zu Fig. 2<Ib), 3 3'''7

Claims (1)

[Claims] 1. In a multilayer wiring structure in which a pedestal is erected on the lower wiring and the upper end of the pedestal is exposed on the interlayer insulating film to make electrical connection with the upper wiring, A multilayer wiring structure in which multiple pedestals are installed independently on the side wiring, and the upper and lower wiring are electrically connected via these pedestals. 2. The multilayer wiring structure according to claim 1, wherein the interlayer insulating film is formed to a thickness that covers the pedestal by bias sputtering, and is etched back to expose the upper end of the pedestal. 3. The multilayer wiring structure according to claim 1, wherein the total cross-sectional area of the plurality of pedestals is set to a required cross-sectional area.