JPS60192348A - Method for forming multilayer wiring of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a multilayer wiring having no disconnection of wire by a method wherein, after an etching process has been performed in such a manner that the contact part of a lower wiring metal will be protruded, an insulating film is formed on the surface other than the contact part in such a manner that it will be positioned on the same plane surface. CONSTITUTION:A surface protective film 2 and the first layer wiring metal film 3 are provided on a semiconductor substrate 1, and a photoresist 9 is coated on a contact part only. Then, the wiring metal film 3 located on the area other than a protruded part 8 is removed by etching in the thickness of t1 using the photoresist 9 as a mask. Subsequently, a photoresist 10 is coated, a patterning is performed, and after an etching has been conducted, the resist 10 is removed. Then, an insulating film 11 of the thickness t1 is provided, a photoresist 12 is coated on the surface, excluding the protruded part. After an etching has been performed on the insulating film located on the section corresponding to the protruded part 8 using the resist 12 as a mask, the resist 12 is removed, and the second wiring metal film 5 is coated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a method for forming a multilayer wiring in which a semiconductor integrated circuit has two or more wiring electrode layers.

[Prior art and its problems]

In large-scale semiconductor integrated circuits where a large number of extremely finely processed functional elements are integrated on a single semiconductor substrate, the upper electrode wiring becomes extremely complex, and the required connections cannot be achieved with just one layer of metal film. Since it is not possible to satisfy all of the above requirements, it is common practice to perform multilayer wiring in which a second layer, a third layer, and a wiring metal film are disposed with an insulating film interposed therebetween.

The most important thing when forming such a multilayer wiring is to maintain a good connection between each wiring metal film through a contact hole provided in an insulating film. However, in general, a steep portion is likely to occur in the shape of a step between the contact hole wall provided in the interlayer insulating film and the wiring metal film, resulting in defective step coverage at the step portion, which may lead to wire breakage.

For example, FIG. 1 is a schematic cross-sectional view of a part of a semiconductor integrated circuit, in which a first layer of wiring metal 3 is provided on the main surface of a semiconductor substrate 1 with a surface protective film 2 interposed therebetween. In this case, an insulating film 4 is further deposited, and a second layer of wiring metal 5 is provided on top of it to form a two-layer wiring. It will be held in Hall 6. However, as shown in FIG. 1, due to the step difference caused by the insulating film 4, the second layer wiring metal 5 is
Sharp corners may be formed and wires may break.

On the other hand, several methods have been used to avoid step coverage defects. FIG. 2 is a partial cross-sectional view of a semiconductor integrated circuit in which parts common to those in FIG. 1 are denoted by the same reference numerals. For example, as shown in FIG.
In the photo-etching process for forming the contact hole 6, etching in the lateral direction is promoted more than in the vertical direction, thereby tapering the contact hole 6 and preventing the formation of steep steps in the insulating film 4. 5
One of the countermeasures is the bevel method to improve poor step coverage. However, although this method is simpler in processing than the case shown in Figure 1, the wiring width must be widened by the taper of the contact hole 6, so the functional elements are miniaturized to increase the degree of integration. Not good for this purpose. In addition, to prevent step coverage defects in the second layer wiring metal, alumina (A
There is also an anodic oxidation method that creates an insulating film of l2Og) and leaves a contact part, but since oxidation in the lateral direction also proceeds at the same time, it is slightly better than the bevel method, but it is still fine because a tapered part is formed. There are limits to its application to integrated circuits with functional elements. In addition, At in the groove of the wiring pattern formed in the insulating film with the same thickness as the predetermined wiring At film thickness.
In order to make a truly flat layer, the lift-off method is used to form an apparently flat first layer At wiring pattern by embedding
It takes a lot of man-hours because it is necessary to add processes such as applying and removing photoresist, but on the other hand, after forming the pattern of the first layer wiring At by etching, a resin such as polyimide is applied over it to form a flat layer. Each of the above-mentioned methods cannot avoid its own drawbacks, such as the fact that microfabrication of materials such as polyimide is limited by the chemical properties of the insulation method.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks and to form a multilayer interconnection method capable of maintaining good interconnection between interconnect metals when performing multilayer interconnection of an integrated circuit equipped with a large number of miniaturized semiconductor elements. Our goal is to provide the following.

[Key points of the invention]

In the present invention, the surface of the lower wiring metal other than the contact portion is removed by etching to an appropriate depth, the contact portion is processed to protrude, and then the insulating film is cut out from the surface other than the contact portion. By making the surface of the contact part on the same plane and depositing the upper layer wiring metal on this surface, a multilayer wiring with good connections is formed without disconnections caused by steps. It is.

[Embodiments of the invention]

The present invention will be explained below based on examples.

FIG. 3 is a partially enlarged cross-sectional view of a semiconductor integrated circuit having a wiring metal layer formed by the method of the present invention, and FIG. 4 is a cross-sectional view showing the method of the present invention in the order of steps. Also, parts common to those in FIGS. 1 and 2 are represented by the same reference numerals.

In Figure 3, a protrusion 8 is formed on the first layer wiring metal 3 provided on the semiconductor substrate 1 via the surface protection film (5) 2, which becomes a connection part with the second layer wiring metal 5. The surface area of the first layer wiring metal 3 where the protrusion 8 is not formed is covered with an insulating film 4, and the protrusion 8 and the insulating film 4 are arranged so that their respective upper end surfaces are on the same plane. Since the second layer wiring metal 5 is deposited on a flat surface, the wiring metal has a structure in which variations in thickness due to steps cannot occur.

In Figure 4, the manufacturing process for creating such a structure is shown in A-
The steps will be explained by arranging them in the order of steps up to F. First, as shown in FIG. 4A, a surface protective film 2 and a first-layer wiring metal film 3 such as At are formed on a semiconductor substrate 1 in this order, and a photoresist 9 is applied only to the contact portions between the wiring metals. At this time, the thickness of the first layer wiring metal film 3 is the thickness of the protruding portion 8 shown in FIG. 3, that is, the thickness t of the portion located directly below the insulating film 4 in FIG.

and the thickness tl of only the protruding portion of the protrusion 8, to+
It is necessary to keep this in mind. Next, using the photoresist 9 as a mask, the wiring metal film 3 other than the protrusion 8 is etched away by a thickness tl, resulting in the result shown in FIG. 4B(6). Next, as shown in FIG. 4C, a photoresist 10 is applied and patterned to form a second layer wiring metal film, and after etching, the resist 10 is removed, resulting in the result as shown in the fourth diagram. Next, an insulating film 11 with a thickness tl is provided on the protrusion 8.
When the photoresist 12 is coated on the surface except for
It becomes like this. Using this resist 12 as a mask, the insulating film 11 at the portions corresponding to the protrusions 8 is etched and removed, and then the resist 12 is removed and a second layer wiring metal film 5 such as KT is deposited. A two-layer wiring of an integrated circuit is formed which has interlayer insulation as shown in FIG. 4F and whose connections are made in a precise shape. In this example, 271
In the case of I wiring As mentioned above, if multilayer wiring of three or more layers is required, it goes without saying that the above-mentioned steps A and F can be repeated.

Although FIG.

The method shown in FIG. 5 is omitted because the steps up to the fourth drawing are the same, and starting from the state of the fourth drawing,
An organic insulating film or inorganic insulating film 13 made of, for example, polyimide or milanol resin is formed on the first layer wiring metal film 3.
When the surface of the insulating film 13 is uniformly flattened by spin coating, the thickness of the insulating film 13 at the protrusion 8 becomes considerably thinner than the thickness of the insulating film in the area where no protrusion is formed, but as shown in FIG. A plane parallel to the substrate 1 is obtained.

Next, if the insulating film 13 is uniformly etched away until the surface of the protrusion 80 is exposed and the thickness is reduced, the transition can be made as shown in FIG. 5B while keeping the plane parallel to the substrate 1. , a second layer wiring metal film 5 is deposited on this surface,
The state shown in FIG. 5C is obtained.

As shown in the two embodiments shown in FIGS. 4 and 5 above, in both cases, the connection between the upper and lower wiring metal layers is handled by the protrusion of the lower wiring metal, and the connection between the upper and lower wiring metal layers is The parts other than the connection parts are filled with an insulating film, so
There is no room for wiring points with sharp edges. Furthermore, the fifth
The procedure shown in the figure is advantageous in that the step of buttering using a photoresist corresponding to FIG. 4E can be omitted.

〔Effect of the invention〕

As shown in the embodiments above, the method for forming a multilayer interconnection according to the present invention is applicable to the locations where the first layer interconnect metal film provided on the semiconductor substrate through the insulating film connects to the second layer interconnect metal film and conducts. Either leave the only convex part in a convex shape, and cover the non-connected part with an insulating film so that it is at the same height as the convex connected part to make the top surface flat, or cover it with a thickness that completely covers the convex connected part. When installing an insulating film, reduce the thickness of this insulating film until the surface of the connection part is exposed so that the connection part and the insulating film are on the same plane, and then deposit a second layer of wiring metal on these surfaces. carried out by
After that, this method can be repeated to obtain any number of multilayer wirings, so when providing the second layer of wiring metal film,
This can be done without considering the level difference between the first-layer wiring metal film and the insulating layer, so there will be no step or coverage defects, and the connection between both wiring metals will not have any defects and will be completely fixed in places. This has the effect of accurately obtaining the shape of the phase (9).

[Brief explanation of the drawing]

1 to 5 each show a partial cross-sectional view of a semiconductor integrated circuit, FIG. 1 is an explanatory diagram of steps and poor coverage, and FIG. 2 is an explanatory diagram of a bevel method. FIG. 3 is an element configuration diagram obtained by the wiring method of the present invention,
FIG. 4 is a manufacturing process diagram, and FIG. 5 is a manufacturing process diagram of the method of the present invention, which is partially different from FIG. 4. 1... Semiconductor substrate, 2... Surface protective film, 3.5...
・Wiring metal film, 4.7.11.13...Insulating film, 6
...Contact hole, 8...protrudes! , 9.10.
12...Fuo I resist. (10) Figure 1 Figure 2

Claims (1)

[Claims] 1) A protrusion is formed on the lower layer wiring to be adhered to the surface of the semiconductor substrate, and then an insulating film is provided that covers the lower layer wiring other than the protrusion and whose surface is flush with the upper surface of the protrusion, and 1. A method for forming multilayer wiring for a semiconductor integrated circuit, the method comprising depositing upper layer wiring on a semiconductor integrated circuit.