JPS62155537A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the increase of connecting resistance between wirings by a method wherein an organic insulating film is attached, a section up to the middle of the thickness of an inorganic insulating film is etched, the surface is covered with an inorganic insulating film as an upper layer, and a conductive hole is formed through etching under the state in which the organic insulating film is not exposed. CONSTITUTION:An SiO2 film 2 is shaped onto a first layer wiring film 1 consisting of an Al/Si alloy, and an organic silanol film 3 is applied and the surface is flattened. A pattern for a resist film 5 is formed onto the surface of the organic silanol film. A section up to the middle of their SiO2 film 2 is removed through dry etching to shape a recessed section 13. The surfaces are coated with an SiO2 film 4 including the recessed section 13. A pattern for a resist film 51 is shaped onto the oxide film again, and dry-etched. Consequently, a conductive hole 12 reaching up to the first Al/Si alloy film 1 from the bottom of the recessed section 13 is formed. The organic insulating film does not deposit on the bottom of the through-hole 12 at that time. Accordingly, when a second layer Al wiring film 7 is shaped as shown in the figure (g), the contact resistance of first and second layer wiring films is not increased.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention provides a semiconductor device in which an interlayer insulating film is coated on the lower layer metal wiring of a multilayer wiring structure formed on a semiconductor substrate, an electrically conductive hole is formed therein, and then the upper layer metal wiring is laminated. Regarding the manufacturing method.

[Prior art and its problems]

A multilayer wiring structure of a semiconductor integrated circuit is conventionally formed by, for example, the steps shown in FIG. In FIG. 2 fal, a silicon oxide film 2 is deposited to a thickness of 5,000 layers using a vapor phase growth method on the 171st wiring film 1 made of an aluminum-silicon alloy with a thickness of 5,000 layers on a semiconductor substrate (not shown). After applying an organic silanol film 3 with a thickness of approximately 1000 μm to compensate for the unevenness of the oxide film and flatten the surface, a silicon oxide film 4 with a thickness of 100 μm is deposited again by vapor phase growth. do. Next, a pattern of the resist film 5 is formed using CHF
Figure (
A conductive hole 12 is formed as shown in C1. However, during this etching, an insulating film 6 with a thickness of several tens of organic substances is deposited on the AI/Si alloy 11, as shown in FIG.
Although the thickness is still 5000 mm, the contact resistance between the second layer wiring film 7 made of pure M and the first layer wiring film 1 becomes large, which causes poor characteristics.

[Purpose of the invention]

The present invention solves the above-mentioned problems, and when an organic insulating film is interposed between inorganic insulating films to flatten the surface of an interlayer insulating film, organic matter is deposited on the surface of the lower layer wiring during etching to form a conductive hole. The present invention relates to a method of manufacturing a semiconductor device that prevents the connection resistance between interconnects in a conductive hole from increasing due to the accumulation of .

[Key points of the invention]

In the present invention, after forming a first inorganic insulating film on the lower metal wiring, an organic insulating film is applied, and then etching is performed to form a recess that penetrates the organic insulating film and reaches the middle of the thickness of the first inorganic insulating film. After forming a second inorganic insulating film on the bottom and side surfaces of the recess and covering the top of the organic insulating film, a conductive hole is formed by etching to pass through the second inorganic insulating film and the remainder of the first inorganic insulating film. The second inorganic insulating film covers the organic insulating film during etching, so there is no accumulation of organic matter at the bottom of the through hole, and the above-mentioned purpose is achieved. is achieved.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention, and in FIG. 0 ta+, parts common to those in FIG.
A silicon oxide film 2 is formed by vapor phase growth on a first layer wiring film 1 made of a /SS alloy, and an organic silanol film 3 is applied to planarize the surface. Next, a pattern of a resist film 5 is formed on the surface of the organic silanol film as shown in FIG. In this case, the size of the opening in the resist film 5 is set to be 0.1 or more larger than the contact area required for connecting the first wiring film 1 to the upper wiring film, and the CH
Dry etching is performed using Fz+0 dew gas 11 to remove up to the middle of the SlO□ film 2 as shown in Figure tc), and the recess 1 is
form 3. In the figure (dl), the concave portion 13 is covered with a StO film 4 formed by vapor phase growth. In the figure tel, a resist film 51 is again formed on this oxide film.
A pattern is formed and dry etching is performed, whereby the first glue/St alloy 1f! is removed from the bottom of the recess 13 as shown in Figure (f). A conductive hole 12 reaching up to 1 is formed. As mentioned above, in this case, the organic silanol M3 is covered with the Si0g film 4 and does not come into contact with the etching plasma, so no organic insulating film is deposited at the bottom of the through hole 12. Therefore, as shown in FIG. Second layer M wiring film 7
1. The contact resistance of the second layer wiring film does not increase. FIG. 3 shows an MO3FET portion of a semiconductor integrated circuit manufactured according to an embodiment of the present invention.
shaped silicon substrate 21 has an N-channel source region 22. A polycrystalline silicon gate 25 is formed on the intermediate surface of the N-channel drain region 23 with a gate oxide film 24 interposed therebetween, and the surface thereof is oxidized and covered with an oxide film 26 . 111th kl/Si alloy wiring film 1
is in contact with source region 22 and drain region 23 at an opening between gate oxide film 24 and field oxide film 27. The interlayer insulating film between the second layer M wiring film 7 is
It consists of vapor-phase grown SiOg films 2 and 4 and an organic silanol film 3 interposed therebetween, and a second wiring film 7 is formed on the first wiring film 1 in the conductive hole 12 formed based on the present invention. are in contact and connected.

【Effect of the invention】

According to the present invention, an organic insulating film is deposited to flatten the surface of an inorganic interlayer insulating film, and then etched to the middle of the thickness of the inorganic insulating film, and then covered with an upper inorganic insulating film, so that the organic insulating film is The conductive hole is formed by etching the conductive hole in an unexposed state, and since there is no deposition of organic matter during the formation of the conductive hole, the contact resistance at the connection between the laminated wiring becomes extremely small, making it suitable for semiconductor devices with a multilayer wiring structure. Manufacturing yield can be improved.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view sequentially showing the process of forming a multilayer wiring structure according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a conventional multilayer wiring structure forming process, and FIG. FIG. 2 is a sectional view of a main part of a semiconductor integrated circuit. 1+A7/Si alloy wiring film, 2.4: Vapor phase growth 5ift
Film, 3: Organic silanol film, 5,51 resist film, (
d) Figure 1〈6 Figure 2

Claims (1)

[Claims] 1) A semiconductor device in which the interlayer insulating film of a multilayer wiring structure formed on a semiconductor substrate is an inorganic insulating film laminated with an organic insulating film interposed therebetween, and the interlayer insulating film is provided with conductive holes for connection between the wirings. In the manufacturing method, a first inorganic insulating film is formed on the lower metal wiring, an organic insulating film is applied, and then a recess is formed that penetrates the organic insulating film and reaches the middle of the thickness of the first inorganic insulating film. , after covering the bottom and side surfaces of the recess and the top of the organic insulating film with a second inorganic insulating film, a conductive hole is formed by etching to penetrate the second inorganic insulating film and the remainder of the first inorganic insulating film; A method for manufacturing a semiconductor device, comprising filling the conductive hole to form an upper layer metal wiring.