JPH05267290A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Semiconductor integrated circuit and manufacture thereof

Info

Publication number
JPH05267290A
JPH05267290A JP6250192A JP6250192A JPH05267290A JP H05267290 A JPH05267290 A JP H05267290A JP 6250192 A JP6250192 A JP 6250192A JP 6250192 A JP6250192 A JP 6250192A JP H05267290 A JPH05267290 A JP H05267290A
Authority
JP
Japan
Prior art keywords
wiring
integrated circuit
semiconductor integrated
metallic
metallic wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6250192A
Other languages
Japanese (ja)
Inventor
Harumi Hifumi
晴美 一二三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamaguchi Ltd
Original Assignee
NEC Yamaguchi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamaguchi Ltd filed Critical NEC Yamaguchi Ltd
Priority to JP6250192A priority Critical patent/JPH05267290A/en
Publication of JPH05267290A publication Critical patent/JPH05267290A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a semiconductor integrated circuit having a metallic wiring of a shape which can improve the step coverage of a coating film, by causing the metallic wiring to have a structure in which the metallic wiring has, in the vertical section thereof, an obtuse angle formed between the upper surface and the side thereof and has an acute angle formed between the undersurface and the side thereof CONSTITUTION:In a semiconductor integrated circuit having a metallic wiring 5 connecting elements and circuits, the metallic wiring 5 is provided with a structure in which the metallic wiring has, in the vertical section thereof, an angle greater than 90 degrees formed between the upper surface and the side thereof and has an angle not greater than 90 degrees formed between the undersurface and the side thereof. When a layer insulation film 2 is formed on a semiconductor substrate 1 and a metallic layer 3 becoming a wiring is formed thereon to manufacture a semiconductor integrated circuit, a photoresist film 4 is formed on the upper surface of the metallic layer 3 and a desired metallic wiring is patterned. Then, with the photoresist film 4 as a mask the metallic layer 3 is etched by an isotropic etching process. Next, an etching is performed by an anisotropic etching process to form the metallic wiring 5.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体集積回路および
その製造方法に利用され、特に、金属配線の形状とその
形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a semiconductor integrated circuit and a method for manufacturing the same, and more particularly to a shape of metal wiring and a method for forming the same.

【0002】[0002]

【従来の技術】従来の半導体集積回路のアルミニウム配
線は、ドライエッチングによる異方性エッチングのみを
使用して形成していたため、図3に示すように、アルミ
ニウム配線5の上面と側面とのなす角度は、直角または
鋭角になっていた。
2. Description of the Related Art Since aluminum wiring of a conventional semiconductor integrated circuit is formed by using only anisotropic etching by dry etching, as shown in FIG. Had a right angle or an acute angle.

【0003】このような形状のアルミニウム配線5上に
PSG膜などのパッシベーション膜6を成長させると、
パッシベーション膜6は下地の鋭くとがった部分、すな
わちアルミニウム配線5の上面と側面の接する角度部に
集中して厚く成長するため、パッシベーション膜6はス
テップカバレージの悪い形状になっていた。
When a passivation film 6 such as a PSG film is grown on the aluminum wiring 5 having such a shape,
Since the passivation film 6 grows thickly in a sharply-grounded portion of the base, that is, at an angle portion where the upper surface and the side surface of the aluminum wiring 5 are in contact with each other, the passivation film 6 has a shape with poor step coverage.

【0004】[0004]

【発明が解決しようとする課題】この従来の半導体集積
回路におけるアルミニウム配線の形状では、上面が側面
に接する角度部が垂直または鋭角であり、この角度部に
パッシベーション膜が集中して成長するため、パッシベ
ーション膜のステップカバレージが悪く、パッシベーシ
ョン膜の厚い部分と薄い部分ができていた。パッシベー
ション膜の厚い部分には、隣接するアルミニウム配線の
パッシベーション膜が接触する欠点があり、パッシベー
ション膜の薄い部分には、耐湿性が悪く、ストレスに対
しても弱くなる欠点があった。
In the shape of the aluminum wiring in the conventional semiconductor integrated circuit, the angle portion where the upper surface is in contact with the side surface is vertical or acute, and the passivation film concentrates and grows at this angle portion. The step coverage of the passivation film was poor, and thick and thin portions of the passivation film were formed. The thick part of the passivation film has a drawback that the passivation film of the adjacent aluminum wiring is in contact with the thick part, and the thin part of the passivation film has a drawback that it has poor moisture resistance and is weak against stress.

【0005】本発明の目的は、前記の欠点を除去するこ
とにより、被覆膜のステップカバレージを改善できる形
状の金属配線を有する半導体集積回路およびその製造方
法を提供することにある。
An object of the present invention is to provide a semiconductor integrated circuit having a metal wiring having a shape capable of improving the step coverage of a coating film by eliminating the above-mentioned drawbacks, and a method of manufacturing the same.

【0006】[0006]

【課題を解決するための手段】本発明の半導体集積回路
は、素子および回路の接続を行う金属配線を有する半導
体集積回路において、前記金属配線は、その垂直断面に
おいて、上面と側面とのなす角度が90度より大であ
り、底面と側面とのなす角度が90度以下である構造を
有することを特徴とする。
The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a metal wiring for connecting elements and circuits, wherein the metal wiring has an angle between a top surface and a side surface in a vertical cross section thereof. Is greater than 90 degrees, and the angle between the bottom surface and the side surface is 90 degrees or less.

【0007】また、本発明の半導体集積回路の製造方法
は、半導体基板上に層間絶縁膜を形成しその上に配線と
なる金属層を形成する工程を含む半導体集積回路の製造
方法において、前記金属層上面にホトレジスト膜を形成
し所望の金属配線をパターンニングする工程と、次い
で、前記ホトレジスト膜をマスクとして前記金属層を等
方性エッチング法によりエッチングする第一のエッチン
グ工程と、次いで、異方性エッチング法によりエッチン
グを行い前記金属配線を形成する第二のエッチング工程
とを含むことを特徴とする。
The method for manufacturing a semiconductor integrated circuit according to the present invention is the method for manufacturing a semiconductor integrated circuit, comprising the step of forming an interlayer insulating film on a semiconductor substrate and forming a metal layer to be a wiring thereon. A step of forming a photoresist film on the upper surface of the layer and patterning a desired metal wiring, then a first etching step of etching the metal layer by an isotropic etching method using the photoresist film as a mask, and then an anisotropic method A second etching step of forming the metal wiring by etching by a positive etching method.

【0008】[0008]

【作用】金属配線例えばアルミニウム配線の形状は、垂
直断面の上面と側面とのなす角度が90度よりも大で、
下面と側面のなす角度が90度以下であるため、パッシ
ベーション膜はアルミニウム配線の上面部に集中するこ
となく、かつ下面部に十分に行きわたるようになり、ス
テップカバレージの悪化を防止することが可能となる。
The metal wiring, for example, the aluminum wiring has a shape in which the angle between the upper surface and the side surface of the vertical section is larger than 90 degrees,
Since the angle between the lower surface and the side surface is 90 degrees or less, the passivation film can be spread sufficiently over the lower surface without being concentrated on the upper surface of the aluminum wiring, and it is possible to prevent the deterioration of the step coverage. Becomes

【0009】また、このような形状の金属配線の製造方
法としては、金属層から金属配線をエッチングにより形
成する場合に、始めに等方性のエッチング法により金属
配線の上面部を形成することで、上面の角度部をすべて
鈍角とし、次に、異方性エッチング法により、下面の角
度部を90度以下の角度にすることで、製造することが
できる。
Further, as a method of manufacturing the metal wiring having such a shape, when the metal wiring is formed from the metal layer by etching, first, the upper surface portion of the metal wiring is formed by the isotropic etching method. It is possible to manufacture by making all the angled parts of the upper surface obtuse and then making the angled parts of the lower surface 90 degrees or less by the anisotropic etching method.

【0010】[0010]

【実施例】以下、本発明の実施例について図面を参照し
て説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0011】図1は本発明の半導体集積回路の一実施例
の要部を示す断面図である。
FIG. 1 is a sectional view showing a main part of an embodiment of a semiconductor integrated circuit according to the present invention.

【0012】本実施例は、半導体基板1上にシリコン酸
化膜2を介して形成された金属配線としてのアルミニウ
ム配線5を有する半導体集積回路において、本発明の特
徴とするところの、アルミニウム配線5は、その垂直断
面において上面と側面とのなす角度がすべて90度より
も大であり、底面と側面とのなす角度がすべて90度以
下である構造を有している。
This embodiment is a semiconductor integrated circuit having an aluminum wiring 5 as a metal wiring formed on a semiconductor substrate 1 with a silicon oxide film 2 interposed therebetween. The vertical cross section has a structure in which the angles formed by the top surface and the side surfaces are all greater than 90 degrees, and the angles formed by the bottom surface and the side surfaces are all 90 degrees or less.

【0013】本実施例においては、このアルミニウム配
線5の構造により、パッシベーション膜6は、アルミニ
ウム配線5の上面に集中することなく下面部によく行き
わたり、各部ともほぼ均一な厚さで形成され、ステップ
カバレージが悪化することはない。
In the present embodiment, due to the structure of the aluminum wiring 5, the passivation film 6 does not concentrate on the upper surface of the aluminum wiring 5 and often spreads to the lower surface portion, and each portion is formed with a substantially uniform thickness. Step coverage does not deteriorate.

【0014】次に、本実施例の製造方法について図2
(a)、(b)および(c)を参照して説明する。
Next, the manufacturing method of this embodiment will be described with reference to FIG.
This will be described with reference to (a), (b) and (c).

【0015】まず、図2(a)に示すように、半導体基
板1上面にシリコン酸化膜2を形成し、その上面にアル
ミニウム層3を形成し、さらにその上面にホトレジスト
膜4を形成しホトリソグラフィ技術を用いてホトレジス
ト膜4をアルミニウム配線用にパターンニングする。
First, as shown in FIG. 2A, a silicon oxide film 2 is formed on the upper surface of a semiconductor substrate 1, an aluminum layer 3 is formed on the upper surface thereof, and a photoresist film 4 is further formed on the upper surface thereof, followed by photolithography. The photoresist film 4 is patterned for aluminum wiring by using a technique.

【0016】次に、図2(b)に示すように、等方性エ
ッチング条件でアルミニウム層3を第一ドライエッチン
グし、湾曲部を形成する。
Next, as shown in FIG. 2B, the aluminum layer 3 is first dry-etched under isotropic etching conditions to form a curved portion.

【0017】次に、図2(c)に示すように、第二ドラ
イエッチングとして、従来通りの異方性エッチングを行
い、アルミニウム配線5を形成する。
Next, as shown in FIG. 2C, as the second dry etching, the conventional anisotropic etching is performed to form the aluminum wiring 5.

【0018】こうして形成したアルミニウム配線5であ
れば、パッシベーション膜6は、図1に示すように、均
一にアルミニウム配線5を被膜することができる。
With the aluminum wiring 5 thus formed, the passivation film 6 can uniformly coat the aluminum wiring 5 as shown in FIG.

【0019】なお、以上の説明においては、金属配線を
アルミニウム配線、および被覆物をパッシベーション膜
としたけれども、これ以外のものについても同様であ
る。
In the above description, the metal wiring is an aluminum wiring and the coating is a passivation film, but the same applies to other materials.

【0020】[0020]

【発明の効果】以上説明したように、本発明は、例えば
アルミニウム配線の上面と側面とのなす角度を90度よ
りも大きく、底面と側面とのなす角度を90度以下にす
ることによって、アルミニウム配線上に被覆する例えば
パッシベーション膜のステップカバレージを改善する効
果がある。
As described above, according to the present invention, for example, the angle between the upper surface and the side surface of the aluminum wiring is larger than 90 degrees, and the angle between the bottom surface and the side surface is 90 degrees or less. This has the effect of improving the step coverage of, for example, a passivation film covering the wiring.

【0021】従って、本発明によれば、隣接アルミニウ
ム配線同士のパッシベーション膜の接触を防ぎ、パッシ
ベーション膜の極端に薄い部分がなくなることによっ
て、製品の耐湿性が向上し、さらに、アルミニウム配線
上にパッシベーション膜が均一に被膜するため、パッシ
ベーション膜からアルミニウム配線へのストレスが一部
に集中することがなく、ストレスマイグレーションが起
こりにくくなり、その効果は大である。
Therefore, according to the present invention, the contact of the passivation film between the adjacent aluminum wirings is prevented, and the extremely thin portion of the passivation film is eliminated, so that the moisture resistance of the product is improved and further the passivation film on the aluminum wiring is improved. Since the film is uniformly coated, the stress from the passivation film to the aluminum wiring is not concentrated on a part, stress migration is less likely to occur, and the effect is great.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体集積回路の一実施例の要部を示
す断面図。
FIG. 1 is a sectional view showing a main part of an embodiment of a semiconductor integrated circuit of the present invention.

【図2】その製造方法の要部を示す工程断面図。FIG. 2 is a process cross-sectional view showing the main parts of the manufacturing method.

【図3】従来例の半導体集積回路の要部を示す断面図。FIG. 3 is a cross-sectional view showing a main part of a conventional semiconductor integrated circuit.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 シリコン酸化膜 3 アルミニウム層 4 ホトレジスト膜 5 アルミニウム配線 6 パッシベーション膜 1 Semiconductor Substrate 2 Silicon Oxide Film 3 Aluminum Layer 4 Photoresist Film 5 Aluminum Wiring 6 Passivation Film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 素子および回路の接続を行う金属配線を
有する半導体集積回路において、 前記金属配線は、その垂直断面において、上面と側面と
のなす角度が90度より大であり、底面と側面とのなす
角度が90度以下である構造を有することを特徴とする
半導体集積回路。
1. A semiconductor integrated circuit having metal wiring for connecting an element and a circuit, wherein the metal wiring has an angle between a top surface and a side surface of more than 90 degrees in a vertical cross section, and a bottom surface and a side surface. 1. A semiconductor integrated circuit having a structure in which an angle formed by is 90 degrees or less.
【請求項2】 半導体基板上に層間絶縁膜を形成しその
上に配線となる金属層を形成する工程を含む半導体集積
回路の製造方法において、 前記金属層上面にホトレジスト膜を形成し所望の金属配
線をパターンニングする工程と、 次いで、前記ホトレジスト膜をマスクとして前記金属層
を等方性エッチング法によりエッチングする第一のエッ
チング工程と、 次いで、異方性エッチング法によりエッチングを行い前
記金属配線を形成する第二のエッチング工程とを含むこ
とを特徴とする半導体集積回路の製造方法。
2. A method of manufacturing a semiconductor integrated circuit, which includes a step of forming an interlayer insulating film on a semiconductor substrate and forming a metal layer to be a wiring thereon, wherein a photoresist film is formed on the upper surface of the metal layer to form a desired metal. A step of patterning the wiring, then a first etching step of etching the metal layer by an isotropic etching method using the photoresist film as a mask, and then etching by an anisotropic etching method to form the metal wiring. And a second etching step for forming the semiconductor integrated circuit.
JP6250192A 1992-03-18 1992-03-18 Semiconductor integrated circuit and manufacture thereof Pending JPH05267290A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6250192A JPH05267290A (en) 1992-03-18 1992-03-18 Semiconductor integrated circuit and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6250192A JPH05267290A (en) 1992-03-18 1992-03-18 Semiconductor integrated circuit and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH05267290A true JPH05267290A (en) 1993-10-15

Family

ID=13201982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6250192A Pending JPH05267290A (en) 1992-03-18 1992-03-18 Semiconductor integrated circuit and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH05267290A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814558A (en) * 1994-08-31 1998-09-29 Texas Instruments Incorporated Interconnect capacitance between metal leads
US5818111A (en) * 1997-03-21 1998-10-06 Texas Instruments Incorporated Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials
US6054769A (en) * 1997-01-17 2000-04-25 Texas Instruments Incorporated Low capacitance interconnect structures in integrated circuits having an adhesion and protective overlayer for low dielectric materials
KR100781394B1 (en) * 1999-02-05 2007-11-30 꼼미사리아 아 레네르지 아토미끄 Zirconium and niobium alloy comprising erbium, preparation method and component containing said alloy
KR100917823B1 (en) * 2007-12-28 2009-09-18 주식회사 동부하이텍 Method of manufacturing metal line of the semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814558A (en) * 1994-08-31 1998-09-29 Texas Instruments Incorporated Interconnect capacitance between metal leads
US6054769A (en) * 1997-01-17 2000-04-25 Texas Instruments Incorporated Low capacitance interconnect structures in integrated circuits having an adhesion and protective overlayer for low dielectric materials
US5818111A (en) * 1997-03-21 1998-10-06 Texas Instruments Incorporated Low capacitance interconnect structures in integrated circuits using a stack of low dielectric materials
KR100781394B1 (en) * 1999-02-05 2007-11-30 꼼미사리아 아 레네르지 아토미끄 Zirconium and niobium alloy comprising erbium, preparation method and component containing said alloy
KR100917823B1 (en) * 2007-12-28 2009-09-18 주식회사 동부하이텍 Method of manufacturing metal line of the semiconductor device
US7659195B2 (en) 2007-12-28 2010-02-09 Dongbu Hitek Co., Ltd. Method for forming metal line of semiconductor device

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