JPH05144812A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05144812A
JPH05144812A JP32712091A JP32712091A JPH05144812A JP H05144812 A JPH05144812 A JP H05144812A JP 32712091 A JP32712091 A JP 32712091A JP 32712091 A JP32712091 A JP 32712091A JP H05144812 A JPH05144812 A JP H05144812A
Authority
JP
Japan
Prior art keywords
film
aluminum
wiring
conductive film
titanium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP32712091A
Other languages
Japanese (ja)
Inventor
Eiichiro Kakehashi
英一郎 梯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP32712091A priority Critical patent/JPH05144812A/en
Publication of JPH05144812A publication Critical patent/JPH05144812A/en
Withdrawn legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To provide the manufacturing method for a semiconductor device on which a metal film is formed on the upper part and the side wall of an aluminum or aluminum alloy wiring in an excellent controllable manner. CONSTITUTION:An aluminum film 13 and a titanium film 14 are successively formed on the oxide film 12 formed on a silicon substrate 11. Then, after an oxide film 15 has been formed, the oxide film 15, the titanium film 14 and the aluminum film 13 are etched successively using the wiring mask formed by photolithography. A TiW film 106 is formed thereon. The TiW film 16 is left on the side wall of the aluminum wiring 13 by conducting an overall etching treatment. Consequently, as an oxide film 15 is formed on the titanium film 14, the titanium film 14 is not exposed to etching when the TiW film 16 is etched.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、特に金属配線の形成方法に改良を加えた半導体
装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device obtained by improving a method for forming metal wiring.

【0002】[0002]

【従来の技術】従来より半導体装置の高集積化に伴い配
線の微細化が進んでおり、近年になってアルミニウム・
シリコン合金からなる配線では、エレクトロマイグレー
ションやストレスマイグレーションによる不良が問題と
なってきた。その対策として、アルミニウム・シリコン
合金からなる配線の上部及び側壁に金属膜を形成する構
造のものが、例えば特開昭60−193362号、特開
昭62−66628号公報等に記載されている。
2. Description of the Related Art Since the miniaturization of wiring has been advancing along with the high integration of semiconductor devices, aluminum
Wiring made of a silicon alloy has been problematic due to defects due to electromigration and stress migration. As a countermeasure, a structure in which a metal film is formed on the upper and side walls of a wiring made of an aluminum-silicon alloy is described in, for example, JP-A-60-193362 and JP-A-62-66628.

【0003】図3に、この従来の半導体装置の製造行程
が示されている。ここで、この図3を用いて従来の半導
体装置の製造方法を説明する。まず、図3(a)に示す
ように、シリコン基板31上に形成された酸化膜(絶縁
膜)32の上にアルミニウム膜33,チタン膜34を順
次スパッタ法により形成する。次いで、フォトリソグラ
フィ(露光技術)により形成した図示しない配線マスク
を用いて、チタン膜34,アルミニウム膜33を順次エ
ッチングして配線パターンを形成する(図3(b)参
照)。次に、この形成された配線パターンを覆うように
チタン膜35を形成する(図3(c)参照)。そして、
基板全面をエッチバックし、アルミニウム配線33の上
部及び側壁にチタン膜34及び35が残るようにする
(図3(d)参照)。これにより、アルミニウム配線3
3の上部及び側壁部をチタン膜34及び35で被覆する
ことができる。
FIG. 3 shows a manufacturing process of this conventional semiconductor device. Here, a conventional method of manufacturing a semiconductor device will be described with reference to FIG. First, as shown in FIG. 3A, an aluminum film 33 and a titanium film 34 are sequentially formed on an oxide film (insulating film) 32 formed on a silicon substrate 31 by a sputtering method. Then, using a wiring mask (not shown) formed by photolithography (exposure technique), the titanium film 34 and the aluminum film 33 are sequentially etched to form a wiring pattern (see FIG. 3B). Next, a titanium film 35 is formed so as to cover the formed wiring pattern (see FIG. 3C). And
The entire surface of the substrate is etched back so that the titanium films 34 and 35 are left on the upper portions and the side walls of the aluminum wiring 33 (see FIG. 3D). As a result, the aluminum wiring 3
The top and side walls of 3 can be coated with titanium films 34 and 35.

【0004】[0004]

【発明が解決しようとする課題】上述した従来技術で
は、アルミニウム配線33側壁に図3(d)に示す金属
膜35(以下、ここでは、「金属膜2」と呼ぶ。)を残
すエッチングの際に、アルミニウム配線33上部に形成
してある金属膜34(以下、ここでは「金属膜1」と呼
ぶ。)はエッチングにさらされる。金属膜1と金属膜2
とを異なる材料の金属膜にして金属膜2のエッチングを
金属膜1に対するエッチング選択比が大きくとれるよう
にしてもエッチングによる金属膜1の膜減りは避けられ
ないという不都合があった。
In the above-mentioned conventional technique, the metal film 35 shown in FIG. 3D (hereinafter referred to as "metal film 2") is left on the side wall of the aluminum wiring 33 during etching. Further, the metal film 34 (hereinafter referred to as “metal film 1” here) formed on the aluminum wiring 33 is exposed to etching. Metal film 1 and metal film 2
Even if the metal films made of different materials are used and the metal film 2 can be etched with a large etching selection ratio with respect to the metal film 1, there is an inconvenience that the reduction of the metal film 1 due to etching is unavoidable.

【0005】[0005]

【発明の目的】本発明の目的は、かかる従来技術の有す
る不都合を改善し、金属配線の上部及び側壁を被覆する
金属膜を制御よく形成することができる半導体装置の製
造方法を提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is capable of improving the disadvantages of the prior art and forming a metal film for covering the upper portion and the side wall of a metal wiring with good controllability. is there.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置の製
造方法では、半導体基板上に形成された絶縁膜の上に第
1の導電膜,第2の導電膜を順次形成し、第2の導電膜
の上にマスク材料膜を形成し、マスク材料膜と第2の導
電膜と第1の導電膜とを同一マスクパターンで順次エッ
チングを行って配線パターンを形成し、次いでこの形成
された配線パターンを覆うように第3の導電膜を形成
し、しかる後に、第1の導電膜の側壁に第3の導電膜を
残すように異方性エッチングを行なうという手法を採っ
ている。
In the method of manufacturing a semiconductor device according to the present invention, a first conductive film and a second conductive film are sequentially formed on an insulating film formed on a semiconductor substrate, and a second conductive film is formed. A mask material film is formed on the conductive film, the mask material film, the second conductive film, and the first conductive film are sequentially etched with the same mask pattern to form a wiring pattern, and then the formed wiring is formed. A method of forming a third conductive film so as to cover the pattern and thereafter performing anisotropic etching so that the third conductive film is left on the sidewall of the first conductive film is adopted.

【0007】[0007]

【実施例】以下、本発明の一実施例を図1に基づいて説
明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

【0008】図1には、本発明の一実施例に係る半導体
製造法における工程図が示されている。ここで、この図
1に沿って半導体装置の製造方法を説明する。
FIG. 1 is a process diagram of a semiconductor manufacturing method according to an embodiment of the present invention. Here, a method of manufacturing a semiconductor device will be described with reference to FIG.

【0009】まず、図1(a)に示すように、半導体基
板としてのシリコン基板11の表面に形成された絶縁膜
としての酸化膜12上に厚さ0.6μmの第1の導電膜
としてのアルミニウム膜13,厚さ0.1μmの第2の
導電膜としてのチタン膜14をスパッタ法により順次形
成する。さらに、このチタン膜14上に、マスク材料膜
としての酸化膜15を形成する。
First, as shown in FIG. 1A, a first conductive film having a thickness of 0.6 μm is formed on an oxide film 12 as an insulating film formed on the surface of a silicon substrate 11 as a semiconductor substrate. An aluminum film 13 and a titanium film 14 as a second conductive film having a thickness of 0.1 μm are sequentially formed by a sputtering method. Further, an oxide film 15 as a mask material film is formed on the titanium film 14.

【0010】次に、フォトリソグラフィにより形成した
図示しない配線マスク(エッチングの際のマスクであ
る。)を用いて、酸化膜15、チタン膜14、アルミニ
ウム膜13を順次エッチングすることによって配線パタ
ーンを形成する(図3(b)参照)。
Next, a wiring pattern is formed by sequentially etching the oxide film 15, the titanium film 14, and the aluminum film 13 using a wiring mask (which is a mask at the time of etching) not shown formed by photolithography. (See FIG. 3B).

【0011】次いで、この形成された配線パターンを覆
うようにして厚さ0.1μmの第3の導電膜としてのT
iW膜16をスパッタ法により形成する(図3c参
照)。
Then, T as a third conductive film having a thickness of 0.1 μm is formed so as to cover the formed wiring pattern.
The iW film 16 is formed by the sputtering method (see FIG. 3c).

【0012】しかる後、TiW膜16をアルミニウム膜
13の側壁に残すように基板全面をエッチバックするこ
とにより図3(d)に示すような所望の配線構造を得
る。
Thereafter, by etching back the entire surface of the substrate so that the TiW film 16 is left on the side wall of the aluminum film 13, a desired wiring structure as shown in FIG. 3D is obtained.

【0013】以上説明した本実施例によると、チタン膜
14の上には酸化膜15が形成されているので、TiW
膜16のエッチングのとき、チタン膜14がエッチング
にさらされることがなく、従って、アルミニウム配線1
3上部のチタン膜14の膜減りをほぼ確実に防止するこ
とができ、これにより、アルミニウム配線上部及び側壁
に金属膜を制御よく形成することができる。
According to this embodiment described above, since the oxide film 15 is formed on the titanium film 14, TiW
During the etching of the film 16, the titanium film 14 is not exposed to the etching and therefore the aluminum wiring 1
3 It is possible to almost certainly prevent the reduction of the titanium film 14 on the upper part, and thereby the metal film can be formed on the upper part and the side wall of the aluminum wiring with good control.

【0014】[0014]

【応用例】図2には、本発明の応用例が示されている。
この応用例は、上記実施例におけるアルミニウム膜13
の下にチタン膜17が形成されている点に特徴を有す
る。これにより、この応用例では、アルミニウム膜,即
ちアルミニウム配線13をバリアメタル(チタン膜1
5,TiW膜16,及びチタン膜17)で囲みこむ構造
を得ることができる。
Application Example FIG. 2 shows an application example of the present invention.
This application example corresponds to the aluminum film 13 in the above embodiment.
It is characterized in that a titanium film 17 is formed underneath. As a result, in this application example, the aluminum film, that is, the aluminum wiring 13 is connected to the barrier metal (titanium film
5, a structure surrounded by the TiW film 16 and the titanium film 17) can be obtained.

【0015】[0015]

【発明の効果】以上説明したように本発明によれば、第
1の導電膜(通常はアルミニウム膜である。)から成る
金属配線上部に密着形成した第2の導電膜(金属膜)の
上にはマスク材料膜(保護膜)が形成されるので、金属
配線側壁に金属膜を残すための異方性エッチングの際、
金属配線上部に密着形成した金属膜はエッチングされな
い。これがため、金属配線上部の金属膜を制御よく形成
することができるという従来にない優れた半導体装置の
製造方法を提供することができる。
As described above, according to the present invention, on the second conductive film (metal film) formed in close contact with the upper part of the metal wiring formed of the first conductive film (usually an aluminum film). Since a mask material film (protective film) is formed on the surface, when anisotropic etching is performed to leave the metal film on the sidewall of the metal wiring,
The metal film formed in close contact with the upper portion of the metal wiring is not etched. For this reason, it is possible to provide an unprecedented excellent method of manufacturing a semiconductor device in which the metal film on the metal wiring can be formed with good control.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体の製造方法の一実施例の工程を
示す説明図である。
FIG. 1 is an explanatory view showing a process of an embodiment of a semiconductor manufacturing method of the present invention.

【図2】本発明の応用例を示す説明図である。FIG. 2 is an explanatory diagram showing an application example of the present invention.

【図3】従来の半導体の製造方法の工程を示す説明図で
ある。
FIG. 3 is an explanatory view showing steps of a conventional semiconductor manufacturing method.

【符号の説明】[Explanation of symbols]

11 半導体基板としてのシリコン基板 12 絶縁膜としての酸化膜 13 第1の導電膜としてのアルミニウム膜 14 第2の導電膜としてのチタン膜 15 マスク材料膜としての酸化膜 16 第3の導電膜としてのTiW膜 11 Silicon substrate as a semiconductor substrate 12 Oxide film as an insulating film 13 Aluminum film as a first conductive film 14 Titanium film as a second conductive film 15 Oxide film as a mask material film 16 As a third conductive film TiW film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に形成された絶縁膜の上に
第1の導電膜,第2の導電膜を順次形成し、前記第2の
導電膜の上にマスク材料膜を形成し、前記マスク材料膜
と前記第2の導電膜と前記第1の導電膜とを同一マスク
パターンで上から順次エッチングを行って配線パターン
を形成し、次いでこの形成された配線パターンを覆うよ
うに第3の導電膜を形成し、しかる後に、前記第1の導
電膜の側壁に前記第3の導電膜を残すように異方性エッ
チング行なうことを特徴とした半導体装置の製造方法。
1. A first conductive film and a second conductive film are sequentially formed on an insulating film formed on a semiconductor substrate, and a mask material film is formed on the second conductive film. The mask material film, the second conductive film, and the first conductive film are sequentially etched from above with the same mask pattern to form a wiring pattern, and then a third wiring pattern is formed so as to cover the formed wiring pattern. A method of manufacturing a semiconductor device, comprising forming a conductive film, and thereafter performing anisotropic etching so as to leave the third conductive film on a sidewall of the first conductive film.
JP32712091A 1991-11-15 1991-11-15 Manufacture of semiconductor device Withdrawn JPH05144812A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32712091A JPH05144812A (en) 1991-11-15 1991-11-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32712091A JPH05144812A (en) 1991-11-15 1991-11-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05144812A true JPH05144812A (en) 1993-06-11

Family

ID=18195531

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32712091A Withdrawn JPH05144812A (en) 1991-11-15 1991-11-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05144812A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498571A (en) * 1993-04-13 1996-03-12 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device having reliable multi-layered wiring
US7994021B2 (en) 2006-07-28 2011-08-09 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
CN103426750A (en) * 2012-05-24 2013-12-04 上海宏力半导体制造有限公司 Metal wet etching method without metal wire cut problem
US8815740B2 (en) 2012-08-24 2014-08-26 Kabushiki Kaisha Toshiba Method for forming pattern and method for fabricating semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5498571A (en) * 1993-04-13 1996-03-12 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device having reliable multi-layered wiring
US5759912A (en) * 1993-04-13 1998-06-02 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device having multi-layered wiring without hillocks at the insulating layers
US7994021B2 (en) 2006-07-28 2011-08-09 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
US8703579B2 (en) 2006-07-28 2014-04-22 Semiconductor Energy Laborator Co., Ltd. Method of manufacturing semiconductor device
CN103426750A (en) * 2012-05-24 2013-12-04 上海宏力半导体制造有限公司 Metal wet etching method without metal wire cut problem
US8815740B2 (en) 2012-08-24 2014-08-26 Kabushiki Kaisha Toshiba Method for forming pattern and method for fabricating semiconductor device

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Legal Events

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Effective date: 19990204