JPS62242337A - Formation of metal film for multilayer interconnection - Google Patents
Formation of metal film for multilayer interconnectionInfo
- Publication number
- JPS62242337A JPS62242337A JP8491986A JP8491986A JPS62242337A JP S62242337 A JPS62242337 A JP S62242337A JP 8491986 A JP8491986 A JP 8491986A JP 8491986 A JP8491986 A JP 8491986A JP S62242337 A JPS62242337 A JP S62242337A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal
- interconnection
- multilayer
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims description 37
- 239000002184 metal Substances 0.000 title claims description 36
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 19
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract 2
- 239000001301 oxygen Substances 0.000 claims abstract 2
- 229910052760 oxygen Inorganic materials 0.000 claims abstract 2
- 238000004544 sputter deposition Methods 0.000 claims abstract 2
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000010884 ion-beam technique Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 20
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract description 2
- 239000007789 gas Substances 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052593 corundum Inorganic materials 0.000 abstract 2
- 229910001845 yogo sapphire Inorganic materials 0.000 abstract 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 abstract 1
- 239000004411 aluminium Substances 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 26
- 239000010936 titanium Substances 0.000 description 15
- 239000010931 gold Substances 0.000 description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- ing And Chemical Polishing (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は半導体集積回路における配線用金属膜の形成方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for forming a metal film for wiring in a semiconductor integrated circuit.
（従来の技術）
近年、半導体集積回路の高集積化が進み、配線金属膜も
微細化が進められているが、Ａｌ配線ではエレクトロマ
イグレーション等の問題があり。(Prior Art) In recent years, semiconductor integrated circuits have become highly integrated, and wiring metal films have also been miniaturized, but Al wiring has problems such as electromigration.
信頼性の点ではＡｕ系金属の方が優れている。Ａｕ系金
属を用いた場合は反応性イオンエツチング（ＨＩＥ）に
よる加工は不可能となり、イオンビームエツチング（Ｉ
ＢＢ）による加工が必要となる。Au-based metals are superior in terms of reliability. When using Au-based metals, processing by reactive ion etching (HIE) is impossible, and processing by ion beam etching (I) is not possible.
BB) processing is required.
ＩＢＥによる加工ではレジスト等の厚いマスクを用いて
エツチングすると、第２図に示すようにレジストの側壁
にスパッタではじき出された（スパッタアウト）金属原
子が再付着し、レジスト除去後に角状となって残るため
、後工程に問題が残る。In IBE processing, when etching is performed using a thick mask such as a resist, the metal atoms that were sputtered out (sputtered out) are reattached to the side walls of the resist, forming angular shapes after the resist is removed, as shown in Figure 2. This leaves problems in subsequent processes.
そこでチタン（ＴＩ）のようなＡｌｌに対してエツチン
グ速度比のとれる金属をマスクとしてＡｕの工ッチング
を行なう場合があるが、ＴｉでもＡｕとのエツチング選
択比は５〜７程度と十分でなり０又多層配線を形成する
楊曾Ａｌｌと絶縁膜の密着性が良くないため、Ａｌｌ系
金属の最上層にはＴｉ等の絶縁膜と密着性の良好な金属
が必要となる。これらの技術的問題に対してＴｉをマス
クとしてＡｕ系金属をエツチング加工し、なおかつ最終
的に所望量のＴｉを最上層に残すことは、制御性の点で
問題がある。Therefore, Au is sometimes etched using a metal such as titanium (TI) that has a good etching rate ratio with respect to All as a mask, but even Ti has a sufficient etching selectivity ratio of about 5 to 7 with respect to Au. Furthermore, since the adhesion between the All-metal layer forming the multilayer wiring and the insulating film is not good, the top layer of the All-based metal needs to be a metal such as Ti that has good adhesion to the insulating film. In response to these technical problems, etching the Au-based metal using Ti as a mask and finally leaving a desired amount of Ti in the uppermost layer poses a problem in terms of controllability.
（発明が解決しようとする問題点）
上述したような従来の配線金属膜の形成方法では次のよ
うな問題がある。レジストをマスクとしてＩＢＢによる
加工を行った場合には、レジストの側壁にスパッタアウ
トされた金属原子が再付着し、レジスト除去後角状とな
って残り、平坦化等の後工程に問題となる。(Problems to be Solved by the Invention) The conventional method for forming a wiring metal film as described above has the following problems. When IBB processing is performed using a resist as a mask, metal atoms sputtered out re-adhere to the side walls of the resist and remain in the form of corners after the resist is removed, which poses a problem in subsequent steps such as planarization.
Ｔｉをエツチングマスクとして用いた場合はエツチング
マスクとして用い、かつエツチング［１後、所望膜厚の
Ｔｉを残すには、制御性の点で問題があるとともに、も
とのＴｉの膜厚が厚くなるため、レジストに対して薄い
膜厚でエツチングマスクとし、 ｌ１ｌｔｌ壁の角状の
成長を防ぐとｂうメリットが無くなってしまう。以上の
ような問題点を解決するには、Ａｕに対してより大きな
選択比を持つ加工性の良好な薄膜が必要である。When Ti is used as an etching mask, it is necessary to use it as an etching mask, and to leave a desired thickness of Ti after etching [1], there is a problem in terms of controllability, and the original Ti film becomes thicker. Therefore, if the etching mask is made thinner than the resist to prevent the angular growth of the l1ltl wall, there will be no advantage. In order to solve the above-mentioned problems, a thin film with good processability and a higher selection ratio with respect to Au is required.
本発明は上記の点に鑑み最下１−及び最上層をＴＩとす
るＡｕ系金属のエツチングマスクにアルミナ（ＡＪ！Ｏ
ｎ）を用いて、制御性良（Ａｕ系金属をエツチングし絶
縁膜との密着性も良好として、多層金属配線を可能とす
る多層配線金属膜の形成方法を提供することを目的とす
る。In view of the above points, the present invention has developed an etching mask using alumina (AJ!
It is an object of the present invention to provide a method for forming a multilayer wiring metal film that enables multilayer metal wiring with good controllability (etching of Au-based metal and good adhesion to an insulating film) using the method (n).
（問題点を解決するための手段）
本発明はＡｕ系金属をＩＢＥでエツチングするときのエ
ツチングマスクにＡＪ、０．を用いることによって、最
下層及び最下層をＴＩとする多層配線用Ａｕ系金嘱膜を
制御性良く形成することを特徴とする。(Means for Solving the Problems) The present invention provides an etching mask for etching Au-based metals using IBE. The method is characterized in that an Au-based gold film for multilayer wiring, in which the lowermost layer and the lowermost layer are TI, can be formed with good controllability.
（作用）
本発明によれば、１．Ｂ、Ｅ Ｋよるエツチングに２い
て、エツチング速度の遅いＡＡ’ｆｆ１Ｏ，ヲマスクと
して用すでいるためＡｕ系金属とさらに比較的エツチン
グ速１ぜの遅いＴｉを加工する際にも膜厚は薄くするこ
とができ、側壁への再付着による角状の突起物もなく、
絶縁膜との密着性の良いＴｉを最下層及び最上層に配し
たＡＬＩ系多層金属膜を制（財）住良く加工でき、多層
配線に適した配線金属膜の形成が可能になる。(Function) According to the present invention, 1. B, E Since AA'ff1O, which has a slow etching speed, is used as a mask during etching with K, the film thickness is also made thin when processing Au-based metals and Ti, which has a relatively slow etching speed. There is no angular protrusion due to reattachment to the side wall.
ALI-based multilayer metal films in which Ti, which has good adhesion to insulating films, is disposed in the bottom and top layers can be processed in a controlled manner, and a wiring metal film suitable for multilayer wiring can be formed.
（実施例） 以下本発明の実施例を図面を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の加工方法を用いた多層配線用金属膜の
形成方法の具体的実施例である。FIG. 1 shows a specific example of a method for forming a metal film for multilayer wiring using the processing method of the present invention.
半絶縁性ＧａＡｓ基板１１１Ｃ８ＩＱ、膜１２を介して
第１層金属配＠膜１３として、ＴＩ／Ｍｏ／Ａｕ／ＴＩ
をスパッタにより膜厚をそれぞれ０．１１０．１／１．
０１０．１μ積層堆積する（第１ 図（ａｌ ）。Semi-insulating GaAs substrate 111C8IQ, TI/Mo/Au/TI as first layer metal interconnection film 13 via film 12
were sputtered to a film thickness of 0.110.1/1.
010.1μ layer is deposited (Fig. 1 (al)).
続いて第１層金属配線膜１３上にＡＪ１４を連続して膜
厚０．２μ堆積する（第１１閾「ｂ））。Subsequently, AJ 14 is continuously deposited on the first layer metal wiring film 13 to a thickness of 0.2 μm (eleventh threshold “b)”.
次に、酸累プラズマ雰囲気中にさらしてＡ１４を酸化す
ることによって、アルミナＡ／＊Ｏｓ とする（第１図
（Ｃ））。Next, A14 is oxidized by exposing it to an oxidized plasma atmosphere to form alumina A/*Os (FIG. 1(C)).
次にレジスト１５をマスクとして、 Ａｌ、０． １４
を塩素ガスを用いたＲＩＥで垂直加工を行なう（第１図
ｃｄ））。Next, using the resist 15 as a mask, Al, 0. 14
Vertical processing is performed by RIE using chlorine gas (Fig. 1 c)).
さらにレジスト１５を除去した後、 ＡＪｆｆｉＯｓ
１４をマスクとして第１層金属配＠膜１３をイオンビー
ムエツチングにより加工する（第１図ｒｅ） ） ａ層
間絶縁膜１６を堆積した後、第２１ｉ！金稿配縁膜１７
を堆積し、第１図（ａ）〜（ｅ）のプロセスを繰り返す
ことによって２層配線１７を形成する（第１図【ｆ））
。After further removing resist 15, AJffiOs
14 as a mask, the first layer metal interconnection film 13 is processed by ion beam etching (FIG. 1re)) After depositing the interlayer insulating film 16, the 21i! Gold paper lining film 17
By repeating the processes shown in FIGS. 1(a) to (e), a two-layer wiring 17 is formed (FIG. 1[f)).
.
さらに上記プロセスを繰り返すことによって。By repeating the above process further.
３＠以上の多層配線の形成も可能である。It is also possible to form multilayer wiring of 3@ or more.
その他の実施例としてＡ１１４を事前に酸累プラズマに
さらして酸化させなくても、アルゴン（Ａｔ）と酸累（
０りの混合ガスによるイオンビームエツチングを行なう
ことによっても、Ａ１１４を酸化させアルミナＡ／、０
．にすることが可能であり同様の加工ができる。As another example, A114 can be oxidized by argon (At) and oxidized plasma without having to be oxidized by exposing A114 to an oxidized plasma in advance.
By performing ion beam etching with a mixed gas of 0, A114 is oxidized and alumina A/, 0 is oxidized.
．． It is possible to perform similar processing.
上記実施例ではＯａ Ａ ８半導体装置の場合について
説明したが、本発明はその他の化合物半導体装置や８１
半導体装置についても同様に適用することができる。Although the above embodiment describes the case of an Oa A 8 semiconductor device, the present invention is applicable to other compound semiconductor devices and 81
The same can be applied to semiconductor devices.
以上述べたように本発明によれば、Ａｌｌ系金属のエシ
チングマスクにアルミナＡｌ！、０．を用いることによ
って最上層及び最上層をＴｉとしたＡｕ系多層金属膜を
制御性良く加工でき、多層配線を可能として信頼性の高
−高集積化半導体装置を得ることができる。As described above, according to the present invention, an alumina Al! ,0. By using this method, it is possible to process an Au-based multilayer metal film with Ti as the top layer and top layer with good controllability, and it is possible to form multilayer interconnections and obtain a highly reliable and highly integrated semiconductor device.
第１図は本発明の一実施例による半導体集積回路の形成
方法を示す図、第２図は従来の形成方法を示す図である
。
１１・−・ＧＦＩＡＳ基板％ １２−ｓｉｏ、膜、１３
−・・第１＠金属配線膜、１４・・・Ａ／％１５・・・
フォトレジスト、１６・・・１脅間絶縁膜、１７・・・
第２層金属配線膜。
代理人 弁理士 則 近 憲 重
量 竹 花 喜久男
ｃ′７）
！？１１［ｆ］
第↓凶
第 ２ ＠FIG. 1 is a diagram showing a method of forming a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional forming method. 11--GFIAS substrate% 12-sio, film, 13
-...1st@metal wiring film, 14...A/%15...
Photoresist, 16...1 Insulating film, 17...
Second layer metal wiring film. Agent Patent Attorney Nori Chika Kikuo Takehana c'7)! ? 11 [f] No. ↓ No. 2 @
Claims (3)
上のＡｕ系金属配線を形成するに際し、３層以上からな
る金属膜が、少なくとも絶縁膜と接する最下層及び最上
層の金属を絶縁膜と密着性の良いＴｉ等の金属であるＡ
ｕ系金属であり、該Ａｕ系多層金属膜をエッチング加工
する際のエッチングマスクにアルミナ（Ａｌ＿２Ｏ＿３
）を用いることを特徴とする多層配線用金属膜の形成方
法。(1) When forming at least one or more layers of Au-based metal wiring on a semiconductor substrate via an insulating film, a metal film consisting of three or more layers covers at least the bottom layer and the top layer of metal that are in contact with the insulating film. A is a metal such as Ti that has good adhesion to
It is a u-based metal, and alumina (Al_2O_3) is used as an etching mask when etching the Au-based multilayer metal film.
) A method for forming a metal film for multilayer wiring, the method comprising:
層した後、酸素プラズマ雰囲気に置くことによってＡｌ
を酸化させＡｌ＿２Ｏ＿３としてエッチングマスクとす
ることを特徴とする特許請求の範囲第１項記載の多層配
線用金属膜の形成方法。(2) Following the above multilayer metal film, Al is laminated by continuous sputtering, and then placed in an oxygen plasma atmosphere.
2. The method of forming a metal film for multilayer interconnection according to claim 1, wherein Al_2O_3 is oxidized and used as an etching mask.
グであることを特徴とする特許請求の範囲第１項記載の
多層配線用金属膜の形成方法。(3) The method for forming a metal film for multilayer wiring according to claim 1, wherein the etching method is ion beam etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8491986A JPS62242337A (en) | 1986-04-15 | 1986-04-15 | Formation of metal film for multilayer interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8491986A JPS62242337A (en) | 1986-04-15 | 1986-04-15 | Formation of metal film for multilayer interconnection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62242337A true JPS62242337A (en) | 1987-10-22 |
Family
ID=13844119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8491986A Pending JPS62242337A (en) | 1986-04-15 | 1986-04-15 | Formation of metal film for multilayer interconnection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62242337A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63219591A (en) * | 1987-03-09 | 1988-09-13 | Agency Of Ind Science & Technol | Ion beam resist and production thereof |
| JPS6468946A (en) * | 1987-09-09 | 1989-03-15 | Nec Corp | Manufacture of semiconductor device |
| JPH0330428A (en) * | 1989-06-28 | 1991-02-08 | Hitachi Ltd | Formation of wiring substrate |
| US5416971A (en) * | 1991-07-18 | 1995-05-23 | Hegazi; Gamal M. | Method of assembling a monolithic gallium arsenide phased array using integrated gold post interconnects |
| JP2009111387A (en) * | 2007-10-26 | 2009-05-21 | Samsung Techwin Co Ltd | Method of manufacturing printed circuit board, and printed circuit board manufactured by the same |
-
1986
- 1986-04-15 JP JP8491986A patent/JPS62242337A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63219591A (en) * | 1987-03-09 | 1988-09-13 | Agency Of Ind Science & Technol | Ion beam resist and production thereof |
| JPS6468946A (en) * | 1987-09-09 | 1989-03-15 | Nec Corp | Manufacture of semiconductor device |
| JPH0330428A (en) * | 1989-06-28 | 1991-02-08 | Hitachi Ltd | Formation of wiring substrate |
| US5416971A (en) * | 1991-07-18 | 1995-05-23 | Hegazi; Gamal M. | Method of assembling a monolithic gallium arsenide phased array using integrated gold post interconnects |
| JP2009111387A (en) * | 2007-10-26 | 2009-05-21 | Samsung Techwin Co Ltd | Method of manufacturing printed circuit board, and printed circuit board manufactured by the same |
| JP4705143B2 (en) * | 2007-10-26 | 2011-06-22 | 三星テクウィン株式会社 | Method for manufacturing printed circuit board |
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