JPH0330428A - Formation of wiring substrate - Google Patents

Abstract

PURPOSE:To contract a protrusion on a wiring and avoid a shortcircuit between wirings for assuring the technology of enhancing the electrical reliability by a method wherein first and second specific metallic films are respectively laminated; a specific laminated mask is formed thereon; the second metallic film is physically etched away; and then the first metallic film is chemically etched away. CONSTITUTION:A first metallic film 17A comprising metal(s) of group IVa, group Va or group VIa etc. and a second metallic film 17B comprising metal(s) of group VIII or group 1b etc. are successively laminated on the whole surface of an underneath insulating film 15 on a substrate. Next, a laminated mask 30 having a first mask 30A used for etching away the first metallic film 17A as well as a second mask 30B in the same pattern as that of the first mask 30A used for etching away the second metallic film 17B is formed. Finally, the second mask 30B of the laminated mask 30 is used to mainly and physically etch away the second metallic film 17B in the region excluding the second mask 30B and then the first mask 30A is used to mainly and chemically etch away the first metallic film 17A in the region excluding the first mask 30A so that a wiring 17 comprising the residual first metallic film 17A and the second metallic film 17B may be formed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a wiring forming technology, and in particular, the configuration (1) relates to a wiring forming technology in which a metal of the RB group or a compound containing this metal as a main component is used as a wiring material. It relates to techniques that can be applied and are effective.

[Conventional technology]

A 110aAs IC is being developed in which MESFETs are integrated on the main surface of a semi-insulating substrate made of GaAs (gallium arsenide). This GaAs IC has higher electron mobility than Si IC, so it is superior in high speed.

In GaAs IC, the wiring connecting between MESFETs is Au.
Alternatively, it is formed mainly of Au. , MESFET
AuGe is generally used for the source electrode and drain electrode of the device, and the wiring is made of Au for ohmic connection to the electrode. Further, the electrodes are the source region and drain region (GaAs) of the MESFET.
) is made of AuGe for ohmic connection. Regarding this type of GaAs IC,
For example, PROCEEDINGS OF THE IE
EE, VOL76, NO, 7, JULY (1988),
pp792-815. “MakingGaAs In
tegratad C1rcuits”.

Although the Au wiring of the GaAs IC that the present inventor is currently developing is not a known technique, it is formed by the following formation method as shown in FIGS. 8 and 9 (cross-sectional views of main parts shown for each manufacturing process). There is.

First, as shown in FIG. 8, the wiring 2 is formed on the glabella insulating film (base insulating film) 1 covering elements such as MESFETs.

This wiring 2 is connected from the surface of the interlayer insulating film 1 to the Mo film 2A and the Au film.
It is composed of a three-layer laminated film in which the film 2B and the Mo film 2C are sequentially laminated. The Mo film 2A in the lower layer of the arrangement 12 is formed for the purpose of improving the adhesion between the interlayer insulating film 1 and the Au film 2B. The upper MO film 2C is the upper eyebrow insulation film (3)
This is formed for the purpose of increasing the adhesion between the film and the Au film 2B. A
u 3I2 B is formed as the main part of the wiring 2, and is formed with a thickness of, for example, ICμm]Cμm.

This processing (patterning) of the wiring 2 is performed by etching using an etching mask 5. The etching mask 5 is formed using a photoresist II (photosensitive resin film) formed by photolithography, and has a film thickness of, for example, about 1.0 to 2.0 μml. The lower layer MovA2A of the wiring 2 and the upper layer Mo film 2C are each processed using reactive ion etching (RIE). On the other hand, since the Au film 2B has poor chemical reactivity, it is processed using sputter etching such as ion milling. When processing the Au film 2B of the wiring 2, as shown in FIG. 8, a redeposited layer 2D of Au and MO is generated on the side wall of the etching mask 5 by sputter etching.

As shown in FIG. 9, the re-deposition layer 2D becomes protrusions 2d when the etching mask 5 is removed. This protrusion 2d is generated with a size corresponding to the film thickness of the etching mask 5, and is approximately 0.3~0.3 to 0.3 in the height direction from the wiring 2.
1.50 μm].

[Problem to be solved by the invention]

Projection 2d formed on the wiring 2 of the GaAs IC mentioned above
As shown in FIG. 10 (cross-sectional view of main parts), the interlayer insulating film 3 is deformed during the deposition of the interlayer insulating film 3 on the wiring 2, causing a short circuit between the wirings 2 on the same layer. Further, an upper layer wiring 4 is provided on the interlayer insulating film 3.
In the case of a two-layer wiring structure provided with
A short circuit occurs between the wiring 4 and the wiring 4 in the upper layer. For example, the wiring 4 in the upper layer is the wiring in the lower layer! 2, Mo film 4A, Au film 4
It is formed of a three-layered laminated film in which Mo films B and 4C are sequentially laminated. Therefore, there was a problem in that the electrical reliability of the GaAs IC deteriorated.

An object of the present invention is to provide a technology that can prevent short circuits between wirings and improve electrical reliability in the wiring formation technology described above.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique that can reduce the size of protrusions that occur in wiring and achieve the above object.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In the wiring formation technology, a first metal layer formed of a metal of the IVa group, Va group, or VIa group or a compound containing this metal as a main component is formed on the entire surface of the base insulating film on the substrate. a step of sequentially laminating second metal films each made of a group metal or a compound containing this metal as a main component; and etching the first metal film on the second metal film. a first mask and the second mask formed thereon;
A step of forming a laminated mask having a second mask having the same pattern as the first mask, which is used when etching a metal film; Physically etching the film
The method further includes a step of chemically etching the remaining first metal film using a mask to form a wiring formed of the remaining first metal film and second metal film. ■The a group metal of the first metal film of the wiring is Ti, and the Va group metal is Ta and VIa.
Group metals are Cr, Mo, and W. The second metals of the wiring are Pt and Ni, and the Ib group metals are Au and Cu.

Further, the first mask of the laminated mask is made of group (Pt, Ni)
), Ib group (Au, Cu) or IIIb group (Afl) metal, a compound mainly composed of this metal, or silicon oxide, and the second mask is made of IVa group (Ti), Va group (Ta). The precept is formed of a group VIa metal (Cr, Mo, W) or a compound containing this metal as a main component.

[For production]

According to the above-described means, the first mask of the laminated mask ensures a sufficient etching rate for the first metal film,
The film thickness of the first mask can be made thin, and the second mask can ensure a sufficient etching rate for the second metal film.
Since the film thickness of the second mask can be reduced and, as a result, the film thickness of the laminated mask can be reduced, the second mask can be made thinner.
It is possible to reduce the size of the protrusions (31) in the height direction that adhere to the side walls of the laminated mask during physical etching of the metal film. Since it is possible to prevent short circuits between the wires, the electrical reliability of the wiring formation technique can be improved.

Hereinafter, the structure of the present invention will be described together with an embodiment in which the present invention is applied to a GaAs IC wiring formation technique.

In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

(Example I) The structure of a GaAs IC which is Example I of the present invention is shown in FIG. 1 (a sectional view of the main part).

As shown in FIG. 1, a GaAs IC is constructed by integrating elements such as MESFETQ on the main surface of a semi-insulating substrate 10 made of a GaAs substrate.

MESFETQ includes an n-type semiconductor region 11 and a pair of n-type semiconductor regions 11.

It is composed of a type semiconductor region 12 and a gate electrode 13.

The n-type semiconductor region 11 constitutes a channel formation region.

The pair of Go-type semiconductor regions 12 constitute a source region and a drain electrode. The gate electrode 13 is made of, for example, W, WSix
It is made of metals such as

A source electrode 14 is provided on the main surface of the A-type semiconductor region 12 that is the source region of this MESFETQ, and a drain electrode 14 is provided on the main surface of the Go-type semiconductor region 12 that is the drain region. For example, each of the source electrode 14 and the drain electrode 14 is made of AuG from the surface side of the n° type semiconductor region 12.
It is composed of a three-layer laminated film in which an e film 14A, a Ni film 14B, and an Au film 14C are laminated in sequence. Source electrode 1
4. A u G e of each lower layer of the drain electrode 14
1114A is configured mainly for the purpose of making an ohmic connection with the d-type semiconductor region 12. The upper layer Au film 14C is configured for the purpose of ohmic connection with the first layer wiring (17) connected to the source electrode 14 and the drain electrode 14, respectively.

Each of the source electrode 14 and the drain electrode 14 is connected to the first layer wiring 1 extending on the interlayer insulating film 15 through a connection hole 16 formed in the interlayer insulating film (base insulating film) 15.
Connected to 7. The glabellar insulating film 15 is mainly composed of, for example, a silicon oxide film.

The first layer wiring 17 extends from the surface side of the interlayer insulating film 15 by M
It is composed of a three-layer stacked film in which an O film 17A, an Au film 17B, and a Mo film 17C are sequentially stacked. Mo1117A in the lower layer of the wiring 17 is formed for the purpose of increasing adhesiveness with the underlying interlayer insulating film 15. Upper layer Mo1l17A
is configured for the purpose of increasing adhesion to the upper glabella insulating film (18). The intermediate layer Au1117B is configured as the main body of the wiring 17. The wiring 17 is connected to the source electrode 14,
In particular, the intermediate layer is formed of the Au film 17B so that an ohmic connection can be made even when alloyed with each of the drain electrodes 14.

Further, each of the lower layer and the upper layer of the wiring 17 may be formed of other metal materials. For example, each of the lower layer and the upper layer may be formed of Ti of the IVa group, Ta of the Va group, Cr other than the above-mentioned Mo of the VIa group, or is W, or a compound of these metals such as TiW
It can be formed by

Further, the intermediate layer of the wiring 17 can be similarly formed of other metal materials. For example, the middle layer is Ni, P of the ■ group.
It can be formed of Cu other than the above-mentioned Au of group Ib or group Ib, or a compound of these metals.

The first layer wiring 17 passes through the connection hole 19 formed in the interlayer insulating film 18. It is connected to the second layer wiring 20 extending on the second glabellar insulating film 18 . Like the interlayer insulating film 15, the interlayer insulating film 18 is mainly composed of a silicon oxide film.

The second layer wiring 20 is similar to the first layer wiring 17.
Mo film 20A, Au1 [2
It is composed of a three-layer stacked film in which 0B and Mo films 20C are sequentially stacked.

First layer guide! ! A passivation film 21 is provided on the upper layer of 20.
is provided. The passivation film 21 is formed of a silicon oxide film, a silicon nitride film, or a laminated film of a combination thereof.

Although the GaAs IC of this example is not limited to this,
2 consisting of first layer wiring 17 and second layer wiring 20
Consists of layer wiring structure.

Next, a detailed method for forming the wiring of the GaAs IC will be explained in FIGS. 2 to 61! A brief explanation will be given using FIG.

First, the first layer wiring 17 (or the second layer wiring 20) is formed over the entire surface of the interlayer insulating film 15. M.

The film 17A, the Au film 17B, and the Mo film 17G are sequentially laminated. The lower Mo film 17A is deposited by, for example, a sputtering method, and has a thickness of about 200 [nm]. The intermediate layer Au film 17B is deposited, for example, by sputtering,
It is formed with a film thickness of approximately 1°0 [μm].

The upper layer Mo1m117C is deposited by, for example, a sputtering method, and is formed to have a thickness of about 100 [nm].

Next, as shown in FIG. 2, a laminated mask 30 is formed on the upper MO film 17C. The laminated mask 30 has an upper layer of Mo.
It is formed of a laminated film in which a first mask forming film 30A, a second mask forming film 30B, and a third mask 30C are sequentially laminated on the surface of the film 17G.

The first mask forming film 30A in the lower layer of the laminated mask 30 is formed to form an etching mask for the MOI [17A] in the lower layer of the first layer mark 41117. The first mask forming film 30A is made of Au deposited by sputtering, for example.
Formed by a membrane. Since Au1ll can ensure a sufficient etching rate for chemical etching of the Mo film 17A, it can be formed as a thin film of about 50 nm. In addition, the first mask forming film 30A may be formed of an Au film, Ni of group Ⅰ, Pt, Cu of group Ib, or a compound of these metals. It may be formed with a IIIb group /11 film, and the first mask forming layer 30A may be formed with a silicon oxide film.

The second mask forming film 30B of the intermediate layer of the laminated mask 30 is
A u 1l1117 of the intermediate layer of the first layer wiring 17
This is formed to form an etching mask for B.

The second mask forming film 30B is formed of, for example, a W film deposited by sputtering. Since the W film can ensure a sufficient etching rate for the physical etching of the Au film 17B, it can be formed as a thin film with a thickness of approximately nm. Further, the second mask forming vA3OB may be formed outside the W film by using Ti of group ①a, Ta of group Va, MO or Cr of group Vla, or a compound of these metals, such as TiW.

The upper third mask 30B of the laminated mask 30 is formed of a photoresist (photosensitive resin film) formed by photolithography, for example. The third mask 30C patterns the intermediate layer second mask forming film 30B and the lower layer first mask forming @30A of the laminated mask 30, and
The Mo film 17C, which is the upper layer of the layer wiring 17, is formed at least as thick as the patterning. Third mask 30C
is formed with a film thickness of, for example, about 1.5 [μm]. This third mask 30C is in a state where it is patterned in the shape of the first layer wiring 17.

Next, as shown in FIG. 3, using the third mask 30C in the upper layer of the laminated mask 30, the second mask forming film 30B in the middle layer of the laminated mask 30, and the first mask forming film 1113 are formed.
0A and the upper Mo film 17C of the first layer wiring 17 are sequentially patterned. Said second mask formation I! l!
By patterning 30B, the second mask 30B is formed using the second mask forming film 30B remaining under the third mask 30C. Further, by patterning the first mask forming film 30A, the first mask 30A is formed using the first mask forming film 30A remaining under the second mask 30B.

A second mask forming film 3 which is an intermediate layer of the laminated mask 30
0B and the Mo film 17C on the upper layer of the first layer wiring 1717 are patterned mainly by chemical etching. Here, chemical etching mainly includes a method in which a chemical mode and a physical mode (sputter etching) proceed simultaneously, such as reactive sputter etching. Etching uses reactive sputter etching using, for example, an F-based gas mixed with CF, gas, and O8 gas. In addition, as an etching gas, F such as NF, SF, etc.
system gas or CC02F2. CQ2. CQ of CCU, etc.
A system gas may also be used. Since Mo, W, etc. react with each of F and CQ and evaporate, re-deposition does not occur.

The first mask forming film 30A in the lower layer of the laminated mask 30 is patterned by physical etching. As the physical etching, for example, sputter etching using A, R gas is used. During sputter etching of the first mask forming film 30A, Au of the first mask forming film 30A, W of the second mask 30B, and the MO film 1 of the upper layer of the first layer wiring 17 are etched.
Although the Mo of 7C is slightly re-deposited on the side wall of the third mask 30C, since the Au of the first mask forming film 30A is formed with a thin film thickness, almost no re-deposition layer is generated.

Next, the upper third mask 30C of the laminated mask 30 is removed. This third mask 30 is removed by dry etching using O2 gas, for example.

Next, using the second mask 30B of the intermediate layer of the laminated mask 30, as shown in FIG. 4, the Au film 17B of the intermediate layer of the first layer wiring 17 is patterned. Since chemical etching cannot be used for Au1117B, physical etching is used. For example, sputter etching using a mixed gas of Ar gas and 62 gas is used as the physical etching. In this sputter etching, the Au film 17B=second mask 3
Since the etching rate of 0B can be set to 10 to 20:1, the film thickness of the second mask 30B can be made sufficiently thin.

As shown in FIG. 4, when sputter etching the Outt 117B, Au of the Au film 17B, Mo of the MO film 17C above it, etc. are removed from the first mask 30A and second mask 30B of the laminated mask 30. It reattachs to each side wall, producing protrusions (parallels) 17d. This protrusion 17d
Since each of the first mask 3OA and the second mask 30B is thin, the first mask 3OA and the second mask 30B are
The film is formed in a small size corresponding to the film thickness of each film. Considering that the thickness of the second mask 30B is slightly reduced by sputter etching, the protrusion 17d has a small size with a height of about 50 to 120 nm in the thickness direction of the laminated mask 30. It is formed.

Next, as shown in FIG. 5, chemical etching is mainly applied to the entire surface of the substrate to remove the second mask 30B of the laminated mask 30 and remove the Mo film 17A below the first layer wiring 17.
pattern. By patterning the lower Mo film 17A, the first layer wiring 17 having a three-layer structure consisting of the Mo film 17A, the Au layer 17B, and the Mo film 17G is completed. The chemical etching removes the upper layer of Mo@17.
Dry etching (reactive sputter etching) is used as well as chemical etching to pattern C. Furthermore, even if the second mask 30B is lost due to etching during patterning of the lower Mo film 17A, the first mask 30A under it acts as an etching mask.

Next, as shown in FIG. 6, the first mask 30 remaining after the laminated mask 30 is removed by physical etching. This physical etching uses sputter etching similar to the physical etching for patterning the intermediate layer of Au [17B of the first layer wiring 17. This first
By removing the mask 30, the small protrusions 17d generated on the first layer wiring 17 become even smaller.

The GaAs IC of this example has a two-layer wiring structure.

Since the second layer interconnection 1!20 is formed by a method substantially similar to that of the first layer interconnection 17 described above, the method for forming the second N-th interconnection 20 will be omitted.

In this way, in the wiring formation technology, the semi-insulating base i
F! A step of sequentially laminating each of Mo film 17A (or 20A) and Au@17B (or 20B) on the entire surface of the glabella insulation 11115 (or 18) on i10, and this Au film 1
7B, the first mask 30A used when etching the Mo film 17A and the first mask 30A formed thereon.
The first film used when etching the u film 17B
A step of forming a laminated mask 30 having a second mask 30B having the same pattern as the mask 30A, and a step of forming the laminated mask 3
The remaining Mo film 17B is physically etched using the second mask 30B of 0.0, and the remaining Mo film 17A is mainly chemically etched using the first mask 30A. 17A and a step of forming a first layer wiring 17 made of Au1117B. With this configuration, the first mask 30A of the laminated mask 30 can ensure a sufficient etching rate with respect to the Mo film 17A, the film thickness of the first mask 30A can be made thin, and the second
The mask 30B can ensure a sufficient etching rate with respect to the AU film 17B, and the thickness of the second mask 30B can be reduced, and as a result, the thickness of the laminated mask 30 can be reduced. It is possible to reduce the size in the height direction of the protrusions 17d attached to the side walls of the laminated mask 30 during physical etching of the Au film 17B. Therefore, based on the protrusion 17d, the first
Short circuit between layer marks 817 (or 20), first layer marks 817
Since it is possible to prevent a short circuit between the first layer and the second layer wiring 20, the electrical reliability of the wiring formation technique can be improved.

(Example ■) This example ■ is a GaAs IC in the above-mentioned Example I.
This is a second embodiment of the present invention in which the number of wiring formation steps is reduced.

In this embodiment (2), after the step shown in FIG.
Using this third mask 30C, the intermediate layer Au film 17B of the first layer wiring 17 is patterned without removing it. This Au11117B is made of Ar gas and 0. Since patterning is performed by sputter etching (physical etching) using a gas mixture, the third mask 30C is etched together with the etching of the Au 111[17B]. The sputter etching is performed under conditions such that the third mask 30C disappears before patterning of the Au film 17B is completed.

According to this forming method, since the third mask 30 disappears during the sputter etching, it is possible to prevent the protrusion 17d from being generated on the side wall of the third mask 30, and also to remove the third mask 30. Au film 17B
Since it can be used also in the patterning step, the number of steps for forming the first layer wiring 17 can be reduced.

(Example ■) The present Example ■ is the same as that of the above-mentioned Example ■.
This is a second embodiment of the present invention in which the structure of the mask used for processing the C wiring is changed.

Regarding the method for forming a GaAs IC, which is this example (■),
This will be briefly explained using FIG. 7 (a sectional view of main parts in a predetermined manufacturing process).

The first layer wiring 17 of the GaAs IC shown in FIG. 7 is in a patterned state. This patterning of the first layer wiring 17 is performed using a single layer mask 31. The single layer mask 31 is formed of, for example, a silicon oxide film. Since the etching rate between this silicon oxide film and Au is approximately 1:3,
The single layer mask 31 is formed to have a thickness that is at least ⅓ of the thickness of the Au film 17B that is the intermediate layer of the first layer wiring 17. The patterning of the single layer mask 31 is performed using, for example, CHF,
This is mainly done by chemical etching (reactive sputter etching) using gas.

The single layer mask 31 is basically not removed after the first layer wiring 17 is patterned.

That is, it remains at the stage when the GaAs IC is completed. However, if necessary, the mask 31 may be removed.

By patterning the first layer wiring 17 using the single layer mask 31 in this manner, the number of steps for forming a mask for patterning the first layer wiring 17 can be reduced. Further, by leaving the single layer mask 31 on the first layer wiring 17, it is possible to improve the adhesion between the first layer wiring NlA 17 and the upper glabellar insulating film 18.

(Example 2) This example 2 is a method for removing the protrusion 17d formed in the above-mentioned Example I.

The steps up to the steps shown in FIG. 3 were performed in the same manner as in Example 1, and FIG.
The mask 30C is removed as shown in FIG. After this, as shown in FIG. 4, sputter etching is further performed using Ar gas and 0□ gas. The portion where the protrusion 17d shown in FIG. 4 is formed is shown in FIG. 12 (an enlarged sectional view of the main part).
, the upper part of the mask 30B is than re-deposited by sputtering.

A surface 17e on which etching progresses appears. Moreover, a protrusion 17d to be reattached appears at the lower part of the surface 17e where the etching progresses. Compared to Example I above.

By increasing the etching time of the Au film 17B (or decreasing the film thickness of the mask 30B), the protrusions 17d
can be removed.

Specific wiring 17 sputter etched under these conditions
The cross-sectional structure of the mask 30 is shown in FIG. 13 (cross-sectional view of the main part).
7s increases, and the protrusions 17d conversely decrease and disappear.

After etching the Au film 17B, processing is performed in the same manner as in Example I, resulting in an arrangement having the cross-sectional shape shown in FIG.
lA17 is formed. In the step shown in FIG. 6 of the embodiment (2), the protrusion 17d remains on the wiring 17, but in this embodiment, the protrusion 17d does not exist. Conversely, the upper part of the wiring 17 is scraped off due to the retreat of the mask 30B, resulting in the inclined surface 1.
7f is formed. This inclined surface 17f and the interlayer insulating film 15
The angle α formed with the surface of the semi-insulating substrate 10 (or the semi-insulating substrate 10) varies slightly depending on the etching film, mask, etc., but for example, 20
~60 degrees.

An inclined surface 17g is formed at the bottom of the wiring 17. This inclined surface 17g and the interlayer insulating film 15 (or semi-insulating substrate 10)
The angle β with the surface is, for example, 60 to 80 degrees. In other words, the angle α is smaller than the angle β.

In this way, according to this embodiment (2), the protrusion 1 is placed on the wiring 17.
7d does not exist, the interlayer insulating film 18 and the upper layer wiring 2
0 each step coverage is improved. Moreover, defects caused by the protrusion 17d can be prevented.

Note that if the sputter etching time using the Ar gas and O2 gas is increased.

In the arrangement i@17, the inclined surface 17g disappears and only the inclined surface 17f exists. The wiring 17 configured in this manner can further improve the step coverage described above.

The invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is as follows.

It goes without saying that the invention is not limited to the embodiments described above, and that various changes can be made without departing from the spirit thereof.

For example, in the present invention, the first layer wiring 17 (or 20) is
It is also possible to have a two-layer structure in which the O 1117A and the Au film 17B are sequentially laminated, that is, the first layer wiring 17 must have at least adhesive properties with the underlying interlayer insulating film 15. Bye.

Further, the present invention provides the first layer wiring 17, the second layer wiring [
20 respectively, Ti/Au/Ti, Ti/Au/Tie
, W/Au/W, Ti/Cu/Ti.

Cr/Cu/Cr, TiW/Cu
/ Ti W or Ti / Ni / Ti.

Further, the present invention is not limited to GaAs ICs, but can be applied to wiring boards, such as printed wiring boards, having wiring formed mainly of metals of Group I or Group Ib or their compounds.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In wiring formation technology, short circuits between wirings can be prevented and electrical reliability can be improved.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part of a GaAs IC which is Example I of the present invention, and FIGS. 2 to 6 are new views of main parts showing each manufacturing process of the GaAs IC. FIG. 7 is a sectional view of a main part of a GaAs IC according to the embodiment (1) of the present invention in a predetermined manufacturing process, and FIGS. 8 to 10 are sectional views of a main part of a conventional GaAs IC at each manufacturing process. , FIGS. 11 to 14 show Ga
FIG. 3 is a cross-sectional view of a main part in a predetermined manufacturing process of As IC. In the figure, 10... Semi-insulating substrate, Is, 1B... Interlayer insulating film, 17... First layer wiring, 17A, 17C,
20A, 20C...MO film, 17B, 20B -
Au film, 20... Second layer wiring, 30... Laminated mask, 30A... First mask, 30B... Second mask, 30C... Third mask, 31... Mono It is a layered mask.

Claims (6)

[Claims] 1. IVa group, Va group or VIa group on the base insulating film on the substrate.
A first metal film formed of a group metal or a compound containing this metal as a main component, and a second metal film formed of a group VIII or Ib metal or a compound containing this metal as a main component. A method for forming a wiring board having sequentially laminated wiring, the method comprising: sequentially laminating each of the first metal film and the second metal film on the entire surface of the base insulating film on the substrate; A first mask used when etching the first metal film and a pattern identical to the first mask used when etching the second metal film formed thereon are placed on the metal film. A step of forming a laminated mask having a second mask, and using the second mask of the laminated mask, mainly physically etching the second metal film in other areas, and using the first mask, etching the second metal film in other areas. 1. A method for forming a wiring board, comprising the steps of mainly chemically etching a first metal film and forming wiring formed of the remaining first metal film and second metal film. 2. The first mask of the laminated mask is made of a group VIII, Ib, or IIIb metal, a compound containing this metal as a main component, or silicon oxide, and the second mask is made of a group IVa, Va, group metal.
2. The method for forming a wiring board according to claim 1, wherein the wiring board is formed of a group metal or a group VIa metal or a compound containing this metal as a main component. 3. 2. The method of forming a wiring board according to claim 1, wherein the laminated mask is formed of a silicon oxide film. 4. 4. The wiring is formed of a laminated film in which a third metal film made of the same kind of metal as the first metal film is provided on a second metal film. A method for forming each wiring board. 5. 5. The wiring according to claim 1, wherein the wiring has a protrusion having a height of one-third or less of the film thickness thereof, and the protrusion is formed on the upper end side of the wiring. A method of forming each wiring board. 6. The side surface of the wiring is formed in two stages with different angles between the lower side surface and the upper side surface of the substrate, and the angle between the lower side surface and the surface of the substrate is the same as the angle between the upper side surface and the surface of the substrate. 5. The method of forming a wiring board according to claim 1, wherein the angle between the lower side surface and the surface of the substrate is 90 degrees or less.