KR100477141B1 - Method for manufacturing a semiconductor device comprising a metal film and an insulating layer thereon - Google Patents

Abstract

The gate pattern of the liquid crystal display device, the gate electrode, the gate pattern of the gate pad and the data wiring of the liquid crystal display, and the data pattern of the data pad and the source / drain electrode are formed by using a single layer of chromium, molybdenum or molybdenum alloy or a combination thereof do. At this time, contact holes are formed simultaneously on the gate electrode, the drain electrode, and the data pad using photoresist as a mask. When dry etching the portion where only the protective film is formed and the portion where the protective film / gate insulating layer is formed at the same time, the following three methods are applied. Firstly, a _two- step etching method of exposing the molybdenum-tungsten alloy film with only O ₂ + CF ₄ gas; secondly, a two-step etching method of partially etching under SF ₆ + HCl and finishing the remaining part with O ₂ + CF ₄ , Finally, after partial etching with SF ₆ + HCl or O ₂ + CF ₄ gas, the polymer is formed in plasma using a gas of carbon tetrafluoride (CF ₄ ) and hydrogen (H ₂ ) or hydrogen chloride (HCl), and then O There is a three-step dry etching method that finishes with ₂ + CF ₄ gas. At this time, the SF ₆ + HCl gas improves the etch profile for the molybdenum-tungsten alloy film and the protective film, the O ₂ + CF ₄ gas is because the etching ratio to the molybdenum-tungsten alloy film is very small that the molybdenum- tungsten alloy film is etched And the polymer membrane is prevented from being etched into the side portion. Here, in order to minimize the etching of the molybdenum tungsten alloy film, the ratio of CF ₄ and O ₂ is preferably 10: 4 or less.

Description

A method of manufacturing a semiconductor device comprising a metal film and an insulating layer thereon

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a metal film and an insulating layer thereon.

In general, since the wiring of the semiconductor device is used as a means for transmitting a signal, it is required to suppress signal delay and disconnection.

As a method of preventing disconnection, a method of forming a plurality of wirings has been proposed, but not only different etching solutions are required to form multilayer wiring, but also several etching processes are required.

As a method of preventing signal delay, a material such as aluminum (Al) or aluminum alloy (Al alloy) having low resistance is generally used. However, when using aluminum or aluminum alloys, it is necessary to add anodization processes to reinforce the weak physical properties of aluminum. In addition, in the case of reinforcing aluminum using ITO (indium tin oxide) in the pad part as in the liquid crystal display device, there is a problem in that the contact property between aluminum or an aluminum alloy and ITO is poor, and another metal must be interposed therebetween.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a wiring alloy in which each layer has a similar etching ratio under the same etching conditions even when the wiring is formed in multiple layers, thereby simplifying the manufacturing process of the semiconductor device and the characteristics of the product. It is the task to improve.

Another object of the present invention is to smooth the edge inclination angle of the contact hole exposing the conductive film or the metal wiring and to prevent the etching of the conductive film under the contact hole.

The wiring according to the present invention can be processed into a taper shape under the same etching conditions and a double conductive film having a taper angle in the range of 20 to 70 °, or an etching of the upper conductive film than the etching ratio of the lower conductive film under the same etching conditions. It consists of a double electrically conductive film with a ratio of about 70-100 Pa / sec.

Here, when the etching method is wet etching, the same etching conditions mean using the same etching solution.

The conductive film is composed of a lower conductive film having a low resistivity of 15 μΩcm or less and an upper conductive film made of a pad material. Here, the material for the pad means a material having properties that can be used as the pad. The characteristics will be described in the Examples.

Here, aluminum or an aluminum alloy is used as the lower conductive layer, and a molybdenum composition or alloy composed of tungsten (W) having an atomic percentage of less than 0.01% to 20%, remaining molybdenum (Mo), and unavoidable impurities is used as the upper conductive layer. do. The composition ratio of tungsten in the molybdenum alloy is preferably 9% to 11%, in particular 10%, in atomic percentage.

Such a molybdenum-containing composition can be used as a single film wiring because the resistivity is as small as 12 to 14 µΩcm and can be used as a pad.

When the conductive film formed on the lower portion is an aluminum alloy, it is preferable that the transition metal or rare earth metal contained is 5% or less.

In wet etching, the etchant is an etchant used to etch aluminum or an aluminum alloy, and for example, CH ₃ COOH / HNO ₃ / H ₃ PO ₄ / H ₂ O, wherein the concentration of HNO ₃ is 8∼. 14% is preferable.

The double conductive layer may be used as a gate line for applying a scan signal or a data line for applying a data signal in the display device.

In the method of manufacturing a wiring according to the present invention, a lower conductive film is stacked on an upper substrate, and an upper conductive film is stacked on the lower conductive film by an etching ratio of about 70 to 100 kPa / sec larger than that of the lower conductive film under the same etching conditions. Next, the upper conductive film and the lower conductive film are simultaneously etched to complete the wiring.

The method for manufacturing a wiring made of such a double conductive film can also be applied to a method for manufacturing a gate line for applying a scan signal or a data line for applying a data signal in the method for manufacturing a display device.

As described above, a liquid crystal display device may be manufactured using such molybdenum-tungsten wiring.

In the method for manufacturing a thin film transistor substrate for a liquid crystal display according to the present invention, a molybdenum alloy composed of tungsten having an atomic percentage of less than 0.01% to 20%, remaining molybdenum, and unavoidable impurities is laminated, and a molybdenum alloy film is patterned using an etchant to form a gate. A gate wiring including a line, a gate pad, and a gate electrode is formed.

Here, it is also possible to laminate a conductive film made of aluminum or an aluminum alloy under the molybdenum alloy film, and when the molybdenum alloy film is patterned, the conductive film is patterned together.

In addition, in the method of manufacturing a thin film transistor substrate according to the present invention, the data line including the data line, the data pad, and the source / drain electrode is made of molybdenum-containing tungsten with an atomic percentage of less than 0.01% to 20%, and remaining molybdenum and unavoidable impurities. It is formed from a single film of tungsten alloy, chromium or molybdenum, or a combination of these.

In the method of manufacturing a semiconductor device according to the present invention, a photoresist is patterned on an insulating film on a metal film or a metal wiring, and the insulating film is etched using the mask to form two or more contact holes on the metal film. At this time, in order to prevent etching of the metal film under the contact hole of the thinner side with different thickness of the insulating film and etching at a gentle inclination angle, the contact hole is formed in two or three steps.

In the method of forming in two steps, first, partial etching is performed on the photoresist and the insulating film under etching conditions having an etching selectivity of 1: 1 to 1: 1.5, wherein the thickness of the insulating film is a part of the insulating film and the metal film. Is etched. Subsequently, the remaining insulating film is etched under etching conditions in which the etching selectivity between the insulating film and the metal film is 1:15 or more.

In the method of forming in three steps, first, the metal film having the thinner insulating film is etched until the metal film is exposed, and then a polymer film is formed on the exposed surface during etching. Next, the remaining insulating film is etched under etching conditions in which the etching selectivity of the insulating layer and the metal film is 15: 1 or more. Here, the polymer film prevents the insulating film from being laterally etched in the last step.

This method can be applied to a structure in which the first metal film, the first insulating film, the second metal film, and the second insulating film are continuously formed. That is, the first contact hole exposing the second metal film under the second insulating film and the second contact hole exposing the second metal film under the first and second insulating films may be simultaneously formed.

This method can also be applied when forming contact holes for exposing pads for connecting wirings of semiconductor devices to the outside, especially when forming contact holes for exposing gate pads and data pads, respectively, in a thin film transistor substrate. Applicable

In particular, when the metal film is a molybdenum film or a molybdenum-tungsten alloy film, the insulating film is a silicon nitride film, and the insulating film is etched using plasma dry etching, the molybdenum film or molybdenum is used as the gas used in the last step of the two- or three-step etching method. It is preferable to use CF ₄ + O ₂ which can minimize the etching of the tungsten alloy film. In addition, SF ₆ + HCl (+ He) or SF ₆ + Cl ₂ (+ He) is suitable as a gas used in the first step in the two-step etching method.

In addition, when the ratio of CF ₄ and O ₂ is 10: 4 or less, the gate pad and the data pad of the molybdenum film or molybdenum-tungsten alloy film can be simultaneously exposed in one etching step.

DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

As the wiring of the semiconductor device, especially the display device, materials such as aluminum, aluminum alloy, molybdenum, copper, etc. having a low resistivity of 15 μΩcm or less are suitable. On the other hand, the wiring should have a pad for receiving a signal from the outside or transmitting a signal to the outside. The pad material should of course have a resistivity below a certain level, but moreover, it should not oxidize well and should not easily break in the manufacturing process. Aluminum and aluminum alloys have very low resistivity but are not suitable for pad materials. In contrast, materials such as chromium, tantalum, titanium, molybdenum and alloys thereof are suitable for pads but have a higher resistivity than aluminum. Therefore, when the wiring is made, a metal having both characteristics is used, or a low resistance conductive film is used at the bottom and a pad conductive film is used at the top, so that the pad can be used with low resistance.

In addition, when wiring is doubled, the same etching conditions, particularly wet etching, are simultaneously etched using one etchant but processed into a tapered shape having a gentle inclination angle. For this purpose, it is preferable that the same etching liquid has a taper angle in the range of less than 20 to 70 °, or that the etching ratio of the upper conductive film is about 70 to 100 kPa / sec higher than that of the lower conductive film. Moreover, even when wiring is formed by a single film, it is preferable to have a taper angle in the range below 20-70 degrees.

In this process, a molybdenum alloy including tungsten having an atomic percentage of less than 0.01% to 20%, remaining molybdenum, and unavoidable impurities was developed as an alloy for wiring according to an embodiment of the present invention. Here, it is preferable that the composition ratio of tungsten is 5%-15% of atomic percentage, and also 9%-11%.

1 to 3 are graphs showing the characteristics of the molybdenum-tungsten alloy (MoW) according to an embodiment of the present invention.

Figure 1 shows the deposition characteristics of the molybdenum-tungsten alloy according to an embodiment of the present invention, the horizontal axis represents the tungsten content in atomic percentage and the vertical axis represents the thickness deposited per unit power.

As can be seen from FIG. 1, when the content of tungsten is 20 atomic percent or less, the thickness of the molybdenum-tungsten alloy film deposited per unit power ranges from 1.20 to 1.40 (kW / W).

Figure 2 shows the resistivity of the molybdenum-tungsten alloy according to an embodiment of the present invention, the horizontal axis represents the tungsten content in atomic percentage and the vertical axis represents the resistivity accordingly.

As can be seen in Figure 2, the specific resistance (R) of the molybdenum-tungsten alloy according to the content of tungsten (W) was 12.0 ~ 14.0 (μΩcm).

As such, the molybdenum-tungsten alloy containing tungsten with an atomic percentage of 20% or less has a low resistivity of 15 μΩcm or less, so that it may be made of a single film and used as a wiring, but because of its properties as a pad material, aluminum or its It is laminated on top of an alloy or the like and can be used as a wiring. In particular, it can be used as a signal line of the display device, or a gate line or a data line of the liquid crystal display device.

Figure 3 shows the etching rate (etch rate) characteristics of the molybdenum-tungsten alloy according to an embodiment of the present invention, the horizontal axis represents the tungsten content in atomic percentage and the vertical axis shows the degree of etching per unit time for the aluminum etchant will be.

In other words, the degree to which the molybdenum-tungsten alloy thin film is etched per unit time with respect to the etching liquid (HNO ₃ : H ₃ PO ₄ : CH ₃ COOH: H ₂ O) of the aluminum alloy is indicated according to the content of tungsten (W).

As can be seen in FIG. 3, when the tungsten content is 0%, the etch ratio is very large as about 250 (Å / sec), but when the tungsten content is 5%, the etch ratio is about 100 (Å / sec). And it turns out that content of tungsten falls to 50 (Pa / sec) or less between 15 and 20%.

On the other hand, aluminum having very low resistivity or an alloy thereof has an etching ratio of about 40 to 80 (Å / sec) with respect to an aluminum etchant consisting of HNO ₃ (8 to 14%): H ₃ PO ₄ : CH ₃ COOH: H ₂ O. Therefore, when the molybdenum-tungsten alloy film having an etching ratio of about 70 to 100 (Å / sec) is larger than the etching ratio of this level, an excellent double film wiring can be obtained.

4 is a view illustrating an etching profile of a molybdenum-tungsten alloy film according to an embodiment of the present invention.

4 shows a profile obtained by etching a single film of molybdenum alloy using an etchant of an aluminum alloy, and it can be seen that a gentle profile is formed.

That is, a tungsten-molybdenum alloy film 2 containing tungsten having an atomic percentage of 10% on the substrate 1 is deposited to a thickness of about 3,000 kPa, and then etched using an aluminum alloy etchant to produce 20 to 25 ° C. A gentle profile with an angle of was formed.

On the other hand, as can be seen in Figure 3, by adjusting the composition ratio of tungsten to lower the etch ratio of the molybdenum-tungsten alloy film to less than 100 (Å / sec), even for a display device even with a single film made of molybdenum-tungsten alloy It can be used as a gate line or a data line of the liquid crystal display device.

5 to 8 illustrate a double layer profile when a double layer of an aluminum alloy and a molybdenum-tungsten alloy are etched using an etchant of an aluminum alloy. An aluminum or aluminum alloy film 3 is deposited on the substrate 1 to a thickness of about 2,000 kPa, and the molybdenum-tungsten alloy film 2 is deposited to a thickness of about 1,000 kPa on the substrate 1, and then an aluminum etchant is used. The aluminum alloy film 3 and the molybdenum-tungsten alloy film 2 were simultaneously etched.

Here, the aluminum alloy is made of aluminum as a base material, and here transition metals such as Ti, Cr, Ni, Cu, Zr, Nb, Mo, Pd, Hf, Ta, W, or Nd, Gd, Dy, In rare earth metals such as Er, an alloy in which two or three elements are bonded, the contained transition element or rare earth metal has an atomic percentage of 5% or less.

In addition, the etchant used an aluminum etchant (HNO ₃ : H ₃ PO ₄ : CH ₃ COOH: H ₂ O), preferably containing about 8 to 14% nitric acid.

FIG. 5 shows a profile of 30 to 40 ° as the content of tungsten is 5% in the molybdenum-tungsten alloy film, and a profile of 40 to 50 ° in the case of FIG. 6 in which the content of tungsten is 10%. When the tungsten content is 15%, the profile becomes 80 to 90 ° as shown in FIG. 7, and when the tungsten content is 20%, the profile of 90 ° is shown as shown in FIG. 8.

In addition, in the embodiment of the present invention, when etching a double layer of aluminum alloy and molybdenum-tungsten alloy using an aluminum etching solution, stains did not appear after etching.

As described above, when a double film made of an aluminum alloy and a molybdenum-tungsten alloy containing tungsten having an atomic percentage of 20% or less is etched using an aluminum alloy etching solution, a taper angle is formed in the range of 30 to 90 degrees. 6, the most preferable taper angle (40-50 degrees) is formed when tungsten content is about 10%, ie, 9%-11%.

Next, the thin film transistor substrate for a liquid crystal display device using the wiring will be described in detail.

First, a structure of a thin film transistor substrate according to a first exemplary embodiment of the present invention will be described with reference to FIGS. 9A, 9B, and 10. Here, FIG. 10 is sectional drawing of the XX 'line | wire in FIG. 9A.

A gate pattern including a gate line 200, a branch of the gate electrode 210, and a gate pad 220 formed at an end of the gate line 200 is formed on the substrate 100. The gate electrode 210 and the gate pad 220 each consist of a lower aluminum film or an aluminum alloy film 211 and 221 and an upper molybdenum-tungsten alloy film 212 and 222. The gate line 200 is also made of aluminum. Or a double film of an aluminum alloy film and a molybdenum-tungsten alloy film. The gate pad 220 transmits a scan signal from the outside to the gate line 200.

A gate insulating layer 300 is formed on the gate patterns 200, 210, and 220, and the gate insulating layer 300 has a contact hole exposing the molybdenum-tungsten alloy film 222, which is an upper layer of the gate pad 220. Have 720. On the gate insulating layer 300 on the gate electrode 210, a hydrogenated amorphous silicon (a-Si: H) layer 400 and hydrogenated amorphous silicon layers 510 and 520 heavily doped with n + impurities are gate electrodes. It is formed on both sides about 210.

A data line 600 is also vertically formed on the gate insulating layer 300, and a data pad 630 is formed at one end thereof to transmit an image signal from the outside. A source electrode 610, which is a branch of the data line 600, is formed on one doped amorphous silicon layer 510, and a drain electrode is disposed on the doped amorphous silicon layer 520 opposite to the source electrode 610. 620 is formed. The data pattern including the data line 600, the source and drain electrodes 610 and 620, and the data pad 630 may be formed of a molybdenum film or a molybdenum-tungsten alloy film. Meanwhile, in FIG. 9B, a gate auxiliary pad part 640 is further formed on the gate insulating layer 300 near the gate pad 220.

A passivation layer 700 is formed on the data patterns 600, 610, 620, and 630 and the amorphous silicon layer 500 that is not covered by the data pattern, and the passivation layer 700 includes the upper molybdenum layer of the gate pad 220. Contact holes 720, 710, and 730 exposing the tungsten alloy film 222, the drain electrode 620, and the data pad 630 are formed, respectively. In FIG. 9B, a contact hole 740 of the passivation layer 700 is formed on the gate auxiliary pad part 640.

Lastly, the passivation layer 700 is connected to the drain electrode 620 through the contact hole 710, and the pixel electrode 800 made of ITO is formed, and the gate pad 220 exposed through the contact hole 720 is formed. ) Is connected to the data pad 630 through the ITO electrode 810 for the gate pad and the contact hole 730 to transmit a signal from the outside to the gate line 200, and transmits a signal from the outside to the data line 600. A data pad ITO electrode 820 is formed. Meanwhile, in FIG. 9B, the gate pad ITO electrode 810 extends to the gate auxiliary pad part 640 and is connected through the contact hole 740.

As shown in FIGS. 9A and 9B, portions of the gate pad ITO electrode 810 and data pad ITO electrode 820 are substantially directly applied to the pad.

Next, a method of manufacturing the thin film transistor substrate having the structure shown in FIGS. 9 and 10 will be described with reference to FIGS. 11A to 11D. The manufacturing method proposed in this embodiment is a manufacturing method using five masks.

As shown in FIG. 11A, an aluminum film or an aluminum alloy film having a thickness of about 1500 to 2000 microns and a molybdenum-tungsten alloy film having a thickness of about 400 to 600 micrometers are sequentially stacked on the transparent insulating substrate 100, and a photolithography is performed using a first mask. As a result, a gate pattern including the gate line 200, the gate electrode 210, and the gate pad 220 is formed. That is, as shown in FIG. 11A, the gate electrode 210 is an aluminum or aluminum alloy film 211 below and a molybdenum-tungsten alloy film 212 above, and the gate pad 220 is an aluminum or aluminum alloy below. The film 221 and the molybdenum-tungsten alloy film 222 thereon, although not shown in Figure 11a, the gate line 210 is also made of a double film.

Here, the molybdenum-tungsten alloy film is composed of tungsten (W) having an atomic percentage of 0.01% or more and less than 20% and the remaining molybdenum (Mo), and the content of tungsten is preferably 9-11% of the atomic percentage. The aluminum alloy film is made of aluminum and rare earth metal or transition metal of 5% or less. In addition, an aluminum etchant, for example, CH ₃ COOH / HNO ₃ / H ₃ PO ₄ / H ₂ O and the like is used, the content of HNO ₃ is preferably contained in the range of 8-14%.

Further, the gate pattern may be formed as a single film by depositing one of aluminum, aluminum alloy, and tungsten-molybdenum alloy.

As shown in FIG. 11B, the gate insulating layer 300 made of a silicon nitride film, the hydrogenated amorphous silicon layer 400, and the hydrogenated amorphous silicon layer 500 doped with a high concentration of N-type impurities are respectively 3,000 to 3000 thick. After stacking in order of about 5000 Å, 2000 2 2500 Å, 500 Å Å to 700 Å, the doped amorphous silicon layer 500 and the amorphous silicon layer 400 are photo-etched using a second mask.

As shown in FIG. 11C, after a molybdenum-tungsten alloy film including tungsten having an atomic percentage of 0.01% or more but less than 20% is laminated to a thickness of about 3000 to 5000 kPa, the wafer is wet-etched using a third mask to form a data line 600. ), A data pattern including a source electrode 610, a drain electrode 620, and a data pad 630 is formed.

The data pattern may be formed of a single film of one of chromium, molybdenum or molybdenum alloy, or a double film combining these. In addition, an aluminum film or an aluminum alloy film may be added to lower the resistance.

Subsequently, the exposed doped amorphous silicon layer 500 is plasma dry etched using the data patterns 600, 610, 620, and 630 as a mask to separate both sides of the gate electrode 210, while the positively doped amorphous silicon is formed. Expose the amorphous silicon layer 400 between layers 510 and 520.

As shown in FIG. 11D, after the protective film 700 is laminated with silicon nitride (SiN _X ) to a thickness of about 2000 to 4000 μs, the gate pad is photographed together with the gate insulating layer 300 by using a fourth mask. Contact holes 720, 710, and 730 exposing the upper molybdenum-tungsten alloy film 222, the drain electrode 620, and the data pad 630 of 220 are formed.

Here, the gate auxiliary pad part 640 may be additionally formed when the date pattern is formed, and the contact hole 740 of the passivation layer 700 may be additionally formed to have a structure such as 9b.

The process of forming the contact hole will be described in detail.

In the photolithography process using the fourth mask, a photoresist having an opening at a position corresponding to the contact holes 720, 710, 730, and 740 is formed on the upper portion of the protective film 700, and the protective film 700 is formed by a plasma dry etching method using the mask as a mask. ) And the silicon nitride film of the gate insulating layer 300 is etched.

However, in order to smooth the edge inclination of the contact holes 720, 710, 730, and 740, not only the passivation layer 700 and the gate insulating layer 300, but also the photoresist 900 covering them must be etched. To this end, the plasma dry etching method may increase the amount of oxygen (O ₂ ) or use SF ₆ + HCl (+ He) or SF ₆ + Cl ₂ (+ He) in a high frequency power source. However, SF ₆ + HCl (+ He) or SF ₆ + Cl ₂ (etching ratio of about 2,500 to 3,000 Å / min with respect to the silicon nitride and the photoresist 900 of the passivation layer 700 and the gate insulating layer 300 is formed. + He), this gas is etched at about 2,000 mW / min with respect to the molybdenum film or the molybdenum-tungsten alloy film of the gate pad 220 and the date patterns 620, 630, and 640 under the silicon nitride film. Because of the ratio, not only the silicon nitride film which is difficult to selectively etch, but also the molybdenum film or molybdenum-tungsten alloy film beneath it is easy to be etched.

In particular, the molybdenum-tungsten alloy film under the contact holes 710, 730, and 740 is severely over-etched due to the difference in thickness of the film to be etched. That is, since the gate insulating layer 300 and the passivation layer 900 are disposed on the gate pad 220, only the passivation layer 900 is disposed on the data patterns 620, 630, and 640. The molybdenum-tungsten alloy film of) is first exposed and etched.

To solve this problem, a condition in which the molybdenum film or the molybdenum-tungsten alloy film is not etched must be applied. For this purpose, CF ₄ +, a dry etching gas having an etching ratio of 400 μm / min or less with respect to the molybdenum film or molybdenum-tungsten alloy film O ₂ can be used. However, since the etching ratio of the photoresist 900 to CF ₄ + O ₂ is 1,000 μs / min or less, and the etching ratio of the silicon nitride film is 6,000 to 10,000 μs / min, the lower portion of the photoresist 900 with time passes. In this case, the amount of etched side surfaces of the silicon nitride film increases, resulting in undercut, which degrades the silicon nitride etching profile.

Even etching with CF ₄ + O ₂ alone can improve the etching profile by reducing the etching time. At this time, the ratio of CF ₄ and O ₂ is preferably set to 10: 4 or less.

In addition, it may be considered to perform two or three steps of etching as a way to further improve this.

12A to 12B and 13A to 13B show two etching processes, and FIGS. 14A to 14C, 15A to 15C, and 16A to 16C and 17A to 17C show three etching processes.

12A through 12B, 14A through 14C, and 16A through 16C illustrate a process of forming the contact holes 710, 730, and 740 by etching the passivation layer 700 and the gate insulating layer 300 covering the gate pad 220. 13A through 13B, 15A through 15C, and 17A through 17C illustrate a process of forming a contact hole 720 by etching a protective film 700 covering the data patterns 620, 630, and 640. It is a cross section.

First, in order to form a good etching profile, the data patterns 620 and 630 using an etching gas having an etching selectivity of about 1: 1.5 of the photoresist 900, the passivation layer 700, and the silicon nitride layer of the gate insulating layer 300. , 640, until the molybdenum-tungsten alloy film is exposed (see FIGS. 12A and 13A). The etching gas is preferably SF ₆ + HCl (+ He) or SF ₆ + Cl ₂ (+ He). In this case, since the molybdenum-tungsten alloy film of the data patterns 620, 630, and 640 also has an etching ratio of about 2,000 mW / min with respect to SF ₆ + HCl or SF ₆ + Cl ₂ , some portions may be etched. In this way, the edge inclination angles of the contact holes 710, 720, 730, and 740 are about 30 to 80 degrees.

Next, as shown in FIGS. 12B and 13B, the photoresist completes the contact hole by applying a gas condition in which the etching selectivity of the silicon nitride film and the molybdenum-tungsten alloy film is not less than about 15: 1. Examples of such gases include the aforementioned CF ₄ + O ₂ .

Next, a method of forming a contact hole in three steps will be described. In the three-step method, the polymer film is formed on the entire surface in the middle. Here, two methods are possible.

In the first method, in order to smooth the edge slope of the contact hole, first, as shown in FIGS. 14A and 15A, a gas of SF ₆ + HCl (+ He) or SF ₆ + Cl ₂ (+ He) is used. The photoresist 900 and the silicon nitride films 700 and 300 are sequentially etched. In this case, the etching process is performed until a part of the molybdenum-tungsten alloy film of the data patterns 620, 630, and 640 is etched. The reason why the etching process is performed until a part of the molybdenum-tungsten alloy film is etched is performed by minimizing the thickness of the gate insulating layer 300 remaining on the gate pad 220. This is to minimize the time to apply for etching.

Next, in the second step, as shown in FIGS. 14B and 15B, a gas mixed with carbon tetrafluoride (CF ₄ ) and hydrogen (H ₂ ) or hydrogen chloride (HCl) is reacted in a plasma state to polymerize the upper portion of the substrate 100. A polymer film 1000 is formed. The polymer film 1000 serves to delay the etching of the passivation layer 700 and the gate insulating layer 300 to the side part when the dry etching is performed. That is, dry etching is performed by the collision of ions generated in the plasma state, and the speed at which the passivation layer 700 and the gate insulating layer 300 are etched is delayed at the side portion that is not exposed to the collision of the ions.

Subsequently, in the third step, as shown in FIGS. 14C and 15C, the etching selectivity between the molybdenum film or the molybdenum-tungsten alloy film 620, 630, and 640 and the silicon nitride films 300 and 700 is 1: 15 or higher. The silicon nitride films 300 and 700 are etched by applying dry etching gas conditions to complete contact holes. At this time, CF ₄ + O ₂ is suitable as a gas to be used, and since the etching ratio of the molybdenum-tungsten alloy film of the gas is about 300 mW / min, even when the gate pad 220 is exposed, the date patterns 620 and 630 are used. 640, the molybdenum-tungsten alloy film is only etched to a minute extent. In addition, since the polymer 1000 is formed, the etching holes of the side surfaces of the gate insulating layer 300 and the passivation layer 700 are delayed compared to the planar portion of the gate insulating layer 300 on the gate pad 220. Side surfaces of the gate insulating layer 300 and the passivation layer 700 having 710, 720, 730, and 740 are formed to have a gentle inclination angle.

Here, the etching ratio of the passivation layer 4000 and the gate insulating layer 3000 may be different under the condition of CF ₄ + O ₂ because the characteristics of the film may be different in the process of forming the same silicon nitride.

In the second method, a polymer film is formed during the plasma dry etching process in which the etching selectivity of the molybdenum film or the molybdenum-tungsten alloy film and the silicon nitride film is higher than 1:15. How to do it.

First, as shown in FIGS. 16A and 17A, a portion of the passivation layer 700 and the gate insulating layer 300 and the data patterns 620, 630, and 640 are formed on the gate pad 220 by using CF ₄ + O ₂ gas. In some embodiments, the contact holes 710, 730, and 740 are formed by etching until the molybdenum-tungsten alloy film of the data patterns 620, 630, and 640 is exposed. The CF ₄ + O ₂ gas may be etched until the data patterns 620, 630, and 640 are exposed because the etching selectivity of the silicon nitride film and the molybdenum-tungsten alloy film of the protective film 700 is 15 or more. have.

Subsequently, in step ₂ , a polymer film is formed on the substrate 100 by reacting a gas containing carbon tetrafluoride (CF ₄ ) with hydrogen (H ₂ ) or hydrogen chloride (HCl) in a plasma state in the same manner as described above. 1000 is formed (see FIGS. 16B and 17B). The polymer film 1000 serves to delay the silicon nitride films 700 and 300 from being laterally etched as described above. In addition, the photoresist 900 increases the effect that the etching of the side portion is delayed because the ions interfere with the side portion.

Subsequently, step 3 is performed in the same manner as the first step to complete the contact hole (see FIGS. 16C and 17C).

This second method is the same as the method of forming contact holes three times in the first method, but in the second method, the application conditions are simple using a single gas for dry etching.

In addition, in the first method, the photoresist 900 and the silicon nitride films 700 and 300 are simultaneously used in a one-step etching process using a gas of SF ₆ + HCl (+ He) or SF ₆ + Cl ₂ (+ He). Because of etching, the polymer film 1000 formed on the side surface of the passivation layer 700 is directly exposed to the dry etching condition in the three-step etching process, thereby delaying the side surface portion of the passivation layer 700 from being etched. However, this is different when etching with CF ₄ + O ₂ gas in the first step etching process. That is, since the CF ₄ + O ₂ gas has an etching ratio of 1,000 μs / min or less with respect to the photoresist 900, as shown in FIG. 17A, the protective film 700 generates an undercut under the photoresist 900. do. Accordingly, as shown in FIG. 17C, when the silicon nitride film is etched using CF ₄ + O ₂ gas in the third step, the photoresist 900 may have the polymer 1000 formed on the side surface of the protective film 700. Prevent direct exposure to Therefore, in the second method, the photoresist 900 may increase the effect of preventing side surfaces of the passivation layer 700 from being etched.

In the above-mentioned plasma etching method, in order to prevent the molybdenum-tungsten alloy film from being etched as much as possible, the ratio of CF ₄ and O ₂ is preferably 10: 4 or less.

In addition, when the ratio of CF ₄ and O ₂ is 10: 4 or less, it is possible to simultaneously form the contact holes 710, 720, 730, and 740 in one step.

Such a method can be used in a process for preventing the etching of the metal film under the contact hole of the thinner side with different thickness of the insulating film in the method of manufacturing a semiconductor device, and for etching the side surface of the insulating film with a gentle inclination angle.

That is, in the structure in which the first metal film, the first insulating film, the second metal film, and the second insulating film are continuously formed, the first contact hole and the lower portion of the second and first insulating films exposing the second metal film below the second insulating film. It is applicable when simultaneously forming a second contact hole for exposing the first metal film of the film.

That is, the side surface of the insulating film is etched to be inclined with respect to the photoresist and the insulating film under the etching conditions of the etching selectivity of 1: 1 to 1: 1.5, and the contact hole is completed under the etching condition of the etching selectivity between the insulating film and the metal film of 15: 1 or more. A process of forming a polymer film is added to prevent the insulating film from being etched laterally.

On the other hand, when the data pad 630 is formed as a double film and the aluminum film or the aluminum alloy film is formed as an upper film, the aluminum film or the aluminum alloy film is removed.

Finally, as shown in FIG. 10, ITO is laminated to a thickness of 400 to 500 kPa and dry-etched using a fifth mask, and the drain electrode 620 and the data pad 630 through the contact holes 710 and 730, respectively. ) And an ITO pattern comprising a pixel electrode 800 connected to the gate pad, an ITO electrode 820 for data pads, and an ITO electrode 810 for gate pads connected to the gate pad 220 through a contact hole 720. .

When the gate auxiliary pad part 640 and the contact hole 740 are added as shown in FIG. 9B, the gate pad ITO electrode 810 is formed to extend to the gate auxiliary pad part 640.

If the upper layer of the gate pad 220 is formed of an aluminum film or an aluminum alloy film, the gate pad is likely to be defective because the ITO electrode 810 for the gate pad directly touches and an oxidation reaction occurs. However, when the molybdenum alloy film is used as the upper layer of the gate pad 220, this problem is eliminated. At this time, since the thickness of the upper molybdenum alloy film is as thin as 400 ~ 600Å, the selective etching of the molybdenum alloy film and the insulating film is further required when forming a contact hole in the upper part of the molybdenum alloy film.

Next, the structure of the thin film transistor substrate according to the second exemplary embodiment of the present invention will be described with reference to FIGS. 18 and 19. Here, FIG. 19 is a cross-sectional view taken along the line XIII-XIII 'in FIG. 18, and the same reference numerals as used in FIGS. 9 and 10 denote parts having the same or similar functions.

A gate pattern including a gate line 200, a branch of the gate electrode 210, and a gate pad 220 formed at an end of the gate line 200 is formed on the substrate 100. The gate pattern is formed of a single layer of molybdenum-tungsten alloy, and the gate pad 220 transmits a scan signal from the outside to the gate line 200.

A gate insulating layer 300 is formed on the gate patterns 200, 210, and 220, and the gate insulating layer 300 has a contact hole 720 exposing an upper portion of the gate pad 220. A hydrogenated amorphous silicon layer 400 is formed on the gate insulating layer 300. The amorphous silicon layer 400 is formed at a position corresponding to the gate electrode 210 to function as an active layer of the thin film transistor, and is formed to be elongated vertically.

Hydrogenated amorphous silicon layers 510 and 520 doped with a high concentration of n-type impurities are formed on the amorphous silicon layer 400. The data patterns 610 and 620 formed of a molybdenum-tungsten alloy film are formed thereon, and the doped amorphous silicon layers 510 and 520 and the data patterns 610 and 620 are formed in the same shape. These two layers are divided into two parts 510, 610; 520, and 620 with respect to the gate electrode 210, respectively, and are formed along the shape of the amorphous silicon layer 400.

Transparent conductive layers 830 and 840 made of a transparent conductive material such as ITO are formed on the data patterns 610 and 620, and some of them 830 are the data pattern 610 and the doped amorphous silicon layer 510. The other portion 840 covers the data pattern 620 and extends to the center portion of the pixel to become the pixel electrode.

Finally, a passivation layer 700 is formed on the ITO patterns 830 and 840 and the gate insulating layer 300 that is not covered by the ITO pattern, and the passivation layer 700 has a gate pad 220 and a transparent conductive layer 830. Contact holes 720 and 730 exposing the ends of the < RTI ID = 0.0 >) < / RTI >

Next, a method of manufacturing the thin film transistor substrate having the structure shown in FIGS. 18 and 19 will be described with reference to FIGS. 20A to 20D. The manufacturing method proposed in this embodiment is a manufacturing method using four masks.

As shown in FIG. 20A, a molybdenum-tungsten alloy film is laminated on the transparent insulating substrate 100 to a thickness of 2000 to 4000 micrometers and photo-etched using a first mask to form a gate line 200, a gate electrode 210, and a gate. A gate pattern including the pad 220 is formed.

Here, the molybdenum-tungsten alloy film is composed of tungsten (W) having an atomic percentage of 0.01% or more and less than 20% and the remaining molybdenum (Mo), and the content of tungsten is preferably 9-11% of the atomic percentage. In addition, an aluminum etchant, for example, CH ₃ COOH / HNO ₃ / H ₃ PO ₄ / H ₂ O and the like is used, the content of HNO ₃ is preferably contained in the range of 8-14%.

In addition, the gate pattern may be formed as a double layer by adding an aluminum film or an aluminum alloy to the lower portion of the molybdenum-tungsten alloy film, or may be formed as a single film by depositing one of these materials.

Here, in the case of using an aluminum alloy film, the aluminum alloy film is made of aluminum and rare earth metal or transition metal of 5% or less.

Next, a gate insulating layer 300 made of silicon nitride having a thickness of 3000 to 5000 GPa, a hydrogenated amorphous silicon layer 400 having a thickness of 2000 to 2500 GPa, and a hydrogenated amorphous silicon layer doped at a high concentration with an N-type impurity having a thickness of 500 to 700 GPa (500) and a molybdenum-tungsten alloy film 600 containing tungsten having an atomic percentage of 0.01% or more and less than 20% having a thickness of 2000 to 4000 micrometers in succession, and using a second mask, as shown in FIG. 14B, molybdenum- The tungsten alloy film 600, the doped amorphous silicon layer 500 and the amorphous silicon layer 400 is patterned,

Instead of the molybdenum-tungsten alloy film 600, a single film of chromium, molybdenum or molybdenum alloy, or a combination of these may be formed as a double film. In addition, an aluminum film or an aluminum alloy film may be added to lower the resistance.

Next, as shown in FIG. 20C, ITO, which is a transparent conductive material, is laminated to a thickness of 400 to 500 μm, and then the transparent conductive layers 830 and 840 are patterned using a third mask. Subsequently, the exposed molybdenum-tungsten alloy film 600 and the doped amorphous silicon layer 500 are wet and dry etched using the transparent conductive layers 830 and 840 as masks, respectively. Amorphous silicon layers 510 and 520 are formed.

As shown in FIG. 19, the protective film 700 having a thickness of 2000 to 4000 micrometers is stacked, and then photo-etched together with the insulating layer 300 using a fourth mask to form the gate pad 220 and the data pattern 610. Contact holes 720 and 730 exposing an upper portion of the transparent conductive film 830 corresponding to the ends are formed.

Therefore, in the method of manufacturing a semiconductor device according to the present invention, the molybdenum alloy has a low resistance and can be used as a gate line and a data line of the liquid crystal display because an aluminum etchant can be used during tapering. In addition, since the molybdenum alloy thin film has the characteristics described above, there is an effect that can improve the operating characteristics of the liquid crystal display device. In addition, when forming the upper contact hole of the data / gate pattern, the edge of the contact hole is smooth by forming a polymer film which delays the side etching of the protective layer and the gate insulating layer or by using CF ₄ + O ₂ , in which the molybdenum-tungsten alloy layer is not etched. The inclined and molybdenum-tungsten alloy film under the contact hole can be prevented from being etched.

1 to 3 is a graph showing the characteristics of the molybdenum alloy (MoW) according to an embodiment of the present invention,

4 is a cross-sectional view showing an etching profile of a molybdenum alloy (MoW) film according to the present invention,

5 to 8 illustrate an etching profile of a double layer made of molybdenum alloy (MoW) and aluminum alloy (Al alloy) according to an embodiment of the present invention.

9A and 9B are plan views showing the structure of a thin film transistor substrate according to the first embodiment of the present invention;

FIG. 10 is a cross-sectional view taken along the line X-X 'of FIG. 9A;

11A to 11D are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

12 to 17 are cross-sectional views illustrating in detail a process of forming a contact hole in an upper portion of a thin film transistor substrate according to a first embodiment of the present invention.

18 is a plan view illustrating a structure of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

19 is a cross-sectional view taken along the line XIII-XIII 'of FIG. 12,

20A to 20C are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention.

Claims (8)

A gate electrode and a gate line having a double conductive film on the substrate and tapered. A gate insulating layer pattern covering the gate electrode and the gate line and exposing a part of the gate end; An amorphous silicon pattern and a doped amorphous silicon pattern formed on the gate insulating layer pattern; A source electrode, a drain electrode, and a data line formed at least partially in contact with the doped amorphous silicon pattern; A passivation layer pattern exposing a part of an end end of the gate line together with an end end of the drain electrode and the data line and a gate insulating layer pattern; A plurality of conductive patterns electrically connected to the drain electrode, the data wire end, and the gate end; A thin film transistor substrate, wherein the edge inclination angle of the contact hole between the gate insulating layer pattern and the protective layer pattern exposing the gate line is 30 to 80 °. In claim 1, And the gate electrode and the gate line are formed of an upper conductive layer and a lower conductive layer. In claim 2, The lower conductive film is a thin film transistor substrate, characterized in that made of aluminum or aluminum alloy. In claim 3, The aluminum alloy is a thin film transistor substrate, characterized in that consisting of aluminum and rare earth metal or transition metal. A tapered gate electrode and gate line including a double conductive layer on the substrate. A gate insulating layer pattern covering the gate electrode and the gate line and exposing a part of the gate end; A doped amorphous silicon pattern formed in contact with an amorphous silicon pattern formed on the gate insulating layer pattern and an upper surface of the amorphous silicon layer, and all surfaces of the lower part contacted with the amorphous silicon layer pattern; A source electrode, a drain electrode, and a data line formed at least partially in contact with the doped amorphous silicon pattern; A passivation layer pattern exposing a part of an end of the drain electrode and the data line and a part of the end of the gate line and contacting an upper surface of the amorphous silicon layer exposed between the source electrode and the drain electrode, A plurality of conductive patterns electrically connected to the drain electrode, the data wire end, and the gate end; A thin film transistor substrate, wherein the edge inclination angle of the contact hole of the gate insulating layer pattern and the protective layer pattern exposing the gate line end is 30 to 80 °. In claim 5, And the gate electrode and the gate line are formed of an upper conductive layer and a lower conductive layer. In claim 6, The lower conductive film is a thin film transistor substrate, characterized in that made of aluminum or aluminum alloy. In claim 7, The aluminum alloy is a thin film transistor substrate, characterized in that consisting of aluminum and rare earth metal or transition metal.

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