KR100552283B1 - Thin film transistor substrate using molybdenum and molybdenum alloys and its manufacturing method - Google Patents

Abstract

A composition in which molybdenum or tungsten and molybdenum are mixed is deposited on a substrate to form a wiring for a semiconductor device. In particular, when forming a gate / data wiring of a liquid crystal display, the molybdenum alloy exhibits an etching ratio similar to that of aluminum or an aluminum alloy having a low resistance to the aluminum etchant, so that the wiring is doubled between molybdenum alloy and aluminum or aluminum alloy. When formed into a film, gentle oblique etching is possible. In addition, when the transparent conductive film is formed of an ITO film, the transparent conductive film is patterned using Cl ₂ + O ₂ + Ar, which is a dry etching gas. In particular, in a manufacturing process using a four-mask, the ITO film and the molybdenum or molybdenum-tungsten alloy film are simultaneously etched at once to expose the doped amorphous silicon film. In addition, the molybdenum or molybdenum-tungsten alloy film and the amorphous silicon film are simultaneously etched at once. In this case, gentle gradient etching is possible using Cl ₂ + O ₂ + Ar gas as a dry etching method.

Description

Gas for dry etching, a method of manufacturing a semiconductor device and a method of manufacturing a thin film transistor substrate using the same, and a semiconductor device and a thin film transistor substrate including the same

The present invention relates to a dry etching substrate, a method of manufacturing a semiconductor device and a method of manufacturing a thin film transistor substrate using the same, and a semiconductor device and a thin film transistor substrate including the same.

In general, since the wiring of the semiconductor device is used as a means for transmitting a signal, it is required to suppress signal delay and disconnection.

As a method of preventing disconnection, a method of forming a plurality of wirings has been proposed, but not only different etching solutions are required to form multilayer wiring, but also several etching processes are required.

As a method of preventing signal delay, a material such as aluminum (Al) or aluminum alloy (Al alloy) having low resistance is generally used. However, when using aluminum or aluminum alloys, it is necessary to add anodization processes to reinforce the weak physical properties of aluminum. In addition, in the case of reinforcing aluminum using ITO (indium tin oxide) in the pad part as in the liquid crystal display device, there is a problem in that the contact property between aluminum or an aluminum alloy and ITO is poor, and another metal must be interposed therebetween.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and provides a wiring alloy in which each layer has a similar etching ratio under the same etching conditions even when the wiring is formed in multiple layers, thereby simplifying the manufacturing process of the display device and the characteristics of the product. It is the task to improve.

Another object of the present invention is to provide a wiring having low resistance and capable of controlling stress according to thickness.

An object of the present invention is to smooth the edge inclination angle of the contact hole exposing the conductive film or the metal wiring and to prevent the etching of the conductive film under the contact hole.

In the semiconductor device and the method of manufacturing the same according to the present invention, the wiring can be processed into a taper shape under the same etching conditions and the double conductive film having a taper angle in the range of 20 to 70 °, or the lower conductive film under the same etching conditions. The etching rate of the upper conductive film is greater than that of the etching rate, and the double conductive film has a larger etching rate of about 70 to 100 mW / sec.

In the case where the etching method is wet etching, the same etching condition means using the same etching solution.

The conductive film is composed of a lower conductive film having a low resistivity of 15 μΩcm or less and an upper conductive film made of a pad material. Here, the material for the pad means a material having properties that can be used as the pad. The characteristics will be described in the Examples.

Here, aluminum or an aluminum alloy is used as the lower conductive layer, and a molybdenum composition or alloy composed of tungsten (W) having an atomic percentage of less than 0.01% to 20%, remaining molybdenum (Mo), and unavoidable impurities is used as the upper conductive layer. do. The composition ratio of tungsten in the molybdenum alloy is preferably 9% to 11%, in particular 10%, in atomic percentage.

Such a molybdenum-containing composition can be used as a single film wiring because the resistivity is as small as 12 to 14 µΩcm and can be used as a pad.

When the conductive film formed on the lower portion is an aluminum alloy, it is preferable that the transition metal or rare earth metal contained is 5% or less.

In wet etching, the etchant is an etchant used to etch aluminum or an aluminum alloy, and for example, CH ₃ COOH / HNO ₃ / H ₃ PO ₄ / H ₂ O, wherein the concentration of HNO ₃ is 8∼. 14% is preferable.

The double conductive layer may be used as a gate line for applying a scan signal or a data line for applying a data signal in the display device.

In the method of manufacturing a wiring according to the present invention, a lower conductive film is stacked on an upper substrate, and an upper conductive film is stacked on the lower conductive film by an etching ratio of about 70 to 100 kPa / sec larger than that of the lower conductive film under the same etching conditions. Next, the upper conductive film and the lower conductive film are simultaneously etched to complete the wiring.

The method for manufacturing a wiring made of such a double conductive film can also be applied to a method for manufacturing a gate line for applying a scan signal or a data line for applying a data signal in the method for manufacturing a display device.

As described above, the thin film transistor substrate of the liquid crystal display device may be manufactured using such molybdenum-tungsten wiring.

In the method for manufacturing a thin film transistor substrate according to the present invention, a molybdenum alloy composed of tungsten having an atomic percentage of less than 0.01% to 20% and remaining molybdenum and unavoidable impurities is laminated on the substrate, and a molybdenum alloy film is patterned using an etchant to form a gate line. do.

Here, it is also possible to laminate a conductive film made of aluminum or an aluminum alloy under the molybdenum alloy film, and when the molybdenum alloy film is patterned, the conductive film is patterned together.

In the method for manufacturing a thin film transistor substrate according to the present invention, the data line is formed of a single film of molybdenum-tungsten alloy, chromium or molybdenum, or a combination of these.

In this case, when the pixel electrode is formed using the ITO film as the transparent conductive film in the liquid crystal display according to the present invention, patterning is preferably performed by dry etching, and the same applies to the semiconductor device and the manufacturing method thereof.

Here, a dry etching gas, Cl ₂ + O ₂ + Ar is used.

In the manufacturing process of the amorphous silicon thin film transistor, in the case of molybdenum or molybdenum-tungsten alloy, the ITO film and the molybdenum or molybdenum-tungsten alloy film are dry-etched at the same time, and the molybdenum or molybdenum-tungsten alloy film and amorphous silicon are simultaneously etched. Dry etch the membranes at once. The same applies to the semiconductor device and its manufacturing method.

In this case, as an etching method, Cl ₂ + O ₂ + Ar is used as a dry etching gas.

DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

As the wiring of the semiconductor device, especially the display device, materials such as aluminum, aluminum alloy, molybdenum, copper, etc. having a low resistivity of 15 μΩcm or less are suitable. On the other hand, the wiring should have a pad for receiving a signal from the outside or transmitting a signal to the outside. The pad material should have a resistivity below a certain level, should not oxidize well and should not easily break during manufacture. Aluminum and aluminum alloys have very low resistivity but are not suitable as pad materials because of their good oxidation and easy disconnection during manufacturing. In contrast, materials such as chromium, tantalum, titanium, molybdenum and alloys thereof are suitable for pads but have a higher resistivity than aluminum. Therefore, when the wiring is made, a metal having both characteristics is used, or a low resistance conductive film is used at the bottom and a pad conductive film is used at the top, so that the pad can be used with low resistance.

In addition, when wiring is doubled, the same etching conditions, particularly wet etching, are simultaneously etched using one etchant but processed into a tapered shape having a gentle inclination angle. For this purpose, it is preferable that the same etching liquid has a taper angle in the range of less than 20 to 70 °, or that the etching ratio of the upper conductive film is about 70 to 100 kPa / sec higher than that of the lower conductive film. Moreover, even when wiring is formed by a single film, it is preferable to have a taper angle in the range below 20-70 degrees.

In this process, a molybdenum alloy including tungsten having an atomic percentage of less than 0.01% to 20%, remaining molybdenum, and unavoidable impurities was developed as an alloy for wiring according to an embodiment of the present invention. Here, it is preferable that the composition ratio of tungsten is 5%-15% of atomic percentage, and also 9%-11%.

1 to 3 are graphs showing the characteristics of the molybdenum-tungsten alloy (MoW) according to an embodiment of the present invention.

Figure 1 shows the deposition characteristics of the molybdenum-tungsten alloy according to an embodiment of the present invention, the horizontal axis represents the tungsten content in atomic percentage and the vertical axis represents the thickness deposited per unit power.

As can be seen from FIG. 1, when the content of tungsten is 20 atomic percent or less, the thickness of the molybdenum-tungsten alloy film deposited per unit power ranges from 1.20 to 1.40 (kW / W).

Figure 2 shows the resistivity of the molybdenum-tungsten alloy according to an embodiment of the present invention, the horizontal axis represents the tungsten content in atomic percentage and the vertical axis represents the resistivity accordingly.

As can be seen in Figure 2, the specific resistance (R) of the molybdenum-tungsten alloy according to the content of tungsten (W) was 12.0 ~ 14.0 (μΩcm).

As such, the molybdenum-tungsten alloy containing tungsten with an atomic percentage of 20% or less has a low resistivity of 15 μΩcm or less, so that it may be made of a single film and used as a wiring, but because of its properties as a pad material, aluminum or its It is laminated on top of an alloy or the like and can be used as a wiring. In particular, it can be used as a signal line of the display device, or a gate line or a data line of the liquid crystal display device.

Figure 3 shows the etching rate (etch rate) characteristics of the molybdenum-tungsten alloy according to an embodiment of the present invention, the horizontal axis represents the tungsten content in atomic percentage and the vertical axis shows the degree of etching per unit time for the aluminum etchant will be.

In other words, the degree to which the molybdenum-tungsten alloy thin film is etched per unit time with respect to the etching liquid (HNO ₃ : H ₃ PO ₄ : CH ₃ COOH: H ₂ O) of the aluminum alloy is indicated according to the content of tungsten (W).

As can be seen in FIG. 3, when the tungsten content is 0%, the etch ratio is very large as about 250 (Å / sec), but when the tungsten content is 5%, the etch ratio is about 100 (Å / sec). And it turns out that content of tungsten falls to 50 (Pa / sec) or less between 15 and 20%.

On the other hand, aluminum having very low resistivity or an alloy thereof has an etching ratio of about 40 to 80 (Å / sec) with respect to an aluminum etchant consisting of HNO ₃ (8 to 14%): H ₃ PO ₄ : CH ₃ COOH: H ₂ O. Therefore, when the molybdenum-tungsten alloy film having an etching ratio of about 70 to 100 (Å / sec) is larger than the etching ratio of this level, an excellent double film wiring can be obtained.

4 is a view illustrating an etching profile of a molybdenum-tungsten alloy film according to an embodiment of the present invention.

4 shows a profile obtained by etching a single film of molybdenum alloy using an etchant of an aluminum alloy, and it can be seen that a gentle profile is formed.

That is, a tungsten-molybdenum alloy film 2 containing tungsten having an atomic percentage of 10% on the substrate 1 is deposited to a thickness of about 3,000 kPa, and then etched using an aluminum alloy etchant to produce 20 to 25 ° C. A gentle profile with an angle of was formed.

On the other hand, as can be seen in Figure 3, by adjusting the composition ratio of tungsten to lower the etch ratio of the molybdenum-tungsten alloy film to less than 100 (Å / sec), even for a display device even with a single film made of molybdenum-tungsten alloy It can be used as a gate line or a data line of the liquid crystal display device.

5 to 8 illustrate a double layer profile when a double layer of an aluminum alloy and a molybdenum-tungsten alloy are etched using an etchant of an aluminum alloy. An aluminum or aluminum alloy film 3 is deposited on the substrate 1 to a thickness of about 2,000 kPa, and the molybdenum-tungsten alloy film 2 is deposited to a thickness of about 1,000 kPa on the substrate 1, and then an aluminum etchant is used. The aluminum alloy film 3 and the molybdenum-tungsten alloy film 2 were simultaneously etched.

Here, the aluminum alloy is made of aluminum as a base material, and here transition metals such as Ti, Cr, Ni, Cu, Zr, Nb, Mo, Pd, Hf, Ta, W, or Nd, Gd, Dy, In rare earth metals such as Er, an alloy in which two or three elements are bonded, the contained transition element or rare earth metal has an atomic percentage of 5% or less.

In addition, the etchant used an aluminum etchant (HNO ₃ : H ₃ PO ₄ : CH ₃ COOH: H ₂ O), preferably containing about 8 to 14% nitric acid.

FIG. 5 shows a profile of 30 to 40 ° as the content of tungsten is 5% in the molybdenum-tungsten alloy film, and a profile of 40 to 50 ° in the case of FIG. 6 in which the content of tungsten is 10%. When the tungsten content is 15%, the profile becomes 80 to 90 ° as shown in FIG. 7, and when the tungsten content is 20%, the profile of 90 ° is shown as shown in FIG. 8.

In addition, in the embodiment of the present invention, when etching a double layer of aluminum alloy and molybdenum-tungsten alloy using an aluminum etching solution, stains did not appear after etching.

As described above, when a double film made of an aluminum alloy and a molybdenum-tungsten alloy containing tungsten having an atomic percentage of 20% or less is etched using an aluminum alloy etching solution, a taper angle is formed in the range of 30 to 90 degrees. 6, the most preferable taper angle (40-50 degrees) is formed when tungsten content is about 10%, ie, 9%-11%.

Next, the thin film transistor substrate for a liquid crystal display device using the wiring will be described in detail.

First, a structure of a thin film transistor substrate according to a first exemplary embodiment of the present invention will be described with reference to FIGS. 9A, 9B, and 10. Here, FIG. 10 is sectional drawing of the XX 'line | wire in FIG. 9A.

A gate pattern including a gate line 200, a branch of the gate electrode 210, and a gate pad 220 formed at an end of the gate line 200 is formed on the substrate 100. The gate electrode 210 and the gate pad 220 each consist of a lower aluminum film or an aluminum alloy film 211 and 221 and an upper molybdenum-tungsten alloy film 212 and 222. The gate line 200 is also made of aluminum. Or a double film of an aluminum alloy film and a molybdenum-tungsten alloy film. The gate pad 220 transmits a scan signal from the outside to the gate line 200.

A gate insulating layer 300 is formed on the gate patterns 200, 210, and 220, and the gate insulating layer 300 exposes a contact hole 720 exposing the molybdenum-tungsten alloy layer 222, which is an upper layer of the gate pad 220. Has) The hydrogenated amorphous silicon (a-Si: H) film 400 and the hydrogenated amorphous silicon films 510 and 520 heavily doped with n + impurities are disposed on the gate insulating film 300 on the gate electrode 210. 210 is formed on both sides with the center.

A data line 600 is also vertically formed on the gate insulating layer 300, and a data pad 630 is formed at one end thereof to transmit an image signal from the outside. A source electrode 610, which is a branch of the data line 600, is formed on one doped amorphous silicon film 510, and a drain electrode is formed on the doped amorphous silicon film 520 opposite to the source electrode 610. 620 is formed. The data pattern including the data line 600, the source and drain electrodes 610 and 620, and the data pad 630 may be formed of a molybdenum film or a molybdenum-tungsten alloy film. In FIG. 9B, a gate auxiliary pad part 640 is further formed on the gate insulating layer 300 near the gate pad 220.

A passivation layer 700 is formed on the data patterns 600, 610, 620, and 630 and the amorphous silicon layer 500 not covered by the data pattern, and the passivation layer 700 includes the upper molybdenum layer of the gate pad 220. Contact holes 720, 710, and 730 exposing the tungsten alloy film 222, the drain electrode 620, and the data pad 630 are formed, respectively. In FIG. 9B, a contact hole 740 of the passivation layer 700 is formed on the gate auxiliary pad part 640.

Lastly, the passivation layer 700 is connected to the drain electrode 620 through the contact hole 710, and the pixel electrode 800 made of ITO is formed, and the gate pad 220 exposed through the contact hole 720 is formed. ) Is connected to the data pad 630 through the ITO electrode 810 for the gate pad and the contact hole 730 to transmit a signal from the outside to the gate line 200, and transmits a signal from the outside to the data line 600. A data pad ITO electrode 820 is formed. Meanwhile, in FIG. 9B, the gate pad ITO electrode 810 extends to the gate auxiliary pad part 640 and is connected through the contact hole 740.

As shown in FIGS. 9A and 9B, portions of the gate pad ITO electrode 810 and the data pad ITO electrode 820 are substantially directly applied to the pad.

Next, a method of manufacturing the thin film transistor substrate having the structure shown in FIGS. 9A and 10 will be described with reference to FIGS. 11A to 11D. The manufacturing method proposed in this embodiment is a manufacturing method using five masks.

As shown in FIG. 11A, an aluminum film or an aluminum alloy film and a molybdenum-tungsten alloy film in a thickness of 0.1 to 0.5 μm and 0.02 to 0.15 μm are sequentially stacked on the transparent insulating substrate 100, and photo-etched using the first mask. As a result, a gate pattern including the gate line 200, the gate electrode 210, and the gate pad 220 is formed. That is, as shown in FIG. 11A, the gate electrode 210 is an aluminum or aluminum alloy film 211 below and a molybdenum-tungsten alloy film 212 above, and the gate pad 220 is an aluminum or aluminum alloy below. The film 221 and the molybdenum-tungsten alloy film 222 thereon, although not shown in Figure 11a, the gate line 210 is also made of a double film.

Here, the molybdenum-tungsten alloy film is composed of tungsten (W) having an atomic percentage of 0.01% or more and less than 20% and the remaining molybdenum (Mo), and the content of tungsten is preferably 9-11% of the atomic percentage. The aluminum alloy film is made of aluminum and rare earth metal or transition metal of 5% or less. In addition, an aluminum etchant, for example, CH ₃ COOH / HNO ₃ / H ₃ PO ₄ / H ₂ O and the like is used, the content of HNO ₃ is preferably contained in the range of 8-14%.

Further, the gate pattern may be formed as a single film by depositing one of aluminum, aluminum alloy, and tungsten-molybdenum alloy.

As shown in FIG. 11B, the gate insulating film 300 made of silicon nitride, the hydrogenated amorphous silicon film 400 and the hydrogenated amorphous silicon film 500 heavily doped with N-type impurities are 0.2 to 1.0 μm, respectively. After sequentially stacking at a thickness of 0.1 to 0.3 μm and 0.015 to 0.15 μm, the doped amorphous silicon film 500 and the amorphous silicon film 400 are photo-etched using the second mask.

As shown in FIG. 11C, after the molybdenum-tungsten alloy film including molybdenum or tungsten is laminated to a thickness of 0.3 to 2.0 μm, wet etching is performed using a third mask to form the data line 600 and the source electrode 610. And a data pattern including the drain electrode 620 and the data pad 630.

The data pattern may be formed of a single film of one of chromium, molybdenum or molybdenum alloy, or a double film combining these. In addition, an aluminum film or an aluminum alloy film may be added to lower the resistance.

Subsequently, the doped amorphous silicon film 500 exposed using the data patterns 600, 610, 620, and 630 as a mask is plasma-etched to separate both sides of the gate electrode 210, and both doped amorphous silicon. The amorphous silicon film 400 between the films 510 and 520 is exposed.

As shown in FIG. 11D, the protective film 700 is stacked to a thickness of 0.1 to 1.0 μm, and then photo-etched together with the insulating film 300 using a fourth mask to form the upper molybdenum-tungsten alloy of the gate pad 220. Contact holes 720, 710, and 730 exposing the film 222, the drain electrode 620, and the data pad 630 are formed.

When forming the date pattern, the gate auxiliary pad part 640 may be additionally formed, and the contact hole 740 of the passivation layer 700 may be additionally formed to have a structure such as 9b.

In this case, when the data pad 630 is formed as a double layer and the aluminum layer or the aluminum alloy layer is formed as the upper layer, the aluminum layer or the aluminum alloy layer is removed.

Finally, as shown in FIG. 10, indium tin oxide (ITO) is laminated to a thickness of 0.03 to 0.2 μm, and dry etching is performed using a fifth mask, respectively, through the contact holes 710 and 730. 620, the pixel electrode 800 connected to the data pad 630, the ITO electrode 820 for the data pad, and the ITO electrode 810 for the gate pad connected to the gate pad 220 through the contact hole 720. An ITO pattern is formed.

When the gate auxiliary pad part 640 and the contact hole 740 are added as shown in FIG. 9B, the gate pad ITO electrode 810 is formed to extend to the gate auxiliary pad part 640.

In this case, a dry etching method is used as a method of forming an ITO pattern, and Cl ₂ + Ar + O ₂ is preferably used as a dry etching gas.

Detailed experimental results will be described through Experimental Example 1.

If the upper layer of the gate pad 220 is formed of an aluminum film or an aluminum alloy film, the gate pad is likely to be defective because the ITO electrode 810 for the gate pad directly touches and an oxidation reaction occurs. However, when the molybdenum alloy film is used as the upper layer of the gate pad 220, this problem is eliminated.

Next, a structure of a thin film transistor substrate according to a second exemplary embodiment of the present invention will be described with reference to FIGS. 12 and 13. Here, FIG. 12 is sectional drawing of the line XIX-XIX 'in FIG. 13, and the same code | symbol as FIG. 9A, 9B, and FIG. 10 shows the part which performs the same or similar function.

A gate pattern including a gate line 200, a branch of the gate electrode 210, and a gate pad 220 formed at an end of the gate line 200 is formed on the substrate 100. The gate pattern is formed of a single layer of molybdenum-tungsten alloy, and the gate pad 220 transmits a scan signal from the outside to the gate line 200.

A gate insulating layer 300 is formed on the gate patterns 200, 210, and 220, and the gate insulating layer 300 has a contact hole 720 exposing an upper portion of the gate pad 220. A hydrogenated amorphous silicon film 400 is formed on the gate insulating film 300. The amorphous silicon film 400 is formed at a position corresponding to the gate electrode 210 to function as an active layer of the thin film transistor, and is formed to be elongated vertically.

Hydrogenated amorphous silicon films 510 and 520 doped with a high concentration of n-type impurities are formed on the amorphous silicon film 400. The data patterns 610 and 620 formed of a molybdenum-tungsten alloy film are formed thereon, and the doped amorphous silicon films 510 and 520 and the data patterns 610 and 620 are formed in the same shape. These two layers are divided into two parts 510, 610; 520, and 620 with respect to the gate electrode 210, respectively, and are formed along the shape of the amorphous silicon film 400.

Transparent conductive films 830 and 840 formed of a transparent conductive material such as ITO are formed on the data patterns 610 and 620, and some of them 830 are the data pattern 610 and the doped amorphous silicon film 510. The other portion 840 covers the data pattern 620 and extends to the center portion of the pixel to become the pixel electrode.

Finally, a passivation layer 700 is formed on the ITO patterns 830 and 840 and the gate insulating layer 300 that is not covered by the ITO pattern, and the passivation layer 700 includes the gate pad 220 and the transparent conductive layer 830. Contact holes 720 and 730 are formed to expose the ends of the respective portions.

Next, a method of manufacturing the thin film transistor substrate having the structure shown in FIGS. 12 and 13 will be described with reference to FIGS. 14A to 14C. The manufacturing method proposed in this embodiment is a manufacturing method using four masks.

As shown in FIG. 14A, a molybdenum-tungsten alloy film is laminated on the transparent insulating substrate 100 to a thickness of 0.1 to 2.0 μm, and photo-etched using a first mask to form a gate line 200, a gate electrode 210, and A gate pattern including the gate pad 220 is formed.

Here, the molybdenum-tungsten alloy film is composed of tungsten (W) having an atomic percentage of 0.01% or more and less than 20% and the remaining molybdenum (Mo), and the content of tungsten is preferably 9-11% of the atomic percentage. In addition, an aluminum etchant, for example, CH ₃ COOH / HNO ₃ / H ₃ PO ₄ / H ₂ O and the like is used, the content of HNO ₃ is preferably contained in the range of 8-14%.

In addition, the gate pattern may be formed as a double layer by adding an aluminum film or an aluminum alloy to the lower portion of the molybdenum-tungsten alloy film, or may be formed as a single film by depositing one of these materials.

Here, in the case of using an aluminum alloy film, the aluminum alloy film is made of aluminum and rare earth metal or transition metal of 5% or less.

Next, the gate insulating film 300 with a thickness of 0.2 to 1.0 μm made of silicon nitride, the amorphous silicon film 400 hydrogenated to a thickness of 0.1 to 0.3 μm, and doped with N-type impurities at a thickness of 0.015 to 0.15 μm. The molten amorphous silicon film 500 and the molybdenum or molybdenum-tungsten alloy film 600 were sequentially stacked at a thickness of 0.3 to 2.0 μm, and the molybdenum-tungsten alloy film (as shown in FIG. 600), the doped amorphous silicon film 500 and the amorphous silicon film 400 are patterned in sequence at one time.

In this case, a dry etching method is preferable as a method of etching the triple layer formed of the molybdenum-tungsten alloy film 600, the doped amorphous silicon film 500, and the amorphous silicon film 400, Cl as a dry etching gas _{Use 2} + Ar + O ₂ . In the case of using this gas, the three-layer film is formed by a tapered etching having a gentle inclination angle, and the inclination angle is formed to be 60 ° or less. Here, when etching the three layer film during the dry etching, it is preferable to consider the etching selectivity of the exposed gate insulating film 300 and the amorphous silicon film 400.

Detailed experimental results will be described through Experimental Example 2.

Instead of the molybdenum-tungsten alloy film 600, a single film of chromium, molybdenum or molybdenum alloy, or a combination of these may be formed as a double film. In addition, an aluminum film or an aluminum alloy film may be added to lower the resistance.

Next, as shown in FIG. 14C, ITO, which is a transparent conductive material, is laminated to a thickness of 0.03 to 0.2 μm, and then the ITO film and the molybdenum-tungsten alloy film 600 are patterned successively or simultaneously using a third mask to form a transparent conductive material. The films 830 and 840 and the data patterns 610 and 620 are formed. The doped amorphous silicon layers 510 and 520 are formed by wet or dry etching the doped amorphous silicon layer 500 using the transparent conductive layers 830 and 840 and the data patterns 610 and 620 as masks.

At this time, the method for patterning the ITO film and molybdenum-tungsten 600 is preferably using a dry etching method, Cl ₂ + Ar + O ₂ is used as a dry etching gas. In the case of using such a gas, the transparent conductive films 830 and 840 and the data patterns 610 and 620 are formed by tapered etching having a gentle inclination angle, and the inclination angle is formed to be 70 ° or less. Here, it is preferable to consider the etching selectivity with the doped amorphous silicon film 500 exposed during the dry etching.

Detailed experimental results will be described through Experimental Example 2.

As shown in FIG. 13, the protective film 700 is stacked to a thickness of 0.1 to 1.0 μm, and then photo-etched together with the gate insulating film 300 using a fourth mask to form a gate pad 220 and a data pattern 610. Contact holes 720 and 730 exposing an upper portion of the transparent conductive film 830 corresponding to the ends of the upper and lower portions.

Experimental Example 1

In Experimental Example 1, a process of etching a conductive film made of ITO using Cl ₂ + Ar + O ₂ which is a dry etching gas according to an embodiment of the present invention will be described in detail.

As the liquid crystal display becomes larger and finer, the size of the panel is required to increase while increasing the size of the panel. In order to form a pixel electrode formed of an ITO film as the size of the pixel decreases, the size of the panel is increased. Fine patterning is required.

When the ITO film is patterned, HCl + HNO ₃ + DI is mainly used as an etchant when the wet etching method is used. However, this etchant erodes metal materials such as Cr, Al, Mo, Mo alloy, etc., and the ITO film has a disadvantage of low etching ratio with respect to the etchant, which is disadvantageous when there is a metal material under the ITO film. In order to overcome this disadvantage, it is preferable to perform dry etching.

In order to perform dry etching, from a productive point of view, it is first necessary to prevent a heat-up phenomenon in which the substrate is heated in order to secure a process for patterning the ITO film. This is because the photoresist applied at the time of patterning is not removed due to the wet-up phenomenon.

For example, in order to increase the etch ratio of the ITO membrane in the reactive ion etch, a halogenated gas is used. Among them, an HI gas is most advantageous, and dry etching is performed using HI + Ar gas. .

15 is a graph illustrating a change in temperature of a glass substrate when dry etching is performed using HI + Ar gas.

As shown in FIG. 15, as the number of substrates increases from 0 to 10 sheets, when the high frequency power source is 1700W, the temperature of the substrate increases from 100 ° C. to about 100 ° C. or more, and in the case of 2000W, the temperature of the substrate is 100-150. Increased from 200 ° C. and above. In addition, as the high frequency power applied during dry etching increased from 1700W to 2000W, the temperature of the substrate increased from 100 to 150 ° C to 200 ° C or more. This is because the generated heat generated upon dissolving HI + Ar gas is very high. Therefore, it can be seen that HI + Ar gas is not suitable as a dry etching gas.

16 to 18 are graphs showing characteristics of a process of dry etching a conductive film made of ITO using a dry etching gas Cl ₂ + Ar + O ₂ according to an embodiment of the present invention.

16 to 18, the ITO film was deposited by a sputtering method, and the pressure was 0.7 Pa, the temperature was 200 ° C., and the thickness was 70 nm.

16 is a graph showing the characteristics of the ITO conductive film according to the pressure change of the dry etching gas Cl ₂ + Ar + O ₂ according to the embodiment of the present invention.

At this time, the high-frequency power supply during dry etching is 1700W, the flow rate of Cl ₂ + Ar + O ₂ is 180sccm.

As shown in FIG. 16, it can be seen that as the pressure during dry etching is changed from 25 mTorr to 75 mTorr, the etching ratio of the ITO film falls in the range of 100 to 150 kPa / min from 300 to 350 kPa / min.

FIG. 17 illustrates a change in the etch ratio of the ITO film according to the change in the high frequency power during dry etching according to an embodiment of the present invention.

Here, the pressure during dry etching is 3.3 Pa, the flow rate of Cl ₂ + Ar + O ₂ is 180 sccm.

As shown in FIG. 17, it can be seen that as the high frequency power supply during dry etching is changed from 1500W to 2000W, the etching ratio of the ITO film rises from about 250 kW / min to 350 kW / min or more.

18 illustrates a change in the etching ratio of the ITO film according to the change in the ratio of Cl ₂ during dry etching according to an embodiment of the present invention.

Here, the dry etching pressure is 3.3Pa, the high frequency power supply is 1700W, the flow rate of O ₂ + Ar is 60 sccm.

As shown in FIG. 18, Ar + O ₂ 3 ratio of Cl ₂ about: 6-1: etching the ITO film according to the sense of turning into 1 ratio can be seen to decline at 360Å / min or less 310Åmin.

19 is a view showing the results of measuring the end point detect (EPD) time of Cl ₂ + Ar gas and HI + Ar according to an embodiment of the present invention.

Here, the EPD time means a time at which the etching of the ITO film is finished, and 451 nm is a wavelength at which indium is emitted and detected when the ITO film is etched.

Analyzing the results based on FIG. 19, it can be seen that when dry etching is performed using HI + Ar gas, the EPD time decreases from 130SEC to 115SEC as the number of substrates increases. This means that as the number of etching increases, the substrate is rapidly heated to increase the etching ratio of the ITO film, thereby reducing the overall EPD. On the other hand, when dry etching is performed using the dry etching gas Cl ₂ + Ar according to the embodiment of the present invention, it can be seen that the EPD time is irregular and does not change even when the number of substrates is increased. This means that in the case of Cl ₂ + Ar gas, no shut-up phenomenon occurs.

20 and 21 are graphs illustrating characteristics of a thin film transistor fabricated by dry etching an ITO film using a dry etching gas Cl ₂ + Ar + O ₂ according to an embodiment of the present invention.

In this case, the horizontal axis represents the gate voltage Vg, and the vertical axis represents the log drain current log Id or the drain current Ids.

FIG. 20 is a graph illustrating characteristics of a thin film transistor fabricated by applying dry etching gases Cl ₂ + Ar + O ₂ and HI + Ar gases, respectively, to show characteristics before and after annealing. Here, # 1 and # 2 are cases where Cl ₂ + Ar + O ₂ is applied, and # 7 and # 8 are cases where HI + Ar is applied.

As shown in FIG. 20, even when using Cl ₂ + Ar + O ₂ gas, good characteristics of the thin film transistor were obtained.

21 is a graph illustrating characteristics of a thin film transistor by applying dry and wet etching conditions, respectively.

Here, in the case of wet etching, the etchant uses HCl + HNO ₃ + DI, and in the case of dry etching, HI + Ar and Cl ₂ + O ₂ + Ar gases are used.

As a result, as shown in FIG. 21, the thin film transistor showed similar characteristics in both the wet etching and the dry etching.

Experimental Example 2

In Experimental Example 2, a process of using four masks in the method of manufacturing a thin film transistor substrate according to an embodiment of the present invention will be described in detail.

In general, in the method of manufacturing a thin film transistor substrate for a liquid crystal display device, reducing the number of masks from five masks to four masks is intended to reduce productivity and improve productivity. To this end, as shown in FIGS. 14B and 14C, the molybdenum-tungsten alloy film 600, the doped amorphous silicon film 500, and the amorphous silicon film 400 are patterned one at a time, and the ITO film and the molybdenum-tungsten alloy It is preferable to expose the doped amorphous silicon film 500 by simultaneously etching the film 600 simultaneously.

First, a method of etching a three-layer film made of a molybdenum or molybdenum-tungsten alloy film, a doped amorphous silicon film, and an amorphous silicon film will be described in detail.

A method of etching a three-layer film made of a molybdenum or molybdenum-tungsten alloy film, a doped amorphous silicon film, and an amorphous silicon film is conventionally performed by wet etching followed by dry etching.

First, the molybdenum or molybdenum-tungsten alloy film was patterned by wet etching, and then the amorphous silicon film and the amorphous silicon film doped by dry etching were sequentially etched.

FIG. 22 is a cross-sectional view of patterning a three-layer film of molybdenum-tungsten alloy film, doped amorphous silicon film, and amorphous silicon film through wet and dry etching. FIG.

As shown in FIG. 22, an amorphous silicon film 20, a doped amorphous silicon film 30, and a molybdenum or molybdenum-tungsten alloy film 40 are formed on a portion of the substrate 10. At this time, under-cutting occurs in the lower portion of the molybdenum or molybdenum-tungsten alloy film 40.

In the case of using wet and dry etching, the equipment for etching is divided into two and complicated, and the same patterning is difficult because both conditions are isotropic etching. In order to solve this problem, there is a method of removing a portion where an under-cut has occurred in the molybdenum or molybdenum-tungsten alloy film 40 formed on the uppermost portion. However, the process is complicated and meaningless in the process for reducing the number of masks.

In order to improve this problem, the molybdenum-tungsten alloy film, the doped amorphous silicon film, and the amorphous silicon film using the dry etching gas Cl ₂ + Ar + O ₂ according to the embodiment of the present invention according to the embodiment of the present invention The process of etching the layer film at once will be described in detail.

In general, in order to dry etch molybdenum or molybdenum-tungsten alloy film, the volatilization temperature is very important when the gas reacts chemically at atmospheric pressure. That is, the lower the volatilization temperature is advantageous to the etching.

Here, the volatilization temperature of the molybdenum or molybdenum-tungsten alloy film will be described in detail.

FIG. 23 is a view showing volatilization temperatures of molybdenum or molybdenum-tungsten alloy films reacting with fluorine (F) and chlorine (Cl) series gases, respectively.

As shown in FIG. 23, it can be seen that in order to dry etch the molybdenum or molybdenum-tungsten alloy film, the fluorine-based gas reacts at a lower temperature than the chlorine-based gas. Thus, when dry etching the molybdenum or molybdenum-tungsten alloy film, SF ₆ + O ₂ or CF ₄ + O ₂ gas is used. However, in the method of manufacturing a thin film transistor using a four-sheet mask, as shown in FIG. 14B, the molybdenum-tungsten alloy film 600, the doped amorphous silicon film 500, and the amorphous silicon film 400 are sequentially turned on at once. The etching selectivity and the gate insulating layer 300 made of silicon nitride (SiN _X ) to be patterned and exposed must be considered. In this case, in the case of using SF ₆ + O ₂ or CF ₄ + O ₂ gas, a two-step process is required in most cases. That is, the molybdenum or molybdenum-tungsten alloy film is firstly etched, and the amorphous silicon film is etched secondly by securing a condition having an etching selectivity with the gate insulating film.

24 is a cross-sectional view of a three-layer film of a molybdenum-tungsten alloy film, a doped amorphous silicon film, and an amorphous silicon film by a two-step method.

As shown in FIG. 24, a gate insulating film 60 is formed on the entire surface of the substrate 10, and an amorphous silicon film 20, a doped amorphous silicon film 30, and a molybdenum or molybdenum-tungsten alloy film (a part of the substrate 10 is formed on the substrate 10). 40 are sequentially formed. In addition, the photoresist 50 is formed on the molybdenum or molybdenum-tungsten alloy film 40. The photoresist 50 and the molybdenum or molybdenum-tungsten alloy film 40 were tapered etched through the first step etching, and the amorphous silicon film 20 and the doped amorphous silicon film 30 were tapered etched through the second step etching. .

However, there is a high possibility that under-cutting occurs in the lower portion of the molybdenum or molybdenum-tungsten alloy film 40.

To solve this problem, it is suitable to use Cl ₂ + O ₂ + Ar, which is a chlorine-based gas. In particular, when using a chlorine-based gas, the etching selectivity between the gate insulating film and the amorphous silicon film can be improved, and the etching ratio between the molybdenum or molybdenum-tungsten alloy film and the amorphous silicon film can be adjusted.

FIG. 25 is a view showing an etching ratio of ITO, amorphous silicon (a-Si), molybdenum-tungsten alloy (MoW), and silicon nitride (G-SiN _X ) of the gate insulating layer with respect to Cl ₂ + O ₂ + Ar gas. .

Here, the vertical axis represents the etching ratio (Å / SEC) and the horizontal axis represents each film.

At this time, the molybdenum-tungsten alloy contains 10 at% of tungsten, and the flow rate of pressure, power, and Cl ₂ + Ar during dry etching is 3.25 Pa, 1700 W, and 120 sccm, respectively, and the flow rate of O ₂ is 30 sccm, 60 Etch ratios were measured while adding sccm and 90 sccm.

As shown in FIG. 25, both the amorphous silicon (a-Si) and molybdenum-tungsten alloys (MoW) were both for the Cl ₂ + Ar + O ₂ gas when the amount of O ₂ was 30 sccm and at 60 sccm. Has an etch rate This means that the three-layer film can be etched at once at the same time through the reactive ion etch. In addition, when the amount of O ₂ is reduced from 60 sccm to 30 sccm, the etching selectivity of amorphous silicon (a-Si) and silicon nitride (G-SiN _X ) may be increased.

In addition, it was found that the etching ratio of molybdenum-tungsten alloy (MoW) and amorphous silicon (a-Si) can be adjusted according to the flow rate of O ₂ . That is, when the flow rate of O ₂ is small, the etching ratio of the molybdenum-tungsten alloy (MoW) is decreased, but the etching ratio of amorphous silicon (a-Si) is increased.

Through these results, the gates were used under conditions in which the etch rate of the hydrogenated amorphous silicon (a-Si: H) or molybdenum-tungsten alloy (MoW) was high and the etching selectivity with the silicon nitride (G-SiN _X ) film was excellent. A three-layer film consisting of a molybdenum or molybdenum-tungsten alloy film, a doped amorphous silicon film, and an amorphous silicon film formed on the insulating film was etched at once.

FIG. 26 is a cross-sectional view of a three-layer film of molybdenum or molybdenum-tungsten alloy, a doped amorphous silicon film, and an amorphous silicon film at one time using Cl ₂ + Ar + O ₂ gas.

As shown in FIG. 26, a molybdenum or molybdenum-tungsten alloy film 40, a doped amorphous silicon film 30, and an amorphous film are sequentially formed on the gate insulating film 60 formed on the entire upper surface of the substrate 10. The silicon film 20 has a tapered structure with a gentle inclination angle.

At this time, the taper angle was good at 60 ° or less, and the etching selectivity between the amorphous silicon film 20 and the gate insulating film 60 was 6: 1.

Next, a method of exposing the doped amorphous silicon film by simultaneously etching the ITO film and the molybdenum-tungsten alloy film simultaneously will be described in detail.

As mentioned in Experiment 1, in the case of using the etching solution HCl + HNO ₃ + DI, the molybdenum or molybdenum-tungsten alloy film formed on the lower part of the ITO film is rapidly etched to generate under-cut, resulting in slow Taper etching with one tilt angle is not possible.

FIG. 27 is a cross-sectional view illustrating a structure in which molybdenum or molybdenum-tungsten alloy films and an ITO film are continuously etched using the etching solution HCl + HNO ₃ + DI.

As shown in FIG. 27, a molybdenum or molybdenum-tungsten alloy film 20 and an ITO film 30 are sequentially formed on a part of the substrate 10. At this time, the molybdenum or molybdenum-tungsten alloy film 20 is etched more than the ITO film 30 to form an inverse tapered structure.

This is because the etching ratio of the molybdenum or molybdenum-tungsten alloy film 10 is about 47.5 (µs / sec) faster than the etching ratio 17.5 (µs / sec) of the etching solution HCl + HNO ₃ + DI to the ITO membrane 20.

In order to solve this problem, as the dry etching gas according to an embodiment of the present invention, the etching ratio of the ITO film and the molybdenum or molybdenum-tungsten alloy film to Cl ₂ + O ₂ + Ar will be described in detail.

FIG. 28 is a graph showing an etching ratio of a protective film made of ITO, molybdenum-tungsten alloy (MoW), and silicon nitride (SiN _X ) with respect to Cl ₂ + O ₂ + Ar gas.

Here, the vertical axis represents the etching ratio (Å / SEC) and the horizontal axis represents each film.

At this time, the conditions are the same as those in FIG. 30, and the flow rate of O ₂ was measured for each etching ratio while adding 0 sccm and 30 sccm.

As shown in FIG. 28, the molybdenum-tungsten alloy (MoW) and ITO both have an etch ratio for the Cl ₂ + Ar + O ₂ gas. This means that through the reactive ion etching, the molybdenum-tungsten alloy (MoW) film and the ITO film can simultaneously be etched at once. When O ₂ is not used, the etching ratio of the molybdenum-tungsten alloy (MoW) is about three times higher than that of ITO, and about two times higher in the case of the protective film. However, when the amount of O ₂ is 30 sccm, the etching ratio of molybdenum-tungsten alloy (MoW) is about 4.3 times higher than that of ITO, but about 8.57 times lower than that of the protective film. This means that the etching selectivity between the ITO film and the protective film can be secured when the protective film is formed under the ITO film by adjusting the flow rate of O ₂ . In particular, it corresponds to the case of patterning an ITO film in the manufacturing method of the thin film transistor of a 5-sheet mask.

Next, an experiment was further performed to secure reproducibility of the result as shown in FIG. 28.

The conditions at this time were the same as the conditions in FIG. 28, and the flow rate of Cl ₂ + Ar was 150 sccm, and the flow rate of O ₂ was changed.

As shown in FIG. 29, when O ₂ is not used, the etching ratio of the molybdenum-tungsten alloy (MoW) is about 3.66 times higher than that of ITO, and about 2.96 times higher in the case of the protective film. However, when the amount of O ₂ is 30 sccm, the etch rate of the molybdenum-tungsten alloy (MoW) is about 4.55 times higher than that of ITO, but about 0.43 times lower than that of the protective film, similar to that of FIG. 33.

Further, if Referring to FIG. 25, the etching selectivity of ITO and amorphous silicon (a-Si) in the case of adding an O ₂ 30 sccm is showed by about 5 or more, the addition of O ₂ 60 sccm The etching selectivity of molybdenum-tungsten (MoW) and amorphous silicon (a-Si) was about 27.

Through these results, the amorphous silicon film was exposed by etching the ITO film and the molybdenum or molybdenum-tungsten alloy (MoW) film formed on the hydrogenated amorphous silicon (a-Si: H) film at once.

30 is a cross-sectional view of the ITO film and the molybdenum or molybdenum-tungsten alloy film on the amorphous silicon film at one time using Cl ₂ + Ar + O ₂ gas.

As shown in FIG. 30, the gate insulating film 60, the amorphous silicon film 20, and the doped amorphous silicon film 30 are sequentially formed on the substrate 10, and on the doped amorphous silicon film 30. A molybdenum or molybdenum-tungsten alloy film 40 and an ITO film 50 having an opening having a gentle inclination angle are sequentially formed.

At this time, the taper angles of the molybdenum or molybdenum-tungsten alloy film 40 and the ITO film 50 appeared to be satisfactorily 70 degrees or less.

31 and 32 are graphs illustrating characteristics of a thin film transistor fabricated by applying dry etching gases Cl ₂ + Ar + O ₂ and HI + Ar gases, respectively.

31 and 32 show characteristics of a thin film transistor fabricated by applying four masks on the same substrate and simultaneously etching an ITO and a molybdenum or molybdenum-tungsten alloy film at once. Here, the horizontal axis represents the gate voltage Vg, and the vertical axis represents the drain current Ids.

As shown in Figs. 31 and 32, the characteristics of the thin film transistor formed on one substrate were uniform, and good characteristic results were obtained.

Therefore, in the manufacturing method of the display device according to the present invention, the molybdenum alloy has a low resistance and can be used as the gate line and the data line of the liquid crystal display because aluminum etchant and chromium etchant can be used during tapering. In addition, since the molybdenum alloy thin film has the characteristics described above, there is an effect that can improve the operating characteristics of the liquid crystal display device. In addition, the ITO layer may be finely patterned using Cl ₂ + O ₂ + Ar, which is a dry etching gas, in a five or four mask process. In addition, when etching a double triple film made of an ITO film, molybdenum or molybdenum-tungsten alloy film, and an amorphous silicon film in a four-sheet mask process, at the same time to have a gentle inclination angle using Cl ₂ + O ₂ + Ar It can be etched.

1 to 3 is a graph showing the characteristics of the molybdenum alloy (MoW) according to an embodiment of the present invention,

4 is a cross-sectional view showing an etching profile of a molybdenum alloy (MoW) film according to the present invention,

5 to 8 illustrate an etching profile of a double layer made of molybdenum alloy (MoW) and aluminum alloy (Al alloy) according to an embodiment of the present invention.

9A and 9B are plan views showing the structure of a thin film transistor substrate according to the first embodiment of the present invention;

FIG. 10 is a cross-sectional view taken along the line X-X 'of FIG. 9A;

11A to 11D are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

12 is a plan view illustrating a structure of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view taken along the line XIII-XIII ′ of FIG. 12;

14A to 14C are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a second exemplary embodiment of the present invention.

15 is a graph measuring the temperature change of the glass substrate when dry etching using HI + Ar gas,

16 to 18 are graphs showing characteristics of a process of dry etching a conductive film made of ITO using a dry etching gas Cl ₂ + Ar + O ₂ according to an embodiment of the present invention.

19 is a view showing the results of measuring the end point detect (EPD) time of Cl ₂ + Ar gas and HI + Ar according to an embodiment of the present invention,

20 and 21 are graphs illustrating characteristics of a thin film transistor fabricated by dry etching an ITO film using a dry etching gas Cl ₂ + Ar + O ₂ according to an embodiment of the present invention.

FIG. 22 is a cross-sectional view of patterning triple layers of molybdenum-tungsten alloy film, doped amorphous silicon film, and amorphous silicon film through wet and dry etching; FIG.

FIG. 23 is a view showing volatilization temperatures of molybdenum or molybdenum-tungsten alloy films which react with fluorine (F) and chlorine (Cl) series gases, respectively.

FIG. 24 is a cross-sectional view of a triple layer of a molybdenum-tungsten alloy film, a doped amorphous silicon film, and an amorphous silicon film by a two-step method;

25 is a graph showing the characteristics of the dry etching gas Cl ₂ + O ₂ + Ar according to an embodiment of the present invention,

FIG. 26 is a cross-sectional view of an etched triple layer at once using Cl ₂ + Ar + O ₂ gas according to an embodiment of the present invention.

FIG. 27 is a cross-sectional view illustrating a structure etched using etching solution HCl + HNO ₃ + DI,

28 and 29 are graphs showing the characteristics for Cl ₂ + O ₂ + Ar gas according to an embodiment of the present invention,

30 is a cross-sectional view of an etching of a double layer at once using Cl ₂ + Ar + O ₂ gas according to an embodiment of the present invention.

31 and 32 are graphs illustrating characteristics of a thin film transistor fabricated by applying dry etching gases Cl ₂ + Ar + O ₂ and HI + Ar gases, respectively.

Claims (68)

Depositing an ITO film on top of the substrate, Patterning the ITO membrane by dry etching using Cl ₂ + O ₂ + Ar gas Method for manufacturing a semiconductor device comprising a. In claim 1, And forming a protective film made of silicon nitride under the ITO film. In claim 1, And depositing a molybdenum or molybdenum-tungsten alloy film under the ITO film. In claim 3, And the ITO film and the molybdenum film or molybdenum-tungsten alloy film are simultaneously etched at once. In claim 4, And forming an amorphous silicon film under the molybdenum or molybdenum-tungsten alloy film. In claim 4, The ITO film and the molybdenum film or molybdenum-tungsten alloy film are formed with a taper angle of 70 degrees or less. The taper angle is in the range of 70 ° or less, and the signal line includes a molybdenum or molybdenum-tungsten alloy film, a lower film, and an upper film made of ITO. A semiconductor device comprising a. In claim 7, And a dry etching gas used to form the taper angle is Cl ₂ + O ₂ + Ar. Depositing an amorphous silicon film on top of the substrate, Depositing a molybdenum film or molybdenum alloy film on the amorphous silicon film; And patterning the molybdenum film or molybdenum-tungsten alloy film and the amorphous silicon film under one etching condition. In claim 9, And forming a doped amorphous silicon film under the amorphous silicon film. In claim 10, And the doped amorphous silicon layer is etched under the etching conditions. In claim 11, The etching condition is a method of manufacturing a semiconductor device dry etching. In claim 12, The dry etching is a method of manufacturing a semiconductor device using a Cl ₂ + O ₂ + Ar gas. In claim 13, And a taper angle of the amorphous silicon film and the molybdenum film or molybdenum-tungsten alloy film is 60 degrees or less. The method of claim 14, And forming a gate insulating film made of silicon nitride under the amorphous silicon film. A taper angle is in the range of 60 degrees or less, and the lower part is an amorphous silicon film, and the upper part is a molybdenum film or a molybdenum- tungsten alloy film. The method of claim 16, And a dry etching gas used to form the taper angle is Cl ₂ + O ₂ + Ar. The method of claim 16, And an amorphous silicon film doped between the molybdenum film or the molybdenum-tungsten alloy film and the amorphous silicon film. The method of claim 18, And a gate insulating film made of silicon nitride under the amorphous silicon film. Depositing a molybdenum alloy film containing tungsten and molybdenum with an atomic percentage of less than 0.01% to 20% on a substrate, Patterning the molybdenum alloy film with a first mask using an etchant to form a gate pad and a gate electrode; Sequentially depositing a gate insulating film, an amorphous silicon film, an amorphous silicon film doped with a high concentration impurity, and a metal film on the substrate; Etching a three-layer film of the amorphous silicon film, the amorphous silicon film doped with a high concentration impurity, and the metal film by using a second mask under one etching condition; Depositing an ITO film on the substrate and etching the two-layer film of the ITO film and the metal film by using a third mask to expose the doped amorphous silicon film; Etching the doped amorphous silicon film using the ITO film and the metal film as a mask, Forming a passivation layer on the substrate and then etching the gate insulating layer and the passivation layer on the gate pad using a fourth mask Method of manufacturing a thin film transistor substrate comprising a. The method of claim 20, The etching of the two-layer film may be performed by etching under a single etching condition. The method of claim 21, And the metal film is formed of a single film of chromium, molybdenum, or a molybdenum alloy film including tungsten and molybdenum, or a combination of multiple films. The method of claim 22, And when the metal film is molybdenum or molybdenum-tungsten alloy, the one etching condition is dry etching. The method of claim 23, The dry etching is a method of manufacturing a thin film transistor substrate using a Cl ₂ + O ₂ + Ar gas. The method of claim 24, The taper angle of the three-layer film during the dry etching is to form a thin film transistor substrate of 60 ° or less. The method of claim 25, The taper angle of the two-layer film during the dry etching is to form a thin film transistor substrate. The method of claim 26, Stacking a conductive film made of aluminum or an aluminum alloy under the molybdenum alloy film;  And the conductive film is simultaneously patterned with the molybdenum alloy film. The method of claim 27, The etchant is a CH ₃ COOH / HNO ₃ / H ₃ PO ₄ / water manufacturing method of a thin film transistor substrate. Depositing a molybdenum alloy film containing tungsten and molybdenum with an atomic percentage of less than 0.01% to 20% on a substrate, Patterning the molybdenum alloy film with a first mask using an etchant to form a gate pad and a gate electrode; Sequentially depositing a gate insulating film, an amorphous silicon film, an amorphous silicon film doped with a high concentration impurity, and a metal film on the substrate; Etching a three-layer film of the amorphous silicon film, the amorphous silicon film doped with a high concentration impurity, and the metal film using a second mask; Depositing an ITO film on the substrate and etching the two-layer film of the ITO film and the metal film under a single etching condition using a third mask to expose the doped amorphous silicon film; Etching the doped amorphous silicon film using the ITO film and the metal film as a mask, Forming a passivation layer on the substrate and then etching the gate insulating layer and the passivation layer on the gate pad using a fourth mask Method of manufacturing a thin film transistor substrate comprising a. The method of claim 29, The etching of the three-layer film is a method of manufacturing a thin film transistor substrate to be etched under one etching condition. The method of claim 30, And the metal film is formed of a single film of chromium, molybdenum, or a molybdenum alloy film including tungsten and molybdenum, or a combination of multiple films. The method of claim 31, And when the metal film is molybdenum or molybdenum-tungsten alloy, the one etching condition is dry etching. 33. The method of claim 32, The dry etching is a method of manufacturing a thin film transistor substrate using a Cl ₂ + O ₂ + Ar gas. The method of claim 33, And a taper angle between the ITO film and the molybdenum or molybdenum-tungsten is 70 ° or less during the dry etching. The method of claim 34, The taper angle of the said three-layer film is 60 degrees or less, The manufacturing method of the thin film transistor substrate. 36. The method of claim 35 wherein Stacking a conductive film made of aluminum or an aluminum alloy under the molybdenum alloy film;  A method of manufacturing a thin film transistor substrate patterned simultaneously with the molybdenum alloy film. The method of claim 36, The etchant is a CH ₃ COOH / HNO ₃ / H ₃ PO ₄ / water manufacturing method of a thin film transistor substrate. Depositing a molybdenum alloy film containing tungsten and molybdenum with an atomic percentage of less than 0.01% to 20% on a substrate, Patterning the molybdenum alloy film with a first mask using an etchant to form a gate pad and a gate electrode; Sequentially depositing a gate insulating film, an amorphous silicon film, an amorphous silicon film doped with a high concentration impurity, and a metal film on the substrate; Etching a three-layer film of the amorphous silicon film, the amorphous silicon film doped with a high concentration impurity, and the metal film by using a second mask under one etching condition; Depositing an ITO film on the substrate and etching the two-layer film of the ITO film and the metal film under a single etching condition using a third mask to expose the doped amorphous silicon film; Etching the doped amorphous silicon film using the ITO film and the metal film as a mask, Forming a passivation layer on the substrate and then etching the gate insulating layer and the passivation layer on the gate pad using a fourth mask Method of manufacturing a thin film transistor substrate comprising a. The method of claim 38 wherein And the metal film is formed of a single film of chromium, molybdenum, or a molybdenum alloy film including tungsten and molybdenum, or a combination of multiple films. The method of claim 39, And when the metal film is molybdenum or molybdenum-tungsten alloy, the one etching condition is dry etching. 41. The method of claim 40 wherein The one etching condition is a dry etching using a Cl ₂ + O ₂ + Ar gas manufacturing method of a thin film transistor substrate. 43. The method of claim 41 wherein The taper angle of the said two-layer film is 70 degrees or less, The manufacturing method of the thin film transistor substrate. The method of claim 42, The taper angle of the said three-layer film is 70 degrees or less, The manufacturing method of the thin film transistor substrate. A gate electrode formed on a transparent insulating substrate and comprising a molybdenum alloy film containing tungsten with an atomic percentage of less than 0.01% to 20% and the remaining molybdenum, A gate insulating film covering the gate electrode, An amorphous silicon film formed over the gate insulating film, A metal film of molybdenum or molybdenum-tungsten alloy formed on the amorphous silicon film and separated from each other to expose the amorphous silicon film, and an edge portion is formed in the same pattern as the amorphous silicon film; An ITO film connected to the metal film and exposing the amorphous silicon film is formed in the same pattern as the metal film. Thin film transistor substrate comprising a. The method of claim 44, The edge portion is etched and tapered by one etching condition, the taper angle is less than 60 ° thin film transistor substrate. The method of claim 45, The portion exposing the amorphous silicon film is etched and tapered under one etching condition, and the taper angle is 70 ° or less. The method of claim 44, And a doped amorphous silicon film between the amorphous silicon film and the metal film. The method of claim 47, The edge portion of the doped amorphous silicon film is formed in the same pattern as the metal film. Depositing a molybdenum alloy film containing tungsten and molybdenum with an atomic percentage of less than 0.01% to 20% on a substrate, Patterning the molybdenum alloy layer using an etchant to form a gate line, a gate pad, and a gate electrode; Stacking a gate insulating film on the substrate; Forming a semiconductor film on the gate insulating film; Forming a data line, a source electrode and a drain electrode, Stacking a passivation layer and then etching the photo with the gate insulating layer to form a contact hole on the drain electrode and to expose a portion of the gate pad; Stacking ITO, which is a transparent conductive material, and performing dry etching to form a gate conductive layer connected to the gate pad and a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor substrate comprising a. The apparatus of claim 49, Stacking a conductive film made of aluminum or an aluminum alloy under the molybdenum alloy film; And patterning the conductive layer together using the etchant when patterning the molybdenum alloy layer. 51. The method of claim 50, The dry etching is a method of manufacturing a thin film transistor substrate using a Cl ₂ + O ₂ + Ar gas. The method of claim 51, And the data line, the source electrode, and the drain electrode are formed of a single film of chromium, molybdenum or a molybdenum alloy including tungsten and molybdenum, or a combination of multiple films. A gate line formed on the insulating substrate and having a taper angle in the range of 20-70 °, A gate insulating film covering the gate line, An amorphous silicon film formed over the gate insulating film, At least a portion of the data line and the drain electrode formed on the amorphous silicon film or the gate insulating film; A protective film covering the amorphous silicon film exposed between the data line and the drain electrode, A pixel electrode connected to the drain electrode Thin film transistor substrate comprising a. 54. The method of claim 53, The thin film transistor substrate of which the data line and the drain electrode are located only on the amorphous silicon film. 55. The method of claim 54, And a doped amorphous silicon film formed between the data line and the drain electrode and the amorphous silicon film. And the amorphous silicon film has a shape substantially the same as that of the data line and the drain electrode. 54. The method of claim 53, And the pixel electrode is formed on the passivation layer. 54. The method of claim 53, And an auxiliary member formed of the same layer as the pixel electrode and covering an end portion of the gate line or the data line. A gate line formed on an insulating substrate and comprising a molybdenum alloy film containing tungsten and molybdenum having an atomic percentage of less than 0.01% to 20%, A gate insulating film covering the gate line, An amorphous silicon film formed over the gate insulating film, At least a portion of the data line and the drain electrode formed on the amorphous silicon film or the gate insulating film; A protective film covering the amorphous silicon film exposed between the data line and the drain electrode, A pixel electrode connected to the drain electrode Thin film transistor substrate comprising a. The method of claim 58, The thin film transistor substrate of which the data line and the drain electrode are located only on the amorphous silicon film. The method of claim 59, And a doped amorphous silicon film formed between the data line and the drain electrode and the amorphous silicon film. The doped amorphous silicon film has a shape substantially the same as the data line and the drain electrode. The method of claim 58, And the pixel electrode is formed on the passivation layer. The method of claim 58, The gate line has a taper angle in the range of 20-70 °. The method of claim 58, And an auxiliary member formed of the same layer as the pixel electrode and covering an end portion of the gate line or the data line. A gate line formed on the insulating substrate with a taper angle in the range of 20-70 ° and comprising a molybdenum alloy film containing tungsten and molybdenum having an atomic percentage of less than 0.01% to 20%, A gate insulating film covering the gate line, An amorphous silicon film formed over the gate insulating film, At least a portion of the data line and the drain electrode formed on the amorphous silicon film or the gate insulating film; A protective film covering the amorphous silicon film exposed between the data line and the drain electrode, A pixel electrode connected to the drain electrode Thin film transistor substrate comprising a. 65. The method of claim 64, The thin film transistor substrate of which the data line and the drain electrode are located only on the amorphous silicon film. 66. The method of claim 65, And a doped amorphous silicon film formed between the data line and the drain electrode and the amorphous silicon film. The doped amorphous silicon film has a shape substantially the same as the data line and the drain electrode. 65. The method of claim 64, And the pixel electrode is formed on the passivation layer. 65. The method of claim 64, And an auxiliary member formed of the same layer as the pixel electrode and covering an end portion of the gate line or the data line.