JP2809153B2 - Liquid crystal display device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly to an active matrix type liquid crystal display device using an inverted staggered thin film transistor as a switching element and a method of manufacturing the same.

[0002]

2. Description of the Related Art A liquid crystal display device using a thin film transistor as a switching element is a flat display device having a large screen,
A high-quality image can be obtained with a high pixel density, and has been widely used in recent years.

As an example of a conventional thin film transistor, for example, as shown in FIG.
An inverted staggered structure in which a gate electrode 12, a gate insulating film 13, and an undoped semiconductor layer 14 (amorphous silicon layer) are formed, and then source and drain electrodes 18 and 19 are formed is often used. Here, the undoped semiconductor layer 14
(A high-purity semiconductor layer not intentionally doped with impurities; the same applies hereinafter) and source / drain electrodes 18 and 19
The n-type semiconductor layer 15 is provided in order to obtain an ohmic connection.

In order to improve the uniformity of etching of the n-type semiconductor layer when forming a channel portion between a pair of source / drain electrodes, and to further improve the ohmic connection between the undoped semiconductor layer and the source / drain electrode. There is known a technique for forming a silicide layer on an n-type semiconductor layer. For example, in JP-A-61-248564 and JP-A-2-2006131, when titanium, chromium, tantalum, or the like is used for the source / drain electrodes, they are formed at the interface with the n-type semiconductor layer or the undoped semiconductor layer. A technique is disclosed in which a silicide is formed by reacting (interdiffusion) the two with each other based on the thermal history at the time of film formation. In this case, the thickness of the silicide layer is about 5 nm to 10 nm or less. Further, in Japanese Patent Application Laid-Open Nos. 5-235034 and 62-172761, when titanium, chromium, molybdenum, platinum or the like is used for the source / drain electrode or its diffusion preventing layer, the n-type There is disclosed a technique in which these silicides are formed at the interface by reacting them by annealing at about 250 to 300 ° C. Although the thickness of the silicide layer in this case is not clearly described in both publications, it is considered that the thickness is at least greater than 10 nm.

[0005] Next, structurally,
And JP-A-2-206131 disclose a technique characterized by a silicide layer and a self-line process which substantially acts as a source / drain electrode. The end faces of the layers do not match, and the end face of the metal layer is recessed from the end face of the silicide layer, thereby reducing the overlap with the gate electrode and reducing the parasitic capacitance therebetween. Also, Japanese Patent Application Laid-Open
Also in the device disclosed in Japanese Patent No. 172761, the end faces of the silicide layer and the diffusion preventing layer and the metal layer thereover at the channel portion generally coincide with each other because the latter etching is performed in an independent lithography step. Not
Further, in the above-mentioned four publications, the silicide layer is formed only on the source / drain electrode portions, and is not formed on the signal line portions and the terminal portions.

Next, according to the production method, Japanese Patent Application Laid-Open No. 61-2485
No. 64, JP-A-5-235034, JP-A-5-235034
In JP-A-206131, the metal layers of the source and drain electrodes are etched by wet etching. Japanese Patent Application Laid-Open No. Sho 62-172761 does not specifically state.

[0007] As shown in FIG.
In Japanese Patent No. 8564, the source / drain electrodes 18, 19, the transparent conductive film 22, the metal layer 17, the silicide layer 16 and the n-type semiconductor layer 15 are wet-etched with different etchants (however, the last n-type semiconductor). The layer is etched by dry etching).

In general, when the metal of the source / drain electrodes is etched by wet etching, it is often difficult to select an etchant suitable for a thin film transistor manufacturing process, and problems such as residues are likely to occur. In many cases, dry etching that can be easily controlled is used. When the metal is a high melting point metal such as tantalum, molybdenum, chromium, titanium, tungsten, niobium, etc., etching is usually performed using a fluorine-based gas or a mixed gas containing a fluorine-based gas.

[0009]

However, when forming source / drain electrodes, for example, Japanese Patent Application Laid-Open No. 61-2485
When a wet etching method is used as disclosed in Japanese Patent No. 64, there is a problem in the conventional signal line structure that the signal line is easily broken at a step portion intersecting with a scanning line (gate line) or the like. The reason for this is that, for example, the adhesion between the gate insulating film and the signal line metal film is deteriorated on the step portion with the scanning line, and the etchant penetrates into this portion from the side surface of the signal line during over-etching during wet etching. It is presumed that the signal line is etched. This phenomenon is particularly noticeable when the scanning line has a reverse tapered cross section.

Further, in order to increase the screen size and the weight of the liquid crystal display device, it is necessary to make the thin film transistor substrate larger and thinner.
In the conventional signal line structure, the problem of stress migration cannot be ignored. In general, stress migration of a metal wiring is likely to form a crystal grain boundary at a step portion of a base and occurs along the boundary. Therefore, it is considered that it is more likely to occur on a signal line than on a scanning line.

On the other hand, when the source / drain electrodes are formed by dry etching, the thickness of the conventional silicide layer forming technique is very thin, about 5 to 10 nm or less. From 20
Since it is estimated to be about 30 nm and it is difficult to control the film thickness, there is a problem that it is difficult to control over-etching during dry etching. That is, when a high melting point metal such as tantalum, molybdenum, chromium, titanium, or the like is used as a diffusion preventing layer for the source / drain electrodes or a part thereof as in the prior art, this is replaced by carbon tetrafluoride (CF ₄ ) Fluorine-based gas such as (SF ₆ ) or a mixed gas containing these (for example, CF ₄ + O ₂ , SF ₆ + C
When the reactive ion etching is performed in l ₂ ), since the underlying silicide layer is thin, it is difficult to stop the etching at this silicide layer during overetching, and the etching proceeds to the underlying n-type semiconductor layer. Generally, the etching selectivity of metal to amorphous silicon is about 1 with a fluorine-based gas as described above, and cannot be increased. Accordingly, in such a situation, it becomes very difficult to control the over-etching, and it is easy to cause excessive or insufficient etching of the metal layer or the n-type semiconductor layer. In particular, in the case of a channel-etch type thin film transistor, the etching amount of the channel portion is made uniform. Can not. For this reason, there has been a problem that the characteristics of the thin film transistor are deteriorated, and display unevenness occurs during liquid crystal display.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, to improve the transistor characteristics, to reduce display unevenness during liquid crystal display, and to reduce signal line disconnection and stress migration. An object of the present invention is to provide a display device and a manufacturing method thereof.

[0013]

Means for Solving the Problems A liquid crystal display device of the present invention comprises a gate electrode for selectively covering the surface of an insulating substrate;
An island-shaped undoped semiconductor layer intersecting with the gate electrode with a gate insulating film interposed therebetween;
Formed to form the lower electrode of the source and drain electrodes
N-type semiconductor layer, provided on the n-type semiconductor layer,
The upper electrode of the pair of source / drain electrodes is
A metal electrode layer composed of a stacked film of a metal film and a metal film.
An inverted staggered thin film transistor, a scanning line selectively covering the surface of the insulating substrate and connected to the gate electrode, and a pair of sources and
A signal line connected to one of the drain electrodes and intersecting with the scanning line via an interlayer insulating film formed simultaneously with the gate insulating film; and a signal line connected to the other of the pair of source / drain electrodes of the inverted staggered thin film transistor In a liquid crystal display device having a pixel electrode, the metal silicide film is mainly used.
As a refractory metal or a refractory metal deposited on the n-type semiconductor layer.
Consists of a silicide film of a high melting point metal alloy,
The high melting point metal deposited on the metal silicide film
Or, it is made of a high melting point metal alloy .

Here , at least one kind of metal film is used.
Refractory metal film, ie, gold deposited on an n-type semiconductor layer
When the metal silicide film is a tantalum silicide film, gold
Tantalum nitride with metal layer deposited on tantalum silicide film
Film and a tantalum film deposited on it
You can also .

The signal line is the same as the upper electrode of the gate electrode.
Structure, that is, a laminated film of a metal silicide film and a metal film,
Become.

According to a method of manufacturing a liquid crystal display device of the present invention, a gate electrode for selectively covering the surface of an insulating substrate and a scanning line connected thereto are formed, and a gate insulating film is deposited on the entire surface. Forming an island-shaped undoped semiconductor layer having an n-type semiconductor layer on the surface thereof, forming a silicide film of a refractory metal or a refractory metal alloy, and forming a metal film of the refractory metal or refractory alloy Forming a multilayer film by performing reactive ion etching from the surface of the metal film to the middle of the silicide film, and forming the remaining reaction layer at the interface between the silicide film and the n-type semiconductor layer. The n-type semiconductor layer is wet-etched with an etchant having selectivity, and the n-type semiconductor layer is subjected to reactive ion etching to pattern the multilayer film to form a pair of sources. A drain electrode and is that a step of forming a signal line for connecting to one of these.

In this case, an undoped semiconductor layer is formed, an etching protection film is formed, and patterning is performed to form the island-shaped undoped semiconductor layer on the surface of which the etching protection film corresponding to the gate electrode is selectively provided. An n-type semiconductor layer can be formed.

Further, a tantalum silicide film can be formed as a silicide film, a tantalum nitride film can be formed, and a tantalum film can be formed as a metal film.

Further, the silicide film is etched by reactive ion etching using fluorine gas or a mixed gas containing fluorine gas, and the n-type semiconductor is etched by reactive ion etching using fluorine gas, chlorine-based gas or a mixed gas thereof. The layer can be etched. In this case, the thickness of the silicide film can be 30 nm or more and 100 nm or less.

In the liquid crystal display device of the present invention, since the signal lines are formed of a multilayer film of a silicide film and a metal film, the liquid crystal display device has good adhesion to an interlayer insulating film.

The method for manufacturing a liquid crystal display device according to the present invention comprises the steps of:
When forming a source / drain electrode by patterning a multilayer film having a silicide film covering the type semiconductor layer as the lowermost layer, the silicide film is etched halfway by reactive ion etching, and the remaining silicide film and the reaction layer are etched. The removal by wet etching makes it easy to control the etching of the n-type semiconductor layer.

[0022]

FIG. 1A is a circuit diagram showing a first embodiment of the liquid crystal display device of the present invention, and FIG.
FIG. 3 is a plan view illustrating one pixel portion of the liquid crystal display device illustrated in FIG. FIGS. 2A and 2B are a sectional view taken along line AA and a sectional view taken along line BB of FIG. 1B, respectively.

In this embodiment, a gate electrode 12 for selectively covering the surface of an insulating substrate 11 made of glass or the like, an island-shaped undoped semiconductor crossing the gate electrode 12 via a gate insulating film 13 (silicon nitride film). An inverted stagger having a pair of source / drain electrodes 18 and 19 connected to the layer 14 (undoped amorphous silicon layer) and the undoped semiconductor layer 14 via the n-type semiconductor layer 15 (n-type amorphous silicon layer), respectively. Scanning line 24 that selectively covers the surface of the insulating substrate 11 and is connected to the gate electrode 12, and the scanning line 24 that is connected to one of the pair of source / drain electrodes 18 of the inverted staggered thin film transistor 28. And a signal line 20 intersecting via an interlayer insulating film formed simultaneously with the gate insulating film 13 and a pair of inverted staggered thin film transistors 28 In the liquid crystal display device having a source-drain pixel electrode connected to the other 19 of the electrode 27 (transparent conductive film 22), a pair of source and drain electrodes 1
8, 19 and the signal line 20 are formed of the tungsten silicide film 16 and the metal film 1 formed on the silicide film 16.
7 (tungsten film). Note that the signal line 20 is a three-layer film of the transparent conductive film 22 / the tungsten film (17) / the silicide film 16. or,
In the channel portion 23, the silicide film 16 and the metal film 1
7 are almost coincident with each other. That is, the source / drain electrodes have a multilayer structure over the entire area.

Next, a manufacturing method of this embodiment will be described.

First, as shown in FIG. 3A, a metal film such as tantalum, chromium, molybdenum, or tungsten is formed on a transparent insulating substrate 11 such as glass, and the gate electrode 12 is formed through a photolithography process. And scanning lines (Fig. 1
24), a silicon nitride film (gate insulating film 13), an undoped amorphous silicon layer (15), and an n-type amorphous silicon layer (15) doped with phosphorus are formed by plasma enhanced chemical vapor deposition. A continuous film is formed, and an island-shaped undoped semiconductor layer 14 and an n-type semiconductor layer 15 that intersect with the gate electrode are formed through a photolithography process. The gate insulating film 13 may be formed by laminating a silicon nitride film on a silicon oxide film formed in advance by sputtering, or forming the gate electrode 12 and the scanning line 24 with a metal film which can be anodized such as tantalum or molybdenum. When I do it,
These surfaces may be anodized to form an insulating film and used as a part of the gate insulating film 13.

Next, after a contact hole (not shown) for making a terminal in the gate insulating film 13 is opened through a photolithography process, for example, a tungsten silicide film and a tungsten film are respectively
A continuous film is formed by a sputtering method of about 0 nm. At this time, the temperature of the substrate is set to about 200 ° C. Then, silicon and tungsten silicide react with each other on the upper surface and side surfaces of the n-type semiconductor layer 15 and the side surfaces of the island-shaped undoped semiconductor layer 14 to form a reaction layer 25 having a thickness of about 5 to 10 nm. Here, the composition ratio of tungsten silicide (WSi _x) layer is suitably about x = 2 to 3, therefore, becomes a high concentration a little silicon than this composition ratio of (WSi _y in this case) the reaction layer 25 (Y> x and y ≒ x). But,
When viewed as a whole, it is considered that a tungsten silicide film of about 60 nm is formed under the tungsten film. The thickness of the tungsten silicide film formed by sputtering is, as described later, uniformity performance of the etching rate of the dry etching apparatus on the substrate surface and the metal film so that the etching can be stopped by this silicide film during dry etching. An appropriate value is selected in the range of 30 nm to 100 nm in consideration of the etching selectivity of the silicide film. For example, the thickness of the metal film is 150 nm,
Considering the standard case where the in-plane uniformity of the etching rate including the film thickness distribution of the metal film is 30% and the etching selectivity between the metal film and the silicide film is 2, the silicide film is formed by the just etching of the metal film. It has been found that the etching has already been performed at a maximum of about 23 nm, so that the thickness of the silicide film needs to be at least about 30 nm. Similarly, in consideration of the worst case where the uniformity of the etching rate including the thickness distribution of the metal film in the substrate surface is 50% and the worst case, the etching of the metal film is stopped by just etching + 30%. It has been found that etching is performed at a maximum of about 71 nm, so that it is sufficient to set the thickness of the silicide film to about 80 nm. When the film thickness of the metal film is 200 nm, the silicide film is etched at a maximum of 95 nm by the same calculation under the same condition as the above-mentioned condition. Therefore, it is sufficient to set the silicide film to about 100 nm. I understand. However, when the silicide has the above-described composition, its specific resistance is generally higher by one digit or more than that of a metal. Therefore, the thickness of the silicide film should be as thin as possible within the controllable range of the dry etching as described above. It is desirable to lower the resistance. Also, the thinner the silicide film,
The processing time of the wet etching described later can be shortened, and the process is convenient. Thus, a stacked film of the silicide film 16 and the metal film 17 is formed.

Next, through a photolithography process, the portions serving as source / drain electrodes and signal lines are formed as shown in FIG.
As shown in (b), a photoresist film 26 is formed,
Using this as a mask, the metal film 17 is dry-etched with a fluorine-based gas or a mixed gas containing a fluorine-based gas, for example, a mixed gas of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ). Subsequently, the silicide film 16 is etched, but this etching is stopped before reaching the n-type semiconductor layer 15. For example, when the metal film 17 is tungsten, the etching selectivity of tungsten to tungsten silicide can be set to 2 or more in this gas system, so that the etching can be easily stopped in the silicide film 16 over the entire surface of the substrate as described above. Subsequently, the remaining silicide film is wet-etched using dilute hydrofluoric acid or dilute buffered hydrofluoric acid. The concentration of the solution is 0.1 for dilute hydrofluoric acid.
About 1% is appropriate, and in the case of dilute buffered hydrofluoric acid, about 5 to 10% is appropriate with 16 buffered hydrofluoric acid. Since silicon is not etched by these liquids, even if the thickness variation of the silicide film left by the previous dry etching is large, the silicide film 16 including the reaction layer 25 described above is completely etched and removed by this wet etching. Moreover, this etching can be stopped at the surface of the n-type semiconductor layer 15 over the entire surface of the substrate. Thus, source / drain electrodes 18 and 19 are formed.

Next, after the photoresist 32 is removed by stripping, as shown in FIG.
2 and a pixel electrode 27 is formed through a photolithography process. At the same time, the signal line 20 is formed by laminating the silicide film 16, the metal film 17, and the transparent conductive film 22 while leaving the transparent conductive film above the signal line.

Finally, the source / drain electrodes 18 and 19
Is used as a mask, and a fluorine-based gas or a chlorine-based gas or a mixed gas thereof, for example, carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ), sulfur hexafluoride (SF ₆ ) and chlorine (C
l ₂ ) or a mixed gas of hydrochloric acid (HCl) as shown in FIG.
As shown in FIG. 7, the n-type semiconductor layer 15 is dry-etched. Thus, the n-type semiconductor layer 15 can be etched substantially uniformly over the entire surface of the substrate.

When the metal film 17 is made of tungsten,
Since it is not etched by the above-mentioned diluted hydrofluoric acid or diluted buffered hydrofluoric acid, even if the lowermost silicide film of the signal line 20 is abnormally etched on the step of the scanning line 24, it is connected by the upper metal film. Thus, disconnection of the signal line at this portion can be prevented. On the other hand, even when the metal film 17 is formed of a metal which is etched with hydrofluoric acid such as tantalum or chromium, the etching rate of the silicide film is overwhelmingly faster, and the concentration of the etching solution is lower. Since the length can also be shortened, there is practically no problem in film reduction due to etching of the metal film, and it is also possible to prevent disconnection of the signal line. Thus, the channel-etch type thin film transistor of FIG. 2 is obtained.

FIG. 5 is a sectional view showing a liquid crystal display device according to a second embodiment of the present invention. FIGS. 5 (a) and 5 (b) are sectional views taken along line AA of FIG. This corresponds to a sectional view taken along line B.

In this embodiment, the gate electrode and the signal
The first embodiment is different from the first embodiment in that a laminated film is used as the metal layer of the line, and an etching protection film 21 is provided between the island-shaped undoped semiconductor layer 14 and the n-type semiconductor layer 15 in correspondence with the gate electrode 12. It is different from the form.

The metal film is composed of a two-layer film of a tantalum nitride film 17-1 and a tantalum film 17-2, and the silicide film 16a is a tantalum silicide film, but this is not limited to the channel protection type. Also applicable to channel etch type. When a tantalum film is directly applied to the tantalum silicide film, the tantalum film becomes β-tantalum having a large specific resistance. Therefore, a tantalum nitride film 17-1 is provided to avoid the tantalum film and form α-tantalum having a small specific resistance.

Next, the manufacturing method of this embodiment will be described.

First, as shown in FIG. 6A, similarly to the manufacturing method of the first embodiment, first, a transparent insulating substrate 1 is formed.
After forming a gate electrode 12 and a scanning line (24 in FIG. 1) on the first silicon nitride film, a first silicon nitride film (gate insulating film 13), an undoped amorphous silicon film and an etching protection film are formed by plasma enhanced chemical vapor deposition. A second silicon nitride film is continuously formed, and then the second silicon nitride film is patterned and formed into a shape corresponding to the gate electrode 12 through a photolithography process. A crystalline silicon film (15) is formed. Next, through a photolithography process (by patterning the n-type amorphous silicon film, the second silicon nitride film and the undoped amorphous silicon film), the gate electrode 12 is formed.
Island-shaped intrinsic semiconductor layer 14 and n-type semiconductor layer 15
To form Next, after a contact hole (not shown) for making a terminal in the gate insulating film 13 is opened through a photolithography process, for example, a tantalum silicide film, a tantalum nitride film, and a tantalum film are each formed to a thickness of 5 in this order.
A continuous film is formed by a sputtering method at about 0 nm, 30 nm, and 150 nm. At this time, silicon and tantalum silicide react on the upper and side surfaces of the n-type semiconductor layer 15 and the side surfaces of the undoped semiconductor layer 14, and tantalum silicide (Ta)
A reaction layer 25a (here, TaSi _y , y> x and y ≒ x) in which the silicon concentration is a little higher than the silicon concentration x = 2 to 3 of Si _x ) is formed in the range of about 5 nm to 10 nm. It is considered that a tantalum silicide film is formed below the tantalum film by about 60 nm. The thickness of the tantalum silicide film formed by sputtering is set to 30 nm to 100 nm as in the case of the second embodiment. Thus, the silicide film 1
A laminated film of 6a and metal layers 17-1 and 17-2 is formed.

Hereinafter, in the same manner as in the first embodiment, FIG.
As shown in FIG. 2A, source / drain electrodes 18 and 19 formed by stacking a silicide film 16a and a metal layer (here, a tantalum film 17-2 / a tantalum nitride film 17-2 layer film) are formed.
Pixel electrode 27 made of transparent conductive film 22, silicide film 1
6a, metal film (17-1, 17-2) and transparent conductive film 22
Are formed, and finally, a signal line 20 is formed.
As shown in (b), the channel portion 23 is formed by etching the n-type semiconductor layer 15. A series of etching techniques are exactly the same as in the first embodiment. Thus, the channel protection type thin film transistor of FIG. 5 is obtained.

In the first and second embodiments described above, an example has been described in which the metal film is formed of a tungsten film and a tantalum film / tantalum nitride film, respectively. However, this metal has a lowermost layer portion adjacent to the silicide film. Any high melting point metal or alloy made of a high melting point metal may be used. For example, when the metal film is a single layer, in addition to tungsten, tantalum, molybdenum, chromium, titanium, niobium, and alloys thereof such as molybdenum-tantalum, niobium-tantalum,
There are tungsten-tantalum, tungsten-molybdenum and the like. When the metal film has two layers, for example, in addition to the tantalum film / tantalum nitride film, for example, a tantalum film / tungsten film,
There are a tantalum film / molybdenum film, a tantalum film / chromium film, a tantalum film / niobium film, a tantalum film / vanadium film, a tantalum film / niobium-tantalum film, a tantalum film / niobium nitride film, a molybdenum-tantalum film / molybdenum film, and the like.
A tantalum film is attractive as a wiring material because of its high chemical resistance. However, if the underlying layer is a silicide film, it becomes a β-tantalum film. To avoid this, the above-described combinations can be used. In this case, the component metal of the lowermost silicide film and the component metal of the film in contact therewith are the same. This is because the etching is easily interrupted in the middle of the silicide film.

Further, a metal film other than the high melting point metal such as aluminum, aluminum alloy, copper, and copper alloy may be laminated on the high melting point metal film or the high melting point metal alloy film,
For example, aluminum (alloy) / chromium, aluminum (alloy) / titanium, aluminum (alloy) / molybdenum, aluminum (alloy) / tungsten, aluminum (alloy) / titanium-tungsten, aluminum (alloy) / titanium nitride, copper / tantalum, etc. You can choose a combination of

The metal layer may have a laminated structure of three or more layers, for example, a combination of aluminum alloy / titanium nitride / titanium or tantalum / copper / tantalum can be used. The structure of the thin film transistor (channel protection type of channel etch type) and the structure and material of the multilayer film described above may be in any combination.

[0040]

As described above, according to the liquid crystal display device of the present invention, the source / drain electrodes and signal lines of the inverted staggered thin film transistor are formed of a silicide film of at least the lowermost layer of a high melting point metal or an alloy of a high melting point metal. Since the upper layer adjacent to the silicide film is a high-melting-point metal, an alloy of the high-melting-point metal, or a multilayer film of a nitride thereof, disconnection of a signal line at a step of a scanning line or the like. And the stress migration resistance of the signal line on a large and thin substrate can be enhanced. When reactive ion etching is performed on the silicide film and the metal film to form source / drain electrodes and signal lines, this etching is stopped by the silicide film, and the remaining silicide film is etched with an etchant having selectivity with the n-type semiconductor layer. The wet etching makes it easy to control over-etching during the formation of the source / drain electrodes, prevents deterioration of the characteristics of the thin-film transistor due to excessive or insufficient etching of the n-type semiconductor layer, and displays a liquid crystal display. Unevenness can be reduced.

Accordingly, there is an effect that a liquid crystal display device with high yield, high quality and high reliability can be provided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram (FIG. 1A) showing a first embodiment of a liquid crystal display device of the present invention, and a plan view (FIG. 1B) showing one pixel portion.

FIG. 2 is a sectional view taken along the line AA (FIG. 2A) and a sectional view taken along the line BB (FIG. 2B) of FIG. 1B.

FIGS. 3A and 3B are cross-sectional views in the order of steps, illustrating the manufacturing method according to the first embodiment; FIGS.

FIG. 4 is a cross-sectional view in the order of steps, which is separated from (a) and (b) following FIG. 3;

FIG. 5 is a sectional view showing a second embodiment of the liquid crystal display device of the present invention, and FIGS. 5A and 5B are AA in FIG. 1B.
It corresponds to a line sectional view and a line BB sectional view.

FIGS. 6A and 6B are cross-sectional views illustrating the manufacturing method according to the second embodiment in the order of steps shown in FIGS.

FIG. 7 is a cross-sectional view in the order of steps, which is shown separately in FIGS.

FIG. 8 is a cross-sectional view illustrating an example of a conventional thin film transistor.

FIG. 9 is a sectional view showing another example of a conventional thin film transistor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 11 insulating substrate 12 gate electrode 13 gate insulating film 14 undoped semiconductor layer 15 n-type semiconductor layer 16, 16a silicide film 17 metal film 18 source / drain electrode 19 source / drain electrode 20 signal line 21 etching protective film 22 transparent conductive film 23 Channel part 24 scanning line 25, 25a reaction layer 26 photoresist film 27 pixel electrode 28 inverted staggered thin film transistor

Claims (9)

(57) [Claims] 1. A gate electrode for selectively covering the surface of the insulating substrate, the island-shaped undoped semiconductor layer crossing over the gate electrode and the gate insulating film, the undoped semiconductor
The lower electrode of a pair of source / drain electrodes is formed on the layer.
An n-type semiconductor layer formed on the n-type semiconductor layer.
The upper electrode of the pair of source / drain electrodes is made of gold.
Metal electrode composed of laminated film of metal silicide film and metal film
An inverted staggered thin film transistor, a scanning line selectively covering a surface of the insulating substrate and connected to the gate electrode, and one of a pair of source / drain electrodes of the inverted staggered thin film transistor. A liquid crystal display having a signal line crossing the scanning line via an interlayer insulating film formed simultaneously with the gate insulating film, and a pixel electrode connected to the other of the pair of source / drain electrodes of the inverted staggered thin film transistor An apparatus, wherein the metal silicator is
The nitride film is mainly formed on the n-type semiconductor layer.
Consisting of a silicide film of a melting point metal or a high melting point metal alloy,
The metal film is deposited on the metal silicide film.
A liquid crystal display device comprising a high melting point metal or a high melting point metal alloy . 2. The method according to claim 1, wherein the metal film has at least one kind or more.
2. The liquid crystal display device according to claim 1, comprising a high melting point metal film. 3. The signal line according to claim 1, wherein the signal line is formed of a metal silicide film.
2. The liquid crystal display device according to claim 1, wherein the liquid crystal display device comprises a laminated film of metal and a metal film.
Place. 4. The semiconductor device according to claim 1, wherein said metal silicide film is an n-type semiconductor.
A tantalum silicide film deposited on the layer, wherein the gold
A nitride layer having a metal layer deposited on the tantalum silicide film;
Consisting of a tantalum film and a tantalum film deposited thereon
The liquid crystal display device according to claim 2 or 3. 5. A gate electrode for selectively covering the surface of an insulating substrate and a scanning line connected to the gate electrode are formed, a gate insulating film is deposited on the entire surface, and n
Forming an island-shaped undoped semiconductor layer having a type semiconductor layer, forming a silicide film of a high melting point metal or a high melting point metal alloy, and forming a metal film made of the high melting point metal or the high melting point alloy to form a multilayer film And performing reactive ion etching from the surface of the metal film to the middle of the silicide film, and selecting the remaining reaction layer at the interface between the silicide film and the n-type semiconductor layer as the n-type semiconductor layer. Wet etching with a reactive etchant, and reactive ion etching of the n-type semiconductor layer to pattern the multilayer film to form a pair of source / drain electrodes and a signal line connected to one of them. And a method for manufacturing a liquid crystal display device. 6. An undoped semiconductor layer is formed, an etching protection film is formed and patterned to form the island-shaped undoped semiconductor layer on which the etching protection film corresponding to the gate electrode is selectively formed. 6. The method for manufacturing a liquid crystal display device according to claim 5, wherein a type semiconductor layer is formed. 7. The method for manufacturing a liquid crystal display device according to claim 5, wherein a tantalum silicide film is formed as a silicide film, a tantalum nitride film is formed, and a tantalum film is formed as a metal film. 8. A silicide film is etched by reactive ion etching using a fluorine gas or a mixed gas containing a fluorine gas, and n is etched by a reactive ion etching using a fluorine gas, a chlorine-based gas or a mixed gas thereof.
8. The method for manufacturing a liquid crystal display device according to claim 5, wherein the mold semiconductor layer is etched. 9. The method according to claim 1, wherein the thickness of the silicide film is 30 nm or more and 10 or more.
The method for manufacturing a liquid crystal display device according to claim 8, wherein the thickness is 0 nm or less.