JPH06188422A - Thin-film transistor - Google Patents

Abstract

PURPOSE:To provide a thin-film transistor whose reliability can be improved by increasing the selection ratio of a channel protection layer in dry etching of an ohmic contact layer without increasing the film thickness of the channel protection layer, reducing the scattering of film thickness of the channel protection layer, and hence reducing the scattering of TFT characteristics. CONSTITUTION:This inverse-staggered type thin-film transistor consists of a first insulation layer 5a where a channel protection layer 5 is made of silicon nitride (SiNx) and a second insulation layer 5b which is made of silicon oxide (SiO2), etc., which are formed at the upper part of the first insulation layer 5a and whose etching rate of an ohmic contact layer 6 in dry etching is smaller than that of SiNx of the first insulation layer 5a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used as an image sensor or a driving element of a flat panel display, and more particularly to a thin film transistor having a small variation in element characteristics and capable of improving reliability.

[0002]

2. Description of the Related Art Hydrogenated amorphous silicon (a-S
A thin film transistor (a-Si: H TFT) using i: H) as a semiconductor active layer is a liquid crystal display (LC).
It is used as a switching element of D). LCD
In many cases, an inverted staggered thin film transistor having a channel protective layer with excellent uniformity of characteristics and a small off current is used.

Here, the structure of an inverted stagger type thin film transistor using a silicon nitride film (SiNx) as a channel protective layer and hydrogenated amorphous silicon (a-Si: H) as a semiconductor active layer will be described with reference to the sectional view of FIG. It will be described with reference to the drawings. The inverted staggered thin film transistor is
As shown in FIG. 3, chromium (C
r), a gate electrode 2 made of a metal such as tantalum (Ta)
And a gate insulating layer 3 made of silicon nitride (SiNx)
And non-doped hydrogenated amorphous silicon (ia
-Si: H) semiconductor active layer 4, silicon nitride (SiNx) channel protection layer 5, n + hydrogenated amorphous silicon (n + a-Si: H) ohmic contact layer 6, polyimide And a wiring layer 7 made of aluminum (Al), molybdenum (Mo) or the like are sequentially stacked, and a protective film 8 is formed of polyimide or the like so as to cover the whole. Has become.

Here, the ohmic contact layers 6 formed on the semiconductor active layer 4 with the channel protection layer 5 interposed therebetween form a source region (S) and a drain region (D), respectively, and further, the ohmic contact layer. A diffusion preventing layer as a barrier metal such as chromium (Cr) may be provided between the wiring layer 6 and the wiring layer 7.

In particular, the channel protection layer 5 is an insulating layer formed on the semiconductor active layer 4 in order to protect the channel region of the inverted staggered thin film transistor, and the material of the channel protection layer 5 is usually a semiconductor. Silicon nitride (SiNx) is used as the active layer 4, which has good interface characteristics with hydrogenated amorphous silicon (a-Si: H). Since the film thickness of the channel protective layer 5 influences the TFT characteristics, it is necessary to control the film thickness of the channel protective layer 5 with high accuracy in order to obtain a thin film transistor with a small variation in characteristics.

Here, a conventional method of manufacturing a thin film transistor will be described with reference to the process cross-sectional explanatory views of FIGS. A gate electrode 2 made of chromium (Cr) is formed on a glass substrate 1, and plasma CV is formed on the gate electrode 2.
The lower SiNx layer as the gate insulating layer 3, the a-Si: H layer as the semiconductor active layer 4, and the upper SiNx layer as the channel protection layer 5 are successively deposited by the D method without breaking the vacuum. Then, the upper SiNx layer is patterned to form the channel protection layer 5 (see FIG. 4A).

Then, an n + a-Si: H layer as an ohmic contact layer 6 to be the source / drain regions is deposited, and an n + a-Si: H layer and a as the semiconductor active layer 4 are formed.
The -Si: H layer is continuously patterned to form the semiconductor active layer 4 and the ohmic contact layer 6 (FIG. 4).
(See (b)).

Next, polyimide as the interlayer insulating layer 9 is applied to a film thickness of about 1 μm and patterned to form the interlayer insulating layer 9, and aluminum (Al) is deposited on the interlayer insulating layer 9 and patterned, By forming the wiring layer 7,
A conventional thin film transistor has been formed (see FIG. 4C).

[0009] On the other hand, in order to make pixels finer in view of the demand for image quality of displays and the like, there is an urgent need to reduce the pixel size, and the size of the thin film transistor used for the pixel should be scaled down to the same extent as the pixel. There is a need to do. However, the processing accuracy of the channel length in the manufacturing process hinders the size reduction of the thin film transistor.

Particularly, the processing accuracy of the ohmic contact layer 6 as the source / drain regions is important in determining the channel length of the thin film transistor. As shown in FIG. 3, in order to obtain a process margin (process tolerance) in the formation process of the ohmic contact layer 6,
A portion (overlap portion: O / L) where the channel protection layer 5 and the ohmic contact layer 6 overlap is provided. However, the higher the processing accuracy, the shorter the overlap length, and the shorter the channel length. The TFT size can be reduced.

When the ohmic contact layer 6 is formed by wet etching in the manufacturing process of the thin film transistor, the side etching amount (horizontal etching amount) of the ohmic contact layer 6 becomes as large as about 2 μm, and the overlap is shortened. However, when the ohmic contact layer 6 is etched, the semiconductor active layer 4 may be etched, and if this happens, defects occur and the yield decreases.

Therefore, considering the side etching amount of the ohmic contact layer 6 and the misalignment in photolithography, the overlap portion (O /
It is necessary to provide L) with a length of about 5 μm or more, and in that case, the channel length of the TFT can be shortened to only about a dozen μm.

Therefore, there is a method in which the ohmic contact layer 6 is formed by dry etching to reduce the side etching amount of the ohmic contact layer 6 and the overlap portion (O / L) to reduce the TFT size. It is being appreciated. If dry etching is used, the channel length can be reduced to about several μm.

Now, the conditions for dry etching the ohmic contact layer 6 will be described with reference to the etching characteristic explanatory diagrams of FIGS. 5 (a) to 5 (c). FIG. 5 (a)-
(C) shows the high frequency output (W) and the high frequency output (W) in the case where the n + a-Si: H layer as the ohmic contact layer 6 formed on the channel protection layer 5 made of silicon nitride (SiNx) is dry-etched. It is explanatory drawing which shows the relationship with an etching characteristic. The etching gas is SF ₆ /
A mixed gas of CCl ₄ / He is used.

FIG. 5A shows a high frequency output and n + a-Si.
FIG. 5 is an explanatory diagram showing an etching rate (etching rate [angstrom / min]) of the H layer, and FIG. 5B is an explanatory diagram showing a relationship between a high frequency output and the uniformity of the etching rate in the plane of the substrate. 5 (c) shows the selection ratio of SiNx acting as an etching stopper, that is,
Etching rate (R2) of upper n + a-Si: H layer to etching rate (R1) of lower SiNx layer
FIG. 3 is an explanatory diagram showing a selection ratio (R2 / R1) that represents the ratio of

In the actual etching process, the etching rate (etching rate) of the upper n + a-Si: H layer, which is the layer to be etched, is different from the etching rate (etching rate) of the lower SiNx layer, which is the etching stopper. ) Is desirable to be small, and etching is performed under the condition that the selection ratio is as large as possible.

As shown in FIG. 5 (c), when the high frequency output is lowered, the selection ratio is improved, but at the same time, as shown in FIG. 5 (a), the throughput (processing amount) is lowered due to the lower etching rate. As a result, productivity will deteriorate and cost will increase. Further, as shown in FIG. 5B, when the high frequency output is reduced, the variation of the etching rate in the plane of the substrate becomes large. Therefore, in the actual process, the channel protection layer 5 of the ohmic contact layer 6 is dry-etched. The selection ratio of SiNx was about 6. Therefore, the SiNx of the channel protection layer 5 is considerably removed during overetching, and the film thickness is reduced.

Further, the etching rate of dry etching largely depends on the state of the chamber of the etching apparatus, and the etching processing time varies from batch to batch, but it is difficult to monitor the etching end point (end point) with high accuracy. Therefore, there was a variation in overetching time.

On the other hand, when silicon oxide (SiO ₂ ) is used as the channel protection layer 5, the ohmic contact layer 6 is formed.
Although the selection ratio in dry etching is about 30 which is sufficiently high, the state of the interface between the a-Si: H layer of the semiconductor active layer 4 and the channel protection layer 5 becomes poor, and an appropriate threshold voltage cannot be obtained. Since the TFT characteristics are impaired, SiO ₂
The layer could not be used as the channel protection layer 5.

[0020]

However, in the above-mentioned conventional thin film transistor, silicon nitride (SiNx) as the channel protection layer 5 has a selectivity ratio in dry etching of the n + a-Si: H layer as the ohmic contact layer 6. Is as small as about 6, the amount of abrasion during overetching is large, and if the etching rate is not uniform, the overetching time varies and the amount of abrasion of the SiNx layer varies, resulting in a non-uniform thickness of the channel protective layer 5. Therefore, there is a problem that variations in TFT characteristics occur.

Therefore, it is conceivable to increase the film thickness of the SiNx layer in order to reduce the variation in the film thickness of the channel protection layer, but the step difference on the substrate 1 becomes large and the upper wiring layer 7 has a step difference portion. There was a problem that it caused disconnection.

The present invention has been made in view of the above circumstances, and the selection ratio of the channel protective layer in the dry etching of the ohmic contact layer is increased without increasing the thickness of the channel protective layer to increase the channel protective layer. It is an object of the present invention to provide a thin film transistor capable of improving the reliability by reducing the variation in the film thickness of the TFT and the variation in the TFT characteristics.

[0023]

SUMMARY OF THE INVENTION The present invention for solving the above-mentioned problems of the prior art includes a gate electrode formed on a substrate, a gate insulating layer formed so as to cover the gate electrode, and A semiconductor active layer formed on the gate electrode via the gate insulating layer, and a channel protection layer formed on the semiconductor active layer so as to face the gate electrode,
In a thin film transistor having an ohmic contact layer formed so as to cover the semiconductor active layer and overlap a part of the channel protection layer, the channel protection layer is
A first insulating layer made of silicon nitride formed in contact with the semiconductor active layer, and an etching rate in dry etching of the ohmic contact layer formed on the first insulating layer are the first insulating layer. And a smaller second insulating layer.

[0024]

According to the present invention, the channel protective layer has a two-layer structure of the first insulating layer and the second insulating layer, and the lower first insulating layer in contact with the semiconductor active layer has a good interface with the semiconductor active layer. The first thin film transistor is formed of silicon nitride, and the upper second insulating layer is an insulating layer whose etching rate in the dry etching step of the ohmic contact layer is smaller than that of the first insulating layer. The insulating layer makes it possible to form the interface between the semiconductor active layer and the channel protective layer in a good state, and thus obtains proper characteristics of the thin film transistor, and the second insulating layer makes it possible to form the channel protective layer in the dry etching step of the ohmic contact layer. It is possible to improve the selection ratio, reduce the etching amount of the channel protective layer during overetching, and protect the channel. It is possible to suppress the variation in the thickness of the channel protective layer without increasing the thickness of the thin film, reduce the variation in the characteristics of the thin film transistor, and improve the reliability. Furthermore, the process tolerance in the dry etching process of the ohmic contact layer can be improved. Can be higher.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional explanatory diagram of a thin film transistor according to an embodiment of the present invention. It should be noted that parts having the same configuration as in FIG.

As shown in FIG. 1, the thin film transistor of this embodiment has a gate electrode 2 made of chromium (Cr) or tantalum (Ta) and a gate insulating layer 3 made of silicon nitride (SiNx) on a glass substrate 1. When non-doped hydrogenated amorphous silicon: a semiconductor active layer 4 made of (i-a-Si H) , the channel protective layer 5 composed of two layers of silicon nitride (SiNx) and silicon oxide (SiO _2), n + Hydrogenated amorphous silicon (n + a-S
i: H) as an ohmic contact layer 6 as a source region (S) and a drain region (D), an interlayer insulating layer made of polyimide (not shown in FIG. 1), aluminum (Al), molybdenum (Mo), etc. The wiring layer 7 is sequentially laminated, and the protective film 8 is formed so as to cover the entire structure, thereby forming an inverted stagger type structure.

Also in the thin film transistor of this embodiment,
Similar to the thin film transistor of the conventional example, between the ohmic contact layer 6 and the wiring layer 7, a metal such as Al of the wiring layer 7 is prevented from diffusing into the ohmic contact layer 6, and a diffusion preventer made of Cr or the like serving as a barrier metal. Layers can also be provided.

In particular, in the channel protection layer 5 which is a characteristic part of the thin film transistor of this embodiment, the lower layer 5a is a silicon nitride (SiNx) layer and the upper layer 5b is a silicon oxide (SiO 2).
₂ ) Two-layer structure. The SiNx layer as the lower layer 5a of the channel protective layer 5 forms a good interface with hydrogenated amorphous silicon (a-Si: H) as the semiconductor active layer 4 which is in contact with the lower portion of the channel protective layer 5 to provide a proper T
The purpose is to obtain FT characteristics.

The SiO ₂ layer as the upper layer 5b of the channel protective layer 5 is excellent at about 30 in dry etching of the n + a-Si: H layer as the ohmic contact layer 6 formed on the channel protective layer 5. The selection ratio is shown. That is, the etching rate of the SiO ₂ layer is about 1 / the etching rate of the n + a-Si: H layer.
As a result, the SiO ₂ layer sufficiently functions as a stopper in the dry etching of the ohmic contact layer 6. Therefore, the etching amount of the channel protective layer 5 at the time of over-etching is greatly reduced and suppressed to about ⅕ of the conventional one, so that the variation in the film thickness of the channel protective layer 5 can be prevented.

In addition, Si of the lower layer 5a of the channel protection layer 5
The film thickness of the Nx layer is about 500 angstroms, the film thickness of the upper SiO ₂ layer 5b is about 1000 angstroms, and the total film thickness of the channel protection layer 5 is about 1500 angstroms. Since they are almost the same, the step of the substrate does not become large, and therefore,
Even when the wiring layer 7 is formed on the upper portion, there is no fear of step breakage in the step portion.

Next, a method of manufacturing the thin film transistor of this embodiment will be described with reference to the process cross-sectional explanatory diagrams of FIGS. First, a metal such as chromium (Cr) or tantalum (Ta) is deposited on the insulating substrate 1 by DC magnetron sputtering in a thickness of about 500 Å, and patterned by photolithography and etching to form the gate electrode 2. (See FIG. 2A).

Next, by a plasma CVD method, silicon nitride (SiNx) as the gate insulating layer 3 having a film thickness of about 3000 angstrom and hydrogenated amorphous silicon (a-Si: H) as the semiconductor active layer 4 is about 500.
The lower layer 5 of the channel protection layer 5 having a film thickness of angstrom
Silicon nitride (SiNx) as a is continuously deposited to a thickness of about 500 Å, and silicon oxide (SiO ₂ ) as the upper layer 5b is continuously deposited to a thickness of about 1000 Å.

The lower layer 5 serving as the channel protection layer 5
The silicon nitride (SiNx) in the part a and the silicon oxide (SiO ₂ ) in the upper layer 5b are patterned in the same width as the gate electrode 2 in a self-aligned manner by photolithography and etching using backside exposure, and the channel protection layer 5
Is formed (see FIG. 2B).

Then, the n + a-Si: H layer as the ohmic contact layer 6 is formed by plasma CVD to 100
The film is deposited with a film thickness of about 0 angstrom. And n
+ a-Si: a-S as H layer and semiconductor active layer 4
The i: H layer is continuously patterned by photolithography and etching to form the ohmic contact layer 6 as the source region (S) and the drain region (D) and the semiconductor active layer 4 (see FIG. 2C). .

Here, the etching of the ohmic contact layer 6 is performed by dry etching using a gas mixed with CF ₄ , SF ₆ , CCl ₄ , O _{2 and the} like. N + a-S as ohmic contact layer 6
Even if a sufficient over-etching is performed in order to make the etching of the i: H layer more reliable, the selection ratio of the silicon oxide (SiO ₂ ) of the upper layer 5b of the channel protection layer 5 that acts as an etching stopper is sufficiently high. The upper layer 5b is hardly etched, and the reduction in the film thickness of the channel protective layer 5 can be prevented. Further, even if the etching time and the etching conditions are varied, the variation in the film thickness of the channel protective layer 5 can be suppressed to be small.

Next, polyimide is applied to a film thickness of about 1.3 μm and patterned to form an interlayer insulating layer 9. An aluminum (Al) film having a film thickness of about 1 μm is deposited thereon by DC sputtering, and patterned by photolithography and etching to form a wiring layer 7 (see FIG. 2D). In this way, the thin film transistor of this embodiment is formed.

According to the thin film transistor of this embodiment, since the channel protective layer 5 acts as an etching stopper in the dry etching of the ohmic contact layer 6, the channel protective layer 5 has a two-layer structure and the lower layer 5a.
Is silicon nitride (SiNx) that forms a good interface with a-Si: H as the semiconductor active layer 4, and the upper layer 5b has a selectivity in dry etching of the n + a-Si: H layer as the ohmic contact layer 6. Since it is made of high silicon oxide (SiO ₂ ), the selection ratio of the channel protective layer 5 in the dry etching of the ohmic contact layer 6 is improved and the decrease in the film thickness is reduced without impairing the TFT characteristics. There is an effect that the variation in the film thickness can be reduced to reduce the variation in the characteristics of the TFT. Further, since the channel protective layer 5 has durability against over-etching, the process margin (process allowance) of the dry etching process can be reduced. There is an effect that can increase the degree).

Further, since SiO ₂ as the upper layer 5b of the channel protection layer 5 has a sufficiently high selection ratio in the dry etching of the ohmic contact layer of about 30, it is not necessary to make the film thickness thick, and SiNx as the lower layer 5a is required. The thickness of the layer is about 500 Å, and the upper layer 5b is made of Si.
Since the film thickness of the O ₂ layer is about 1000 Å, the film thickness of the entire channel protection layer 5 is about the same as that of the conventional structure, and the wiring layer 7 formed on the channel protection layer 5 has a defect such as a step break. It has the effect of preventing the occurrence.

In this embodiment, the upper layer 5b of the channel protective layer is formed.
Although silicon oxide (SiO ₂ ) is used as the material, tantalum oxide (Ta ₂ O ₅ ) and alumina (Al ₂ O) are used.
Other insulating layers having a high selectivity in etching the n + a-Si: H layer such as ₃ ) may be used. However, Ta
For the _{2 O 5, Al 2 O 3} , since the selection ratio than SiO ₂ is low, the effect is somewhat smaller than that in the case of using SiO _2.

[0040]

According to the present invention, the first channel protection layer is formed.
A two-layer structure of an insulating layer and a second insulating layer, the lower first insulating layer in contact with the semiconductor active layer is formed of silicon nitride forming a good interface with the semiconductor active layer, and the upper second insulating layer is formed. Since the layer is a thin film transistor in which the etching rate in the dry etching step of the ohmic contact layer is smaller than that of silicon nitride of the first insulating layer, the interface between the semiconductor active layer and the channel protective layer is formed by the first insulating layer. The thin film can be formed in a good state, and therefore, proper characteristics of the thin film transistor can be obtained, and the selection ratio of the channel protective layer in the dry etching process of the ohmic contact layer can be improved by the second insulating layer, and channel protection during overetching can be achieved. The thickness of the channel protective layer is reduced without decreasing the amount of etching of the layer and increasing the thickness of the channel protective layer. Variation suppressed, there is an effect that can be to reduce the variation in the characteristics of the thin film transistor enhance reliability, there is an effect that can further increase the process latitude in the dry etching process of the ohmic contact layer.

[Brief description of drawings]

FIG. 1 is a cross-sectional explanatory diagram of a thin film transistor according to an embodiment of the present invention.

2A to 2D are process cross-sectional explanatory views showing a method of manufacturing the thin film transistor of this embodiment.

FIG. 3 is a cross-sectional explanatory diagram of a conventional thin film transistor.

4A to 4C are process cross-sectional explanatory views showing a conventional method of manufacturing a thin film transistor.

FIG. 5 is an explanatory diagram of various etching characteristics in dry etching of an ohmic layer.

[Explanation of symbols]

1 ... Substrate, 2 ... Gate electrode, 3 ... Gate insulating layer,
4 ... Semiconductor active layer, 5 ... Channel protective layer, 6 ... Ohmic contact layer, 7 ... Wiring layer, 8 ... Protective film, 9
... Interlayer insulation layer

Claims (1)

[Claims] 1. A gate electrode formed on a substrate, a gate insulating layer formed so as to cover the gate electrode, and a semiconductor active layer formed on the gate electrode via the gate insulating layer. A thin film transistor having a channel protection layer formed on the semiconductor active layer so as to face the gate electrode, and an ohmic contact layer formed so as to cover the semiconductor active layer and overlap a part of the channel protection layer, A channel protection layer made of silicon nitride formed in contact with the semiconductor active layer;
Thin film transistor, and a second insulating layer formed on the first insulating layer and having an etching rate in dry etching of the ohmic contact layer smaller than that of the first insulating layer. .