JPH08297299A - Thin-film transistor and liquid crystal display device using the same - Google Patents

Thin-film transistor and liquid crystal display device using the same

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Publication number
JPH08297299A
JPH08297299A JP10333595A JP10333595A JPH08297299A JP H08297299 A JPH08297299 A JP H08297299A JP 10333595 A JP10333595 A JP 10333595A JP 10333595 A JP10333595 A JP 10333595A JP H08297299 A JPH08297299 A JP H08297299A
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JP
Japan
Prior art keywords
metal layer
layer
gate electrode
film transistor
liquid crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10333595A
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Japanese (ja)
Other versions
JP2820064B2 (en
Inventor
Katsuo Iwasaki
勝男 岩▲崎▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
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Priority to JP10333595A priority Critical patent/JP2820064B2/en
Publication of JPH08297299A publication Critical patent/JPH08297299A/en
Application granted granted Critical
Publication of JP2820064B2 publication Critical patent/JP2820064B2/en
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Expired - Fee Related legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE: To provide a thin-film transistor(TFT) which has excellent reliability at a high yield by embodying the TFT which is free from the occurrence of an insulation defect and shorting defect therein. CONSTITUTION: The structure of a gate electrode 6 of the TFT is constituted by completely coating a first metallic layer 4 having a two-layered structure consisting of pure Al for a lower layer 2 and an Al alloy mixed with Ta of a high melting metal as an impurity for an upper layer 3 with a second metallic layer 5 having the m.p. higher than the m.p. of the Al. The deformation, such as hillock, arising in the Al at the time of a heat treatment is suppressed and the occurrence of the insulation defect and shorting defect in the TFT is prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、薄膜トランジスタとこ
のトランジスタをスイッチング素子とした液晶表示装置
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a liquid crystal display device using the transistor as a switching element.

【0002】[0002]

【従来の技術】近年、薄膜トランジスタ(以下、TFT
と呼ぶ)を応用した液晶表示装置は大型化及び高精細度
化が進んでいる。液晶表示装置は複数本のゲート線とこ
れらと直交するように設けられた複数のソース線の各交
点にスイッチング素子としてTFTを備え、このTFT
をON/OFFすることにより、ソース線から供給され
る信号を画素電極に供給することによって、画素の表示
を制御している。
2. Description of the Related Art In recent years, thin film transistors (hereinafter referred to as TFTs)
The liquid crystal display device to which the () is applied is becoming larger and higher in definition. The liquid crystal display device is provided with a TFT as a switching element at each intersection of a plurality of gate lines and a plurality of source lines provided so as to be orthogonal to these gate lines.
By turning ON / OFF, the signal supplied from the source line is supplied to the pixel electrode to control the display of the pixel.

【0003】しかしながら、近年の液晶表示装置の大型
化に伴いゲート線、ソース線などの配線の配線長が長く
なることから、配線抵抗の増大が問題となっている。ゲ
ート線には画素数に相当するTFTが接続されており、
また各種の寄生容量も接続されている。そのため、ゲー
ト線に供給されるゲート信号は配線抵抗と各種の寄生容
量によって規定される時定数によって、信号遅延の問題
が発生することから、所定の時間内に正常なスイッチン
グ動作を完了することが困難な場合も発生する。この問
題を解決するためには、 1.ゲート線幅を広くする。
However, since the wiring length of the wiring such as the gate line and the source line becomes longer with the increase in size of the liquid crystal display device in recent years, the increase of the wiring resistance becomes a problem. TFTs corresponding to the number of pixels are connected to the gate line,
Also, various parasitic capacitances are connected. Therefore, since the gate signal supplied to the gate line causes a signal delay problem due to the time constant defined by the wiring resistance and various parasitic capacitances, normal switching operation can be completed within a predetermined time. Difficult cases also occur. To solve this problem, 1. Increase the gate line width.

【0004】2.固有電気抵抗の低い材料を選択する。
の方法がある。しかし、上記1のゲート線幅を広くする
方法は、画素部の開口率を小さくするため通常用いられ
ない。また上記2の方法は、従来から、ゲート電極に固
有抵抗の低い材料としてアルミニウム(Al)を用いる
ことが検討されているが、このAlは、数百℃に加熱す
ると表面にヒロックが発生するという問題がある。この
ため、ゲート電極を形成した後の絶縁膜等の成膜時にゲ
ート電極の表面にヒロックが発生し、このヒロックの影
響でゲート電極とソース電極とが短絡してしまう。この
解決方法として、従来からAlに微量の高融点金属(S
i,Ta等)を含有させると、加熱時におけるヒロック
の発生が抑制されることが解明されている。
[0004] 2. Select a material with low specific electrical resistance.
There is a method. However, the above-described method of widening the gate line width is not usually used because it reduces the aperture ratio of the pixel portion. In the above method 2, aluminum (Al) has been conventionally considered as a material having a low specific resistance for the gate electrode, but this Al causes hillocks on the surface when heated to several hundreds of degrees Celsius. There's a problem. Therefore, hillocks are generated on the surface of the gate electrode when the insulating film or the like is formed after the gate electrode is formed, and the hillocks cause a short circuit between the gate electrode and the source electrode. As a solution to this problem, a small amount of refractory metal (S
It has been clarified that the inclusion of (i, Ta, etc.) suppresses the generation of hillocks during heating.

【0005】[0005]

【発明が解決しようとする課題】図2は、固有電気抵抗
の低い材料AlSi合金でゲート電極を形成したTFT
の断面構造図である。ガラス基板等の絶縁性基板21の
表面にAlに高融点金属のSiを混合したアルミニウム
合金から成る第一の金属層22とその第一の金属層22
を完全に被覆するように形成されたクロム(Cr)から
成る第二の金属層23によってゲート電極24が構成さ
れ、このゲート電極24を覆うごとく絶縁層25を設
け、その上に半導体層26、その上にソース電極27及
びドレイン電極28を順次設けた構造となっている。
FIG. 2 shows a TFT having a gate electrode formed of an AlSi alloy having a low specific electric resistance.
FIG. A first metal layer 22 made of an aluminum alloy in which Al is mixed with a refractory metal Si and a first metal layer 22 on the surface of an insulating substrate 21 such as a glass substrate.
The second metal layer 23 made of chromium (Cr) formed so as to completely cover the gate electrode 24 constitutes the gate electrode 24, the insulating layer 25 is provided so as to cover the gate electrode 24, and the semiconductor layer 26, The structure is such that the source electrode 27 and the drain electrode 28 are sequentially provided thereon.

【0006】この構造では、第一の金属層であるAlS
i合金を大型化及び高精細化のために200nm以上の
膜厚にした場合、ゲート電極の端部29に製造工程での
熱処理によりヒロックが発生し、第二の金属層23で完
全に被覆することができないため、その部分の絶縁耐圧
が劣化し、ゲート電極24とソース電極27との間に短
絡欠陥が発生する。また、従来のAlの湿式エッチング
に用いられている燐酸系エッチング液を改善し(特出4
−274004)、ゲート電極24の断面形状を約60
°のテーパー形状に加工しても、短絡欠陥の発生を完全
になくすことはできなかった。また、湿式の燐酸系エッ
チングでは不純物のSiを除去することができず、乾式
のエッチング等が必要となり生産性にも問題があった。
In this structure, the first metal layer, AlS
When the i alloy has a thickness of 200 nm or more in order to increase the size and the definition, hillocks are generated at the end portion 29 of the gate electrode due to the heat treatment in the manufacturing process, and the i-alloy is completely covered with the second metal layer 23. Therefore, the withstand voltage of that portion deteriorates, and a short circuit defect occurs between the gate electrode 24 and the source electrode 27. In addition, the phosphoric acid-based etching solution used in the conventional wet etching of Al was improved.
-274004), the cross-sectional shape of the gate electrode 24 is about 60
Even if processed into a taper shape of °, it was not possible to completely eliminate the occurrence of short circuit defects. Further, wet phosphoric acid-based etching cannot remove Si, which is an impurity, and dry etching or the like is required, which causes a problem in productivity.

【0007】次に、AlTa合金は、TaがAlの中に
固溶しているため、Ta自身もエッチングにより除去さ
れ、Taの残渣が発生しないという利点があるが、Al
Ta合金でゲート電極24を形成した場合、固有電気抵
抗が純Alの約5倍になるため膜厚を厚くせざるをえ
ず、この結果絶縁層25の被覆特性が悪くなり、ゲート
電極24とソース電極27との間に短絡欠陥が発生して
しまうという課題があった。
Next, the AlTa alloy has the advantage that Ta itself is removed by etching because Ta is a solid solution in Al, and Ta residue is not generated.
When the gate electrode 24 is formed of Ta alloy, the specific electric resistance is about 5 times that of pure Al, so that the film thickness must be increased, and as a result, the covering characteristics of the insulating layer 25 are deteriorated and the gate electrode 24 and There is a problem that a short circuit defect is generated between the source electrode 27 and the source electrode 27.

【0008】[0008]

【課題を解決するための手段】上記問題を解決するため
本発明の薄膜トランジスタ及びこれを用いた液晶表示装
置は、絶縁性基板上にゲート電極が設けられ、この絶縁
性基板およびゲート電極上に絶縁膜が、さらにその上方
に半導体層が設けられ、この半導体層上にソース電極お
よびドレイン電極がゲート電極の直上で互いに対向する
よう設けられた薄膜トランジスタであり、ゲート電極
は、純アルミニウムから成る下層、タンタルを不純物と
して混合したアルミニウム合金から成る上層の二層構造
を有する第一の金属層と、アルミニウムより高い融点を
有する金属から成り第一の金属層の上方に設けられた第
二の金属層とを有し、第二の金属層は第一の金属層を完
全に被覆した構成を有する。
In order to solve the above problems, a thin film transistor of the present invention and a liquid crystal display device using the same are provided with a gate electrode on an insulating substrate, and the insulating substrate and the gate electrode are insulated from each other. The film is a thin film transistor in which a semiconductor layer is further provided thereon, and a source electrode and a drain electrode are provided on the semiconductor layer so as to face each other immediately above the gate electrode, and the gate electrode is a lower layer made of pure aluminum, A first metal layer having an upper two-layer structure made of an aluminum alloy in which tantalum is mixed as an impurity, and a second metal layer made of a metal having a melting point higher than that of aluminum and provided above the first metal layer. And the second metal layer has a configuration in which the first metal layer is completely covered.

【0009】[0009]

【作用】本発明は上記構成にすることによって、第一の
金属層の下層の純Alはゲート電極の抵抗を低くし、上
層のAlTa合金はヒロックを抑制し、またこの第一の
金属層を高融点材料から成る第二の金属層で完全に被覆
するため、製造工程中での熱処理によるヒロック等の変
形の発生はAlTa合金および第二の金属層によって完
全に防止される。そして第一の金属層のうち、上層の端
部の断面角度Bと、下層の端部の断面角度Aを本発明の
条件に形成することにより、第一の金属層の端部に鋭い
エッジがなくなり、この端部に発生するヒロックを防止
するものである。
According to the present invention, with the above-mentioned structure, the pure Al in the lower layer of the first metal layer lowers the resistance of the gate electrode, the AlTa alloy in the upper layer suppresses hillocks, and Since it is completely covered with the second metal layer made of a high melting point material, the AlTa alloy and the second metal layer completely prevent deformation such as hillock due to heat treatment during the manufacturing process. By forming the cross-sectional angle B of the end of the upper layer and the cross-sectional angle A of the end of the lower layer of the first metal layer under the conditions of the present invention, a sharp edge is formed at the end of the first metal layer. This is to prevent hillocks generated at this end.

【0010】[0010]

【実施例】以下、本発明の実施例について図面を参照し
ながらその製造方法並びに構成を詳細に述べる。
Embodiments of the present invention will be described in detail below with reference to the drawings and the manufacturing method and construction thereof.

【0011】図1は本発明の一実施例におけるTFTの
断面構造である。ガラス基板等の絶縁性基板1の表面に
スパッタ法または蒸着法等により連続的に膜厚100〜
500nmの純Alから成る下層2と膜厚50〜250
nmのAlTa合金から成る上層3を堆積することによ
り第一の金属層4を形成する。そして、通常のフォトリ
ソグラフィー法を用いて、所望のレジストパターンを形
成し、エッチング液とし濃度85%の燐酸(H3
4)、濃度61%の硝酸(HNO3)、酢酸(CH3
OOH)及び水(H2O)をそれぞれ、16:4:4:
1の比率で容量混合し、20〜50℃にて純AlとAl
Ta合金を同時にパターニングし第一の金属層4を所望
の形状に形成する。この時、第一の金属層4の下層2の
端部2aと絶縁性基板1とが成す断面角度Aは60度以
下で、上層3の端部3aと絶縁性基板1とが成す断面角
度Bは断面角度Aよりも小さい角度に形成される。また
この際に、上層3のAlTa合金の不純物Taも同時に
除去することができるのでTaの残渣は発生しない。エ
ッチング液の混合比の範囲は、H3PO4:HNO3:C
3COOH:H2O=16:4〜7:4:1であれば良
い。
FIG. 1 is a sectional structure of a TFT according to an embodiment of the present invention. A film thickness of 100 to 100 is continuously formed on the surface of the insulating substrate 1 such as a glass substrate by a sputtering method or a vapor deposition method.
Lower layer 2 made of pure Al of 500 nm and film thickness 50-250
A first metal layer 4 is formed by depositing a top layer 3 of nm AlAl alloy. Then, a desired resist pattern is formed by using a usual photolithography method, and phosphoric acid (H 3 P) having a concentration of 85% is used as an etching solution.
O 4 ), concentration 61% nitric acid (HNO 3 ), acetic acid (CH 3 C
16: 4: 4: OOH) and water (H 2 O), respectively.
Volumetric mixing at a ratio of 1 and pure Al and Al at 20-50 ° C
The Ta alloy is simultaneously patterned to form the first metal layer 4 in a desired shape. At this time, the sectional angle A formed by the end 2a of the lower layer 2 of the first metal layer 4 and the insulating substrate 1 is 60 degrees or less, and the sectional angle B formed by the end 3a of the upper layer 3 and the insulating substrate 1. Is formed at an angle smaller than the sectional angle A. Further, at this time, since the impurity Ta of the AlTa alloy of the upper layer 3 can be removed at the same time, no Ta residue is generated. The range of the mixing ratio of the etching solution is H 3 PO 4 : HNO 3 : C.
It suffices if H 3 COOH: H 2 O = 16: 4 to 7: 4: 1.

【0012】次に、第一の金属層4を完全に被覆するよ
うにスパッタ法または蒸着法等により膜厚100〜20
0nmのCrから成る第二の金属層5を形成し、第一の
金属層4とともにゲート電極6を得る。第二の金属層5
はCrの他、WやTiあるいはTaのいずれか1種で構
成してもよく、またこれらの合金でもよい。
Next, a film thickness of 100 to 20 is formed by sputtering or vapor deposition so as to completely cover the first metal layer 4.
A second metal layer 5 made of 0 nm Cr is formed, and a gate electrode 6 is obtained together with the first metal layer 4. Second metal layer 5
May be composed of any one of W, Ti, and Ta in addition to Cr, or may be an alloy of these.

【0013】次に、このゲート電極6を被覆して絶縁膜
である窒化シリコン(SiNx)膜から成るゲート絶縁
層7を膜厚200〜300nmで絶縁性基板1およびゲ
ート電極6の表面上に形成する。このゲート絶縁層7
は、例えばプラズマCVD法により形成する。さらに、
ゲート絶縁層7の上に、アモルファスシリコン(a−S
i)から成る半導体層8を所定の膜厚に形成し、そして
その半導体層8の表面でゲート電極6の直上のチャンネ
ル形成領域以外に、スパッタ法または蒸着法によりアル
ミニウム(Al)とチタン(Ti)等からなるソース電
極9及びドレイン電極10を互いに対向するよう形成し
ている。
Next, a gate insulating layer 7 made of a silicon nitride (SiNx) film as an insulating film is formed on the surfaces of the insulating substrate 1 and the gate electrode 6 so as to cover the gate electrode 6 and have a film thickness of 200 to 300 nm. To do. This gate insulating layer 7
Is formed by, for example, a plasma CVD method. further,
Amorphous silicon (a-S) is formed on the gate insulating layer 7.
The semiconductor layer 8 made of i) is formed to have a predetermined film thickness, and aluminum (Al) and titanium (Ti) are formed on the surface of the semiconductor layer 8 by a sputtering method or a vapor deposition method in a region other than the channel formation region immediately above the gate electrode 6. ) And the like, the source electrode 9 and the drain electrode 10 are formed so as to face each other.

【0014】以上本発明のように純Alを下層に用いて
その上にヒロックを抑制するAlTa合金から成る上層
を設置することにより、固有抵抗値を増加させずにヒロ
ックの発生を抑制するものである。
As described above, pure Al is used as the lower layer and the upper layer made of an AlTa alloy that suppresses hillocks is provided on the lower layer, thereby suppressing the generation of hillocks without increasing the specific resistance value. is there.

【0015】さらに、Alよりも高い融点を有する第二
の金属層5にて第一の金属層4を完全に被覆することに
より、TFTの製造工程中での熱処理によるAlのヒロ
ック等の変形の発生が抑制される。
Further, by completely covering the first metal layer 4 with the second metal layer 5 having a melting point higher than that of Al, deformation of Al such as hillock due to heat treatment in the TFT manufacturing process is prevented. Occurrence is suppressed.

【0016】これら相乗の抑制効果により、ヒロック等
の発生によるゲート絶縁層7の耐圧の劣化に伴う層間絶
縁不良が防止されることから、ゲート電極6とソース電
極9及びドレイン電極10との間に短絡欠陥の発生が極
めて少なくなり、TFTの歩留まりを大幅に改善するこ
とができる。
Due to the synergistic suppression effect, the interlayer insulation failure due to the deterioration of the breakdown voltage of the gate insulating layer 7 due to the generation of hillocks and the like can be prevented. The occurrence of short circuit defects is extremely reduced, and the yield of TFTs can be significantly improved.

【0017】また、断面角度Aを60度以下、断面角度
Bを断面角度Aよりも小さくすることにより、第一の金
属層4の端部の鋭いエッジをなくすことができる。
Further, by making the sectional angle A 60 degrees or less and the sectional angle B smaller than the sectional angle A, it is possible to eliminate a sharp edge at the end of the first metal layer 4.

【0018】例えばエッジ11とエッジ12はともに1
80°に近い鈍角であり、この角度はエッジ11、エッ
ジ12の界面エネルギーの増大を抑えるのに役立ってい
る。従ってエッジ11、エッジ12においてヒロックが
優先的に発生するのを抑えることができる。
For example, the edges 11 and 12 are both 1
It is an obtuse angle close to 80 °, and this angle is useful for suppressing an increase in the interface energy of the edges 11 and 12. Therefore, it is possible to suppress the preferential occurrence of hillocks at the edges 11 and 12.

【0019】しかもエッジ11、エッジ12が180°
に近い鈍角であれば第二の金属層5による被覆が容易で
あり、エッジ11、エッジ12のみが被覆されないとい
った不都合が解消される。
Moreover, the edges 11 and 12 are 180 °
If the obtuse angle is close to, it is easy to cover with the second metal layer 5, and the disadvantage that only the edges 11 and 12 are not covered is eliminated.

【0020】また、本実施例によれば、ゲート電極6の
第一の金属層4の下層2の純Alと上層3のAlTa合
金が同時にエッチングでき、AlSi合金などで見られ
る不純物除去工程を必要とせず製造コストの低減ができ
る。
Further, according to the present embodiment, the pure Al of the lower layer 2 of the first metal layer 4 of the gate electrode 6 and the AlTa alloy of the upper layer 3 can be etched at the same time, and the impurity removing step found in the AlSi alloy or the like is required. Therefore, the manufacturing cost can be reduced.

【0021】また、ゲート絶縁層7は本実施例では単層
構造であるが膜質の異なる多層構造の絶縁層としてもよ
い。
Although the gate insulating layer 7 has a single layer structure in this embodiment, it may be a multilayer insulating layer having different film qualities.

【0022】そして、本実施例の薄膜トランジスタを液
晶表示装置のスイッチング素子として用いることによ
り、表示欠陥の少ない液晶表示装置を得ることができる
ものである。液晶表示装置は、2枚の互いに対向する絶
縁性基板の間隙に液晶材料を挟持した構成であり、これ
ら互いに対向する側の絶縁性基板の一主面、つまり液晶
材料と接する面に上記実施例の薄膜トランジスタを設け
ればよい。
By using the thin film transistor of this embodiment as a switching element of a liquid crystal display device, a liquid crystal display device with few display defects can be obtained. The liquid crystal display device has a structure in which a liquid crystal material is sandwiched between two insulating substrates facing each other, and the above-mentioned embodiment is provided on one main surface of the insulating substrates facing each other, that is, a surface in contact with the liquid crystal material. The thin film transistor may be provided.

【0023】[0023]

【発明の効果】以上のように本発明によれば、TFTの
製造工程中での熱処理によるAlのヒロック等の変形の
発生が抑制されることから、変形の発生による絶縁層の
耐圧の劣化に伴う層間絶縁不良が防止される。例えばゲ
ート電極とソース電極及びドレイン電極との間に短絡欠
陥の発生が極めて少なくなり、歩留まりが高く、信頼性
に優れたTFTを製造できることになる。
As described above, according to the present invention, the deformation of Al hillock or the like due to the heat treatment during the manufacturing process of the TFT is suppressed, so that the breakdown voltage of the insulating layer is deteriorated due to the deformation. Interlayer insulation failure associated therewith is prevented. For example, the occurrence of short-circuit defects between the gate electrode and the source and drain electrodes is extremely reduced, and a TFT with high yield and excellent reliability can be manufactured.

【0024】このようなTFTを液晶表示装置のスイッ
チング素子として用いれば、ゲート線の配線抵抗を大幅
に低減でき、ゲート信号の遅延の問題を解消できること
だけでなく、歩留まりが高く、信頼性に優れた液晶表示
装置を実現することができる。
When such a TFT is used as a switching element of a liquid crystal display device, the wiring resistance of the gate line can be greatly reduced, the problem of delay of the gate signal can be solved, and the yield is high and the reliability is excellent. It is possible to realize a liquid crystal display device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における薄膜トランジスタの
断面図
FIG. 1 is a sectional view of a thin film transistor according to an embodiment of the present invention.

【図2】従来の薄膜トランジスタの断面図FIG. 2 is a sectional view of a conventional thin film transistor.

【符号の説明】[Explanation of symbols]

1 絶縁性基板 2 下層 2a 下層の端部 3 上層 3a 上層の端部 4 第一の金属層 5 第二の金属層 6 ゲート電極 7 ゲート絶縁層 8 半導体層 9 ソース電極 10 ドレイン電極 A 断面角度 B 断面角度 1 Insulating Substrate 2 Lower Layer 2a End of Lower Layer 3 Upper Layer 3a End of Upper Layer 4 First Metal Layer 5 Second Metal Layer 6 Gate Electrode 7 Gate Insulating Layer 8 Semiconductor Layer 9 Source Electrode 10 Drain Electrode A Cross Section Angle B Section angle

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板上にゲート電極が設けられ、
前記絶縁性基板及びゲート電極上に絶縁膜が設けられ、
さらにその上方に半導体層が設けられ、前記半導体層上
にソース電極およびドレイン電極がゲート電極の直上の
チャンネル形成領域以外に互いに対向するよう設け、か
つ前記ゲート電極は、純アルミニウムから成る下層にタ
ンタルを不純物として混合したアルミニウム合金から成
る上層の二層構造を有する第一の金属層と、アルミニウ
ムより高い融点を有する金属から成り第一の金属層の上
方に設けられた第二の金属層とを有するとともに、前記
第二の金属層は前記第一の金属層を完全に被覆した薄膜
トランジスタ。
1. A gate electrode is provided on an insulating substrate,
An insulating film is provided on the insulating substrate and the gate electrode,
Further, a semiconductor layer is provided above the semiconductor layer, the source electrode and the drain electrode are provided on the semiconductor layer so as to face each other except a channel forming region immediately above the gate electrode, and the gate electrode is a lower layer made of pure aluminum and is made of tantalum. A first metal layer having an upper two-layer structure made of an aluminum alloy in which is mixed as an impurity, and a second metal layer provided above the first metal layer made of a metal having a melting point higher than that of aluminum. A thin film transistor having the second metal layer completely covering the first metal layer.
【請求項2】 ゲート電極を構成する第一の金属層の下
層の端部と絶縁性基板の主面とが成す断面角度Aが60
度以下、第一の金属層の上層の端部と絶縁性基板の主面
とが成す断面角度Bが前記断面角度Aよりも小さい請求
項1記載の薄膜トランジスタ。
2. A sectional angle A formed by an end portion of a lower layer of the first metal layer forming the gate electrode and the main surface of the insulating substrate is 60.
The thin film transistor according to claim 1, wherein a cross-sectional angle B formed by an end portion of the upper layer of the first metal layer and the main surface of the insulating substrate is smaller than the cross-sectional angle A by a degree or less.
【請求項3】 第二の金属層がCr,W,Ti,Taの
いずれか1種の金属、あるいはこれらの合金である請求
項1記載の薄膜トランジスタ。
3. The thin film transistor according to claim 1, wherein the second metal layer is any one metal of Cr, W, Ti, and Ta, or an alloy thereof.
【請求項4】 2枚の互いに対向する絶縁性基板の間隙
に液晶材料を挟持してなる液晶表示装置であり、いずれ
か一方の前記絶縁性基板における前記液晶材料と接する
面に、請求項1,2または3に記載の薄膜トランジスタ
をスイッチング素子として設けた液晶表示装置。
4. A liquid crystal display device comprising a liquid crystal material sandwiched between two insulating substrates facing each other, wherein one of the insulating substrates has a surface in contact with the liquid crystal material. , 2 or 3, wherein the thin film transistor is provided as a switching element.
JP10333595A 1995-04-27 1995-04-27 Thin film transistor and liquid crystal display device using the same Expired - Fee Related JP2820064B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10333595A JP2820064B2 (en) 1995-04-27 1995-04-27 Thin film transistor and liquid crystal display device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10333595A JP2820064B2 (en) 1995-04-27 1995-04-27 Thin film transistor and liquid crystal display device using the same

Publications (2)

Publication Number Publication Date
JPH08297299A true JPH08297299A (en) 1996-11-12
JP2820064B2 JP2820064B2 (en) 1998-11-05

Family

ID=14351294

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2820064B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2322968B (en) * 1997-03-04 1999-09-29 Lg Electronics Inc Thin-film transistor and method of making same
US6008869A (en) * 1994-12-14 1999-12-28 Kabushiki Kaisha Toshiba Display device substrate and method of manufacturing the same
US6333518B1 (en) 1997-08-26 2001-12-25 Lg Electronics Inc. Thin-film transistor and method of making same
JP2010087068A (en) * 2008-09-30 2010-04-15 Hitachi Ltd Display

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6008869A (en) * 1994-12-14 1999-12-28 Kabushiki Kaisha Toshiba Display device substrate and method of manufacturing the same
GB2322968B (en) * 1997-03-04 1999-09-29 Lg Electronics Inc Thin-film transistor and method of making same
US6340610B1 (en) 1997-03-04 2002-01-22 Lg. Philips Lcd Co., Ltd Thin-film transistor and method of making same
US6333518B1 (en) 1997-08-26 2001-12-25 Lg Electronics Inc. Thin-film transistor and method of making same
US6573127B2 (en) 1997-08-26 2003-06-03 Lg Electronics Inc. Thin-film transistor and method of making same
JP2010087068A (en) * 2008-09-30 2010-04-15 Hitachi Ltd Display

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