JPH088255A - Wiring structure for semiconductor device and transistor array for display element - Google Patents

Abstract

PURPOSE:To provide a wiring structure for semiconductor devices having a low resistance and chemical resistance, and a transistor array for display elements having such a wiring structure. CONSTITUTION:A wiring 1 consists of a first pattern 1a and a second pattern 1b. The first pattern 1a is made of a material containing at least Al as a major component, and continuously formed on the surface of a substrate 2. The second pattern 1b is made of low-resistance semiconductor or metal, and continuously formed on the substrate 2 in such a way that it covers the first pattern 1a. In this wiring structure, the first pattern 1a is covered with the second pattern 1b, which prevents the formation of hillocks and makes the wiring resistant to chemicals. In addition, the material of the first pattern 1a reduces the resistance of the wiring 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor device and a transistor array for a display device having the wiring structure.

[0002]

2. Description of the Related Art In a conventional thin film transistor array, for example, as shown in FIG.
And the auxiliary wiring 52 is formed. Auxiliary wiring 52
Is, for example, a capacitance (Cs) line used for a display element or a lead line from a power source (not shown).

An insulating layer 53 is formed on the substrate 50 so as to cover the gate wiring 51 and the auxiliary wiring 52, and the active layer 5 is formed on the insulating layer 53 on the gate wiring 51.
4 are formed. The source wiring 55 is connected to the source side of the active layer 54, and the drain wiring 56 is connected to the drain side thereof. Further, an insulating protective film 57 is formed so as to cover them.

In a liquid crystal display device provided with a thin film transistor array having the above-mentioned structure, the screen size is increasing in order to make it easier to see. Further, the number of display pixels is increased in order to achieve high definition. Therefore, the gate wiring 51
Also, the resistance value of the auxiliary wiring 52, the transistor capacitance, and the parasitic capacitance increase, and the signal propagation delay associated therewith becomes an important issue.

Of these, the gate wiring 51 and the auxiliary wiring 5
Measures for lowering the resistance value of 2 are easy to take, and for example, the following attempts have been made. One is a method of adopting, as a material of the gate wiring 51 and the auxiliary wiring 52, an alloy having a resistance value lower than that of a simple substance such as an alloy of molybdenum-tantalum (hereinafter, referred to as Mo-Ta). Another one is
As a material for the gate wiring 51 and the auxiliary wiring 52, aluminum (hereinafter, referred to as A
1) or a metal containing Al as a main component.

[0006]

However, Mo-T
Even if the alloy of a was used, the low resistance values of the gate wiring and the auxiliary wiring were still insufficient. When Al or a metal material containing Al as a main component is used, hillocks are generated on the surface of the metal material when heat treatment is performed,
There was a problem that the interlayer breakdown voltage deteriorates.

As a measure for preventing the generation of hillocks, there is a method of forming a wiring by hardening the surface of a metal material by anodic oxidation, for example. Alternatively, there is a method in which another metal is continuously formed on a metal material and then continuously etched to form a wiring. However, in any of the methods, there is a problem in that the lateral side of the wiring is eroded by the acid used in the subsequent cleaning process or etching process.

The present invention has been made to solve the above problems, and provides a wiring structure of a semiconductor device having a low resistance value and chemical resistance, and a transistor array for a display device having the wiring structure. It is an object.

[0009]

The wiring structure of the semiconductor device of the present invention (hereinafter referred to as the present invention structure) is at least Al.
A first pattern formed of a material containing as a main component and formed in a continuous or discontinuous state on the surface of a substrate, and a low resistance semiconductor or metal that covers and continues the first pattern. This is a structure including a second pattern formed on the substrate. The display element transistor array of the present invention (hereinafter referred to as the device of the present invention) has a gate wiring and an auxiliary wiring, and the gate wiring and the auxiliary wiring have the above-described structure of the present invention. .

[0010]

In the structure of the present invention, the resistance value of the wiring is lowered by the Al of the first pattern. Further, since the first pattern is covered with the second pattern, hillocks that are likely to occur on the surface of the first pattern due to the second pattern are suppressed. Further, the first pattern, which is more likely to be eroded, is not eroded by the second pattern as well. Further, in the device of the present invention, the resistance value of the gate wiring and the auxiliary wiring becomes low.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the structure of the present invention and the device of the present invention will be described below with reference to the drawings. 1 is a schematic sectional view of a first embodiment of the structure of the present invention, and FIG. 2 is a reduced plan view thereof. As shown in the drawing, the wiring 1 of the first embodiment has a first pattern 1a formed on the surface of a base 2 and a first pattern 1a.
And a second pattern 1b formed on the substrate 2 so as to cover the base.

The first pattern 1a is made of a material containing at least Al as a main component. Then, as shown in FIG. 2, it is formed in a continuous state on the surface of the substrate 2. The first pattern 1a is formed to have a thickness of 300 nm or less,
The thickness is desirably 100 nm or less.

The second pattern 1b is made of a low resistance semiconductor or a metal material. Examples of the low resistance semiconductor include amorphous silicon containing impurities and polycrystalline silicon containing impurities. For the metal material, for example, C
Refractory metals such as r, Ta, Ti, Mo, and W, and alloys thereof are included. Then, such a material is formed on the base 2 so as to cover the first pattern 1a and to be continuous.

In the structure of the wiring 1 described above, the first pattern 1a on the surface of the substrate 2 is completely covered with the second pattern 1b. Therefore, hillocks are not generated in the first pattern 1a even if the heat treatment is performed. In addition, the wiring 1 may be formed by an acid used in a cleaning process or an etching process.
The sides of the are not eroded. Moreover, the resistance value of the wiring 1 itself is lowered by the first pattern 1a containing at least a low resistance Al as a main component.

Therefore, according to the first embodiment, there is no hillock generation, and the wiring 1 is chemically resistant and has a low resistance value.
Can be realized. Therefore, by using such a structure of the wiring 1, it becomes possible to obtain a semiconductor device having high electrical reliability.

Next, a second embodiment of the structure of the present invention will be described with reference to the plan view shown in FIG. As shown in the figure, the structure of the wiring 3 of this embodiment is different from that of the above embodiment in that the first pattern 3a is discontinuously formed on the substrate 1.
For example, when the element 4 is provided on the wiring 3 at a portion indicated by a chain double-dashed line in the drawing, the first pattern 3a is provided on a portion excluding the element 4 forming portion.
To form. Then, the second pattern 3b is continuously formed on the base 2 while covering the first pattern 3a.

Also in this structure of the wiring 3, the first pattern 3a is formed.
Are completely covered by the second pattern 3b. Therefore, the wiring 3 has no hillocks and has chemical resistance. Moreover, the wiring 3 having a low resistance value is formed by the first pattern 3a containing at least a main component of Al having a low resistance.

Further, in the wiring 3, the first pattern 3a is provided in a portion other than the portion where the element 4 is formed. Therefore, in the structure in which a part of the wiring is usually the gate electrode of the element, the gate electrode has the same structure as the conventional one. be able to. Therefore, even if the material of the first pattern 3a and the material of the second pattern 3b react with each other in the thermal process, the threshold change of the element due to the work function change of the material before and after the reaction which can be considered in such a case. It is possible to avoid undesired phenomena. Further, since the material of the first pattern 3a is not diffused, the quality of the film forming the element 4 is not deteriorated by the metal of the material forming the first pattern 3a. Therefore, according to the second embodiment, a semiconductor device having higher electrical reliability can be realized.

Next, the device of the present invention will be described. FIG.
FIG. 3 is a sectional view showing a first embodiment of the device of the present invention, showing an inverted stagger type thin film transistor array. In the figure, reference numeral 11 is a substrate made of, for example, glass, and a gate wiring 12 and an auxiliary wiring 13 are formed on the surface of the substrate 11. Here, the auxiliary wiring 13 indicates a capacitance (Cs) line, a lead line from a power source (not shown), and the like.

The gate wiring 12 and the auxiliary wiring 13 have the same structure as the wiring 1 or the wiring 3 of the above embodiment. Therefore, the gate wiring 12 has the first pattern 12a.
And the second pattern 12b, the auxiliary wiring 13 is the first pattern 1
3a and the second pattern 13b. An insulating layer 14, an active layer 15, a source wiring 16, a drain wiring 17 and the like are provided on the gate wiring 12 and the auxiliary wiring 13 like the conventional inverted stagger type.

That is, the insulating layer 14 is formed on the base 11 in a state of covering the gate wiring 12 and the auxiliary wiring 13. Further, the active layer 15 is provided, for example, in an island shape on the insulating layer 14 on the gate wiring 12. Insulation layer 1
The source wiring 1 is formed on the surface 4 of the active layer 15 so as to be connected to the source side thereof, and the drain wiring 17 is formed so as to be connected to the drain side of the active layer 15.

On the other hand, the active layer 15 above the gate wiring 12
A stopper insulating layer 18 is formed on the top. An insulating protective film 19 is provided so as to cover the entire surface of such a thin film transistor array.

In this embodiment, the gate wiring 12 and the auxiliary wiring 13 have a wiring structure in which the first patterns 12a and 13a are covered with the second patterns 12b and 13b, respectively. Therefore, hillocks do not occur, and the wiring has chemical resistance. Further, the resistance value is reduced by the first patterns 12a and 13a containing at least a low resistance Al as a main component. Therefore, a thin film transistor array having no signal propagation delay can be obtained.

A specific example of forming the first embodiment will be described below. First, Al was deposited to a thickness of about 50 nm on the surface of the substrate 1 made of glass by a sputtering method. Then
Al was patterned by lithography and etching to form a first pattern 12a of the gate wiring 12 and a first pattern 13a of the auxiliary wiring 13.

Next, n ⁺ amorphous silicon was deposited to a thickness of about 50 nm by the plasma CVD method. Then, the first pattern 12a is formed by lithography and etching.
Patterning was made thicker by about 1 μm than the wiring width of 13a to form the second pattern 12b of the gate wiring 12 and the second pattern 13b of the auxiliary wiring 13.

Next, it was immersed in buffered hydrofluoric acid or dilute hydrofluoric acid for cleaning, and then the insulating layer 14 was formed by the CVD method. Next, amorphous silicon was deposited on the insulating layer 14 by the CVD method. After that, amorphous silicon was polycrystallized by a laser crystallization method, and the polycrystal silicon was patterned into islands by lithography and etching to form an active layer 15.

Subsequently, silicon nitride was deposited on the active layer 15 by the CVD method. Then, patterning was performed by lithography and etching to form the stopper insulating layer 18. Further, ion shower was performed using the stopper insulating layer 18 as a mask to implant impurities into the source and drain regions of the active layer 15.

Next, Al was deposited on the entire surface by a sputtering method, and then patterned by lithography and etching to form a source wiring 16 and a drain wiring 17. Then, C so as to cover these entire surfaces
The insulating protective film 19 was formed by the VD method.

In the thin film transistor array formed as described above, the gate wiring 12 and the auxiliary wiring 13 are formed by buffer hydrofluoric acid, dilute hydrofluoric acid, and Al etching solution.
No abnormality was found in appearance. Also, there was no abnormality in the wiring resistance value. From this result, it was confirmed that the low resistance gate wiring 12 and the auxiliary wiring 13 which do not generate hillocks and have chemical resistance can be obtained.

In the above embodiments, the reverse stagger type thin film transistor is described. However, the structure of the present invention can be applied to the gate wiring and auxiliary wiring of the display element transistor arrays of various types other than the reverse stagger type. .

For example, as shown in FIG. 5, in a planar type thin film transistor array, an active layer 22 is formed on a substrate 21. A gate wiring 24 is formed on the active layer 22 via a gate insulating layer 23. The gate wiring 24 has a first pattern 24a similar to the gate wiring 12 of the first embodiment.
And a second pattern 24b. Then, the insulating layer 25, the contact hole 26, the source wiring 27, the drain wiring 28, and the insulating protective film 19 are sequentially formed by a method similar to the conventional method, whereby a thin film transistor array with no signal propagation delay can be obtained.

[0032]

As described above, in the structure of the present invention, since the first pattern is completely covered by the second pattern, it is possible to realize a wiring which is free from hillocks and has chemical resistance. Moreover, since the first pattern is formed of a material having at least a main component of low resistance Al,
Wiring having a low resistance value can be realized. Further, in the device of the present invention, since the gate wiring and the auxiliary wiring have the above-mentioned structure of the present invention, the wiring resistance value becomes low. Therefore, a highly reliable device with no signal propagation delay can be realized.

[Brief description of drawings]

FIG. 1 is a sectional view of a first embodiment of the structure of the present invention.

FIG. 2 is a reduced plan view of the first embodiment of the structure of the present invention.

FIG. 3 is a plan view of a second embodiment of the structure of the present invention.

FIG. 4 is a sectional view of a first embodiment of the device of the present invention.

FIG. 5 is a modification of the first embodiment of the device of the present invention.

FIG. 6 is a cross-sectional view of a conventional thin film transistor array for a display element.

[Explanation of symbols]

1, 3 Wirings 1a, 3a, 12a, 13a, 24a 1st pattern 1b, 3b, 12b, 13b, 24b 2nd pattern 2, 11, 21 Base | substrate 12, 24 Gate wiring 13 Auxiliary wiring

Claims (2)

[Claims] 1. A first pattern made of a material containing at least aluminum as a main component and formed in a continuous or discontinuous state on a surface of a substrate, and a low resistance semiconductor or a metal. A wiring structure for a semiconductor device, comprising a second pattern formed on the base in a state of covering and continuing the pattern. 2. A display element transistor array having a gate wiring and an auxiliary wiring, wherein the gate wiring and the auxiliary wiring form the wiring structure of the semiconductor device according to claim 1. Transistor array.